Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel, and belongs to the technical field of display, the array substrate comprises a substrate, a first insulating layer, a first transparent electrode layer and a first metal layer, the first insulating layer comprises a first insulator layer and a second insulator layer, the first insulator layer and the second insulator layer are respectively provided with a first opening and a second opening, and the first opening and the second opening are communicated with each other. The first opening and the second opening are communicated to form a first groove, and the side wall of the second insulator layer exceeds the side wall of the first insulator layer to form a first undercut structure; the first transparent electrode layer is separated at the first undercut structure to form a first cushion layer and a first common electrode, the first cushion layer is arranged in the first groove, and the first common electrode is arranged on the second insulator layer; the first metal layer comprises a first electrode which is arranged on the side, away from the substrate, of the first cushion layer. The production cost can be reduced, and the device stability of the transistor can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] In the array substrate of the relevant solution, two normal photomasks are required to complete the patterning process of the first metal layer and the common electrode layer. The production cost of two normal photomasks is high, which leads to the high cost of the display panel.

[0003] On the other hand, during the patterning process, due to the influence of process parameters and conditions, the patterned electrodes formed by etching the first metal layer and the common electrode layer with etchant will suffer from linewidth loss (CD Loss). Linewidth loss occurs because the edges of the film layer are etched thinner than the middle of the film layer. Linewidth loss leads to uncontrollable linewidth of the patterned electrodes, thereby affecting the device stability of the transistor. Summary of the Invention

[0004] The purpose of this application is to provide an array substrate and a display panel that can reduce production costs and improve the device stability of transistors.

[0005] To solve the above problems, the technical solution of this application is as follows: In a first aspect, this application proposes an array substrate having a pixel region, the array substrate comprising: Substrate; The first insulating layer includes a first insulator layer and a second insulator layer stacked sequentially on one side of the substrate. A first opening is formed in the first insulator layer, and a second opening is formed in the second insulator layer. The first opening and the second opening communicate to form a first groove. The first groove is located in the pixel area. The sidewall of the second insulator layer near the second opening extends beyond the sidewall of the first insulator layer near the first opening, forming a first undercut structure. A first transparent electrode layer is disposed on the side of the second insulator layer away from the first insulator layer. The portion of the first transparent electrode layer located in the pixel area is separated at the first undercut structure to form a first pad layer and a first common electrode. The first pad layer is disposed within the first groove, and the first common electrode is disposed on the side of the second insulator layer away from the first insulator layer. The first metal layer includes a first electrode located in the pixel region, the first electrode being located within the first groove and disposed on the side of the first pad layer away from the substrate.

[0006] In one embodiment of this application, the array substrate further has a border area, which is located on at least one side of the pixel area; A third opening is formed in the first insulator layer, and a fourth opening is formed in the second insulator layer. The third opening and the fourth opening communicate to form a plurality of second grooves. The second grooves are located in the frame area. The sidewall of the second insulator layer near the fourth opening extends beyond the sidewall of the first insulator layer near the third opening, forming a second undercut structure. The first metal layer is located in a portion of the frame area and is separated at the second undercut structure to form multiple fan-out traces. The fan-out traces are located on the side of the second insulator layer away from the first insulator layer, and the gap between two adjacent fan-out traces overlaps with the second groove.

[0007] In one embodiment of this application, in a plan view of the array substrate, the spacing between two adjacent fan-out traces is greater than or equal to 0.3 micrometers, and the width of the fan-out trace is greater than or equal to 1.5 micrometers.

[0008] In one embodiment of this application, the array substrate further includes: A second insulating layer is disposed on the side of the first insulating layer away from the substrate, and covers the first transparent electrode layer and the first metal layer; A semiconductor layer is disposed on the side of the second insulating layer away from the substrate and located in the pixel region. The semiconductor layer includes a first conductor portion, a channel, and a second conductor portion connected in sequence. The first conductor portion overlaps with the edge of the first common electrode, and the channel overlaps with the first electrode. A third insulating layer is disposed on the side of the semiconductor layer away from the substrate. The third insulating layer has a third groove and a fourth groove, which are located in the pixel area. The third groove exposes the first conductor portion, and the fourth groove exposes the second conductor portion. The second metal layer includes a second electrode and a third electrode. The second electrode is disposed in the third groove and connected to the first conductor portion. The third electrode is disposed in the fourth groove and connected to the second conductor portion.

[0009] In one embodiment of this application, the third insulating layer includes a third insulator layer and a fourth insulator layer sequentially stacked on the side of the semiconductor layer away from the substrate. A fifth opening and a sixth opening are formed in the third insulator layer at intervals. A seventh opening and an eighth opening are formed in the fourth insulator layer at intervals. The fifth opening communicates with the seventh opening to form the third groove. The sixth opening communicates with the eighth opening to form the fourth groove. The sidewall of the fourth insulator layer near the seventh opening extends beyond the sidewall of the third insulator layer near the fifth opening, forming a third undercut structure; The sidewall of the fourth insulator layer near the eighth opening extends beyond the sidewall of the third insulator layer near the sixth opening, forming a fourth undercut structure; The second metal layer is separated at the third undercut structure and the fourth undercut structure to form the second electrode and the third electrode.

[0010] In one embodiment of this application, the third insulating layer further includes a fifth insulating layer disposed on the side of the third insulating layer near the semiconductor layer; The fifth insulator layer has a ninth opening and a tenth opening that are spaced apart. The ninth opening, the fifth opening, and the seventh opening are connected to form the third groove; The tenth opening, the sixth opening, and the eighth opening are connected to form the fourth groove; The material of the third insulator layer contains nitrogen and silicon, while the materials of the fourth and fifth insulator layers contain oxygen and silicon.

[0011] In one embodiment of this application, the array substrate further includes: The fourth insulating layer includes a sixth insulator layer and a seventh insulator layer sequentially stacked on the side of the third insulating layer away from the substrate. A first via is formed in the sixth insulator layer, exposing the second electrode. A plurality of spaced eleventh openings are formed in the seventh insulator layer, overlapping the first common electrode, and one of the eleventh openings communicates with the first via. The pixel electrode includes a first connecting portion and a plurality of branch electrodes. The first connecting portion is electrically connected to the plurality of branch electrodes respectively. The first connecting portion is disposed in the first via and connected to the second electrode. The branch electrodes are disposed in the eleventh opening.

[0012] In one embodiment of this application, the fourth insulating layer further includes an eighth insulator layer, which is disposed on the side of the seventh insulator layer away from the sixth insulator layer. The eighth insulator layer has a plurality of spaced twelfth openings, which communicate with the eleventh opening to form fifth grooves. The plurality of fifth grooves are located in the pixel area. The sidewall of the eighth insulator layer near the twelfth opening extends beyond the sidewall of the seventh insulator layer near the eleventh opening, forming a fifth undercut structure. The pixel electrode is separated at the fifth undercut structure to form a plurality of the branch electrodes.

[0013] In one embodiment of this application, a thirteenth opening is further formed in the first insulator layer, and a fourteenth opening is further formed in the second insulator layer. The thirteenth opening and the fourteenth opening are connected to form a sixth groove. The sixth groove is located on one side of the first groove and is formed by the same photomask. The sidewall of the second insulator layer near the fourteenth opening extends beyond the sidewall of the first insulator layer near the thirteenth opening, forming a sixth undercut structure; The first transparent electrode layer is separated at the sixth undercut structure to form a second pad layer, and the second pad layer is disposed in the sixth groove; The first metal layer is separated at the sixth undercut structure to form a first transfer electrode. The first transfer electrode is located in the sixth groove and is disposed on the side of the second pad layer away from the substrate. The first adapter electrode is electrically connected to the first common electrode.

[0014] In one embodiment of this application, a second via and a third via are formed in the second insulating layer at intervals, the second via exposing the first common electrode and the third via exposing the first transition electrode; The third insulator layer also has a fifteenth and a sixteenth opening spaced apart, and the fourth insulator layer also has a seventeenth and an eighteenth opening spaced apart. The second through hole, the fifteenth opening, and the seventeenth opening are connected to form a first transition hole; The third through hole, the sixteenth opening, and the eighteenth opening are connected to form a second transition hole; The first adapter hole, the second adapter hole, the third groove, and the fourth groove are formed by the same photomask. The second metal layer further includes a second transfer electrode and a third transfer electrode, wherein the second transfer electrode is electrically connected to the third transfer electrode; The second adapter electrode is disposed in the first adapter hole and connected to the first common electrode; The third adapter electrode is disposed in the second adapter hole and is connected to the first adapter electrode.

[0015] In one embodiment of this application, a fourth via and a fifth via are further formed in the sixth insulator layer, the fourth via exposing the second transition electrode and the fifth via exposing the third transition electrode; The seventh insulator layer also has a nineteenth opening, which is connected to the fourth through hole and the fifth through hole respectively; The first via, the fourth via, the fifth via, the eleventh opening, and the nineteenth opening are formed through the same photomask. The pixel electrode further includes a second connecting portion, which is disposed in the nineteenth opening, the fourth via, and the fifth via, and connects the second adapter electrode and the third adapter electrode.

[0016] In one embodiment of this application, the array substrate further includes: The fifth insulating layer includes a ninth insulator layer and a tenth insulator layer stacked sequentially on the side of the fourth insulating layer away from the substrate. A sixth via is formed in the ninth insulator layer, and the sixth via exposes the second connection portion. A twentieth opening is formed in the tenth insulator layer, and the twentieth opening communicates with the sixth via. The second transparent electrode layer includes a second connecting portion and a second common electrode. The second common electrode is disposed in the second tenth opening, and the second connecting portion is disposed in the sixth through hole and connects the second common electrode and the second connecting portion.

[0017] Secondly, this application proposes a display panel including an array substrate, the array substrate comprising: Substrate; The first insulating layer includes a first insulator layer and a second insulator layer stacked sequentially on one side of the substrate. A first opening is formed in the first insulator layer, and a second opening is formed in the second insulator layer. The first opening and the second opening communicate to form a first groove. The first groove is located in the pixel area. The sidewall of the second insulator layer near the second opening extends beyond the sidewall of the first insulator layer near the first opening, forming a first undercut structure. A first transparent electrode layer is disposed on one side of the substrate. The portion of the first transparent electrode layer located in the pixel area is separated at the first undercut structure to form a first pad layer and a first common electrode. The first pad layer is disposed within the first groove, and the first common electrode is disposed on the side of the second insulator layer away from the first insulator layer. The first metal layer includes a first electrode located in the pixel region, the first electrode being located within the first groove and disposed on the side of the first pad layer away from the substrate.

[0018] In this application, on the one hand, the first insulating layer can be patterned using a first normal photomask to form a first groove with a first undercut structure. The first metal layer and the first transparent electrode layer subsequently formed on the first insulating layer are separated at the first undercut structure, forming the first electrode and the first common electrode respectively. This eliminates the need for additional photomasks and etching methods to form the first electrode and the first common electrode. Therefore, this application uses only one photomask to pattern the first metal layer and the first transparent electrode layer, reducing the number of photomasks required and lowering production costs. On the other hand, since the first metal layer and the first transparent electrode layer are not formed by etching, the linewidth loss of the first electrode and the first common electrode can be reduced, solving the linewidth loss problem caused by etching with etchants. This makes the linewidth of the first electrode and the first common electrode controllable, improving the device stability of the transistor. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0021] Figure 1 This is a schematic diagram of the first metal layer and the first transparent electrode layer in related technologies; Figure 2 This is another schematic diagram of the first metal layer and the first transparent electrode layer in the related technology; Figure 3 This is a first schematic diagram of the array substrate of this application; Figure 4 This is a schematic diagram of step S11 in a method for manufacturing an array substrate according to this application; Figure 5 This is a schematic diagram of step S12 in a method for manufacturing an array substrate according to this application; Figure 6 This is a schematic diagram of step S13 in a method for manufacturing an array substrate according to this application; Figure 7 This is a schematic diagram of step S14 in a method for manufacturing an array substrate according to this application; Figure 8 This is a schematic diagram of step S15 in a method for manufacturing an array substrate according to this application; Figure 9This is a schematic diagram of step S16 in a method for manufacturing an array substrate according to this application; Figure 10 This is a schematic diagram of step S17 in a method for manufacturing an array substrate according to this application; Figure 11 This is a schematic diagram of step S18 in a method for manufacturing an array substrate according to this application; Figure 12 This is a schematic diagram of step S19 in a method for manufacturing an array substrate according to this application; Figure 13 This is a schematic diagram of the portion of the first metal layer located in the border area of ​​this application; Figure 14 yes Figure 13 A sectional view at section line B-B'; Figure 15 It is a comparison diagram of the fan-out routing in the design of related technologies and the actual fan-out routing; Figure 16 This is a second schematic diagram of the array substrate of this application; Figure 17 This is a schematic diagram of step S21 in a method for manufacturing an array substrate according to this application; Figure 18 This is a schematic diagram of step S22 in a method for manufacturing an array substrate according to this application; Figure 19 This is a schematic diagram of step S23 in a method for manufacturing an array substrate according to this application; Figure 20 This is a schematic diagram of step S24 in a method for manufacturing an array substrate according to this application; Figure 21 This is a schematic diagram of step S31 in a method for manufacturing an array substrate according to this application; Figure 22 This is a schematic diagram of step S32 in a method for manufacturing an array substrate according to this application; Figure 23 This is a schematic diagram of step S33 in a method for manufacturing an array substrate according to this application; Figure 24 This is a third schematic diagram of the array substrate of this application; Figure 25 This is a schematic diagram of step S41 in a method for manufacturing an array substrate according to this application; Figure 26 This is a schematic diagram of step S42 in a method for manufacturing an array substrate according to this application; Figure 27 This is a schematic diagram of step S43 in a method for manufacturing an array substrate according to this application; Figure 28This is a fourth schematic diagram of the array substrate of this application; Figure 29 This is the fifth schematic diagram of the array substrate of this application; Figure 30 This is the sixth schematic diagram of the array substrate of this application.

[0022] Explanation of reference numerals in the attached figures: 100, Array substrate; AA, Pixel area; AA1, Aperture area; AA2, Non-aperture area; NA, Border area; PR1, first organic photoresist material; PR2, second organic photoresist material; PR21, first photoresist; PR22, second photoresist; PR3, third organic photoresist material; 1. Substrate; K1, First opening; K2, Second opening; K3, Third opening; K4, Fourth opening; K5, Fifth opening; K6, Sixth opening; K7, Seventh opening; K8, Eighth opening; K9, Ninth opening; K10, Tenth opening; K11, Eleventh opening; K12, Twelfth opening; K13, Thirteenth opening; K14, Fourteenth opening; K15, Fifteenth opening; K16, Sixteenth opening; K17, Seventeenth opening; K18, Eighteenth opening; K19, Nineteenth opening; C1, First groove; C2, Second groove; C3, Third groove; C4, Fourth groove; C5, Fifth groove; C6, Sixth groove; U1, First undercut structure; U2, Second undercut structure; U3, Third undercut structure; U4, Fourth undercut structure; U5, Fifth undercut structure; U6, Sixth undercut structure; D1, First via; D2, Second via; D3, Third via; D4, Fourth via; D5, Fifth via; P1, First adapter hole; P2, Second adapter hole; PV1, first insulating layer; PV11, first insulator layer; PV12, second insulator layer; 2. First transparent electrode layer; 21. First padding layer; 22. First common electrode; 23. Third padding layer; 24. Second padding layer; M1, First metal layer; M11, First electrode; M12, First electrode to be etched; M13, Fan-out trace; M14, First adapter electrode; PV2, second insulating layer; 3. Semiconductor layer; 31. First conductor portion; 32. Channel; 33. Second conductor portion; PV3, third insulating layer; PV31, fifth insulating layer; PV32, third insulating layer; PV33, fourth insulating layer; M2, second metal layer; M21, second electrode; M22, third electrode; M23, second transfer electrode; M24, third transfer electrode; PV4, fourth insulating layer; PV41, sixth insulating layer; PV42, seventh insulating layer; PV43, eighth insulating layer; 5. Pixel electrode; 51. First connecting part; 52. Branch electrode; 53. Second connecting part. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0024] Please see Figure 1 In one related technology, two normal photomasks are required to complete the patterning of the first metal layer M1' and the common electrode layer 2'. The high cost of two normal photomasks leads to the high cost of the display panel.

[0025] On the other hand, during the patterning process, due to the influence of process parameters and conditions, the patterned electrodes formed by etching the first metal layer M1' and the common electrode layer 2' with an etchant will suffer from linewidth loss (CD Loss). Linewidth loss occurs because the edges of the film are etched thinner than the middle of the film, resulting in a loss of linewidth. Linewidth loss leads to uncontrollable linewidth of the patterned electrodes, thereby affecting the device stability of the transistor.

[0026] Please see Figure 2 In another related technology, a half-tone mask (HTM) is required to pattern the first metal layer M1' and the common electrode layer 2'. Although this reduces the number of masks used, the actual cost reduction is limited because half-tone masks are more expensive than regular masks.

[0027] On the other hand, when using a halftone mask, an etchant is still required to complete the etching. The etchant will inevitably etch the edges of the first metal layer M1' and the common electrode layer 2', causing the edges of the first metal layer M1' and the common electrode layer 2' to be etched thinner than the middle of the film, resulting in linewidth loss.

[0028] In both methods described above, the locations of the first electrode layer M1' and the common electrode layer 2' will form a raised morphology, creating a step difference with the substrate and affecting the flatness of the upper film layer, thus impacting the display effect of the display panel. Specifically, in the second technology, the step difference between the first metal layer M1' and the substrate is greater due to the presence of a portion of the common electrode layer 2' underneath, resulting in a greater impact on the flatness of the upper film layer. Although a flattening layer can be placed on top to reduce the step difference, the flatness performance of the flattening layer is limited and cannot completely eliminate the step difference, thus affecting the display panel.

[0029] This application discloses a display panel applied to a display device. The display device may be a tablet computer, e-reader, electronic display screen, laptop computer, mobile phone, augmented reality (AR) / virtual reality (VR) device, media player, wearable device, digital camera, car navigation system, etc.

[0030] Optionally, the display panel is a liquid crystal display panel.

[0031] Optionally, the display panel includes an array substrate 100 and an opposing substrate disposed opposite each other, and a liquid crystal layer located between the array substrate 100 and the opposing substrate.

[0032] Please see Figure 3 The display panel has pixel areas AA. The array substrate 100 includes a substrate 1, a first insulating layer PV1, a first transparent electrode layer 2, and a first metal layer M1.

[0033] The first insulating layer PV1 includes a first insulator layer PV11 and a second insulator layer PV12 sequentially stacked on one side of the substrate 1. A first opening K1 is formed in the first insulator layer PV11. A second opening K2 is formed in the second insulator layer PV12. The first opening K1 and the second opening K2 communicate to form a first groove C1. The first groove C1 is located in the pixel area AA.

[0034] The sidewall of the second insulator layer PV12 near the second opening K2 extends beyond the sidewall of the first insulator layer PV11 near the first opening K1, forming the first undercut structure U1.

[0035] The first transparent electrode layer 2 is disposed on one side of the substrate 1. The portion of the first transparent electrode layer 2 located in the pixel area AA is separated at the first undercut structure U1, forming a first pad layer 21 and a first common electrode 22. The first pad layer 21 is disposed in the first groove C1. The first common electrode 22 is disposed on the side of the second insulator layer PV12 away from the first insulator layer PV11.

[0036] The first metal layer M1 includes a first electrode M11 located in the pixel region AA. The first electrode M11 is located in the first groove C1 and is disposed on the side of the first pad layer 21 away from the substrate 1.

[0037] In this application, on the one hand, the first insulating layer can be patterned using a first normal photomask to form a first groove with a first undercut structure. The first metal layer and the first transparent electrode layer subsequently formed on the first insulating layer are separated at the first undercut structure, forming the first electrode and the first common electrode respectively. This eliminates the need for additional photomasks and etching methods to form the first electrode and the first common electrode. Therefore, this application uses only one photomask to pattern the first metal layer and the first transparent electrode layer, reducing the number of photomasks required and lowering production costs. On the other hand, since the first metal layer and the first transparent electrode layer are not formed by etching, the linewidth loss of the first electrode and the first common electrode can be reduced, solving the linewidth loss problem caused by etching with etchants. This makes the linewidth of the first electrode and the first common electrode controllable, improving the device stability of the transistor.

[0038] In this application, on one hand, a first organic photoresist material PR1 is formed on the second insulator layer PV12. The first organic photoresist material PR1 is exposed and developed using a first normal photomask to pattern the first insulating layer PV1, thereby forming a first groove C1 with a first undercut structure U1 in the first insulating layer PV1. The first transparent electrode layer 2 is separated at the first undercut structure U1, forming a first pad layer 21 located in the first groove C1 and a first common electrode 22 located on the second insulator layer PV12. The first metal layer M1 is separated at the first undercut structure U1, forming a first pad layer 21 located in the first groove C1 and a first electrode M12 to be etched located on the first common electrode 22. During the patterning process of the first transparent electrode layer 2 and the first metal layer M1, the patterning is completed through the first undercut structure U1, eliminating the need for etching with an etchant as in related technologies, reducing the linewidth loss of the first pad layer 21, the first electrode M11, and the first common electrode 22, and improving the device stability of the transistor.

[0039] On the other hand, after forming the first metal layer M1, a second organic photoresist material PR2 with leveling properties is coated on one side of the substrate 1. Because the leveling second organic photoresist material PR2 flows from a higher potential to a lower potential, the thickness of the second organic photoresist material PR2 above the first electrode to be etched M12 is less than the thickness of the second organic photoresist material PR2 above the first electrode M11. The second organic photoresist material PR2 is then processed using a vacuum chamber drying (VCD) process to evaporate the solvent in the second organic photoresist material PR2, forming a first photoresist PR21 on the first electrode M11 and a second photoresist PR22 on the first electrode to be etched M12. Because the step difference between the upper surface of the first electrode M11 and the upper surface of the first electrode to be etched M12 is large, the first photoresist PR21 and the second photoresist PR22 are separated by this step difference, and the thickness of the second photoresist PR22 is less than the thickness of the first photoresist PR21. An ashing process is used on the first photoresist PR21 and the second photoresist PR22. Since the thickness of the first photoresist PR21 is greater than that of the second photoresist PR22, a portion of the first photoresist PR21 can still be retained when the second photoresist PR22 is completely removed by the ashing process. The first electrode M12 to be etched is removed by etching. Since the first electrode M11 is covered by the first photoresist PR21, the first electrode M11 is not etched. After the first electrode M12 to be etched is removed, the first photoresist PR21 on the first electrode M11 is removed by a photoresist stripping process. In the above process, only one photomask is used when forming the first groove C1, which can reduce the number of photomasks used and reduce production costs.

[0040] It should be understood that, compared to another related technology, although both use a photomask, the photomask in this application is a lower-cost ordinary photomask, while the photomask in the other related technology is a higher-cost halftone photomask. The photomask in this application has a relatively low cost. The second organic photoresist material PR2 can be SR210 or an organic planarization material.

[0041] Meanwhile, compared with another related technology, the first electrode M11 and the first common electrode 22 of this application are formed by being separated by the first undercut structure U1 rather than by etching, which can reduce the linewidth loss of the first electrode M11 and the first common electrode 22.

[0042] Meanwhile, compared with another related technology, the first electrode M11 of this application does not form a protruding morphology, but rather forms a recessed morphology with the first groove C1. The planarization layer has a higher ability to fill recessed morphologies than to fill protruding morphologies. Therefore, this application can improve the flatness of the upper film layer, reduce step differences, and improve the display effect of the display panel.

[0043] Optionally, the pixel area AA includes an opening area AA1 and a non-opening area AA2. The opening area AA1 is used to house the pixel electrode 5 and has high light transmittance. The non-opening area AA2 is used to house traces or transistors and other devices, and has low light transmittance. In this embodiment, the first common electrode 22 is located in the opening area AA1, and the first electrode M11 is located in the non-opening area AA2.

[0044] Optionally, the material of the first insulator layer PV11 is different from the material of the second insulator layer PV12.

[0045] In this embodiment, since the materials of the first insulator layer PV11 and the second insulator layer PV12 are different, the etching selectivity of the first insulator layer PV11 and the second insulator layer PV12 is different in the same etchant, thereby forming the first undercut structure U1.

[0046] Optionally, the first insulator layer PV11 is made of silicon and nitrogen, and the material of the first insulator layer PV11 can be silicon nitride. The second insulator layer PV12 is made of silicon and oxygen. The material of the second insulator layer PV12 can be silicon oxide or silicon dioxide.

[0047] This application discloses a method for fabricating an array substrate 100, comprising the following steps: Step S11: Please refer to Figure 4 A first insulating layer PV1 is formed on the substrate 1. The first insulating layer PV1 includes a first insulator layer PV11 and a second insulator layer PV12 that are sequentially stacked on one side of the substrate 1.

[0048] Step S12: Please refer to Figure 5 A first organic photoresist material PR1 is formed on the second insulator layer PV12. After the first organic photoresist material PR1 is exposed and developed by the first photomask, the first organic photoresist material PR1 exposes the part of the second insulator layer PV12 located in the non-opening region AA2, while the first organic photoresist material PR1 covers the part of the second insulator layer PV12 located in the opening region AA1.

[0049] Step S13: Please refer to Figure 6The portion of the second insulator layer PV12 exposed to the first organic photoresist material PR1 is removed by etching, forming a second opening K2 in the second insulator layer PV12 and a first opening K1 in the first insulator layer PV11. The second opening K2 communicates with the first opening K1 to form a first groove C1. The etching can be dry etching, where the etchant accumulates at the bottom of the first groove C1, resulting in a greater degree of etching on the sidewall of the first insulator layer PV11 near the first opening K1 and a lesser degree of etching on the sidewall of the second insulator layer PV12 near the first opening K1. Therefore, the sidewall of the second insulator layer PV12 near the second opening K2 extends beyond the sidewall of the first insulator layer PV11 near the first opening K1, forming a first undercut structure U1.

[0050] Step S14: Please refer to Figure 7 The first organic photoresist material PR1 covering the opening region AA1 is removed by peeling.

[0051] Step S15: Please refer to Figure 8 A first transparent electrode layer 2 and a first metal layer M1 are sequentially formed on one side of the substrate 1. The first transparent electrode layer 2 is interrupted at the first undercut structure U1 to form a first pad layer 21 and a first common electrode 22. The first pad layer 21 is disposed within the first groove C1, and the first common electrode 22 is disposed on the side of the second insulator layer PV12 away from the first insulator layer PV11. The first metal layer M1 is interrupted at the first undercut structure U1 to form a first electrode M11 and a first electrode to be etched M12. The first electrode M11 is located within the first groove C1 and is disposed on the side of the first pad layer 21 away from the substrate 1. The first electrode to be etched M12 is disposed on the side of the first common electrode 22 away from the substrate 1.

[0052] Step S16: Please refer to Figure 9 A second organic photoresist material PR2 with leveling properties is coated on one side of the substrate 1. Because the leveling second organic photoresist material PR2 flows from higher to lower potentials, the thickness of the second organic photoresist material PR2 above the first electrode M12 to be etched is less than the thickness of the second organic photoresist material PR2 above the first electrode M11. The second organic photoresist material PR2 is then processed using a vacuum chamber drying (VCD) process to evaporate the solvent in the second organic photoresist material PR2, forming a first photoresist PR21 on the first electrode M11 and a second photoresist PR22 on the first electrode M12 to be etched. Because the step difference between the upper surface of the first electrode M11 and the upper surface of the first electrode M12 to be etched is large, the first photoresist PR21 and the second photoresist PR22 are separated by this step difference, and the thickness of the second photoresist PR22 is less than the thickness of the first photoresist PR21.

[0053] Step S17: Please refer to Figure 10 The first photoresist PR21 and the second photoresist PR22 are subjected to an ashing process. Since the thickness of the first photoresist PR21 is greater than that of the second photoresist PR22, when the second photoresist PR22 is completely removed by the ashing process, a portion of the first photoresist PR21 can still be retained.

[0054] Step S18: Please refer to Figure 11 The first electrode M12 is removed by etching. Since the first electrode M11 is covered by the first photoresist PR21, the first electrode M11 will not be etched.

[0055] Step S19: Please refer to Figure 12 After the first electrode M12 to be etched is removed, the first photoresist PR21 on the first electrode M11 is removed by photoresist stripping (PR Strip) process.

[0056] As can be seen from the above-described method for fabricating the array substrate 100, etching is only used in steps S13 and S18. Step S13 etches the first insulating layer PV1, which is an inorganic material and not a patterned electrode, thus not causing linewidth loss. Step S18 removes the first electrode M12 above the first common electrode 22 through etching. This etching does not cause the edge of the film layer of the first common electrode 22 to be etched thinner than the middle of the film layer. In extreme cases, even if the edge of the film layer of the first common electrode 22 is etched thinner than the middle of the film layer, since the edge of the film layer of the first common electrode 22 overlaps with the first undercut structure U1 and part of the first electrode M11, the first electrode M11 can block light from passing through the edge of the film layer of the first common electrode 22, preventing the edge of the film layer of the first common electrode 22 from affecting the display effect.

[0057] Please see Figure 13 Optionally, the array substrate 100 also has a border region NA. The border region NA is located on at least one side of the pixel region AA.

[0058] Please see Figure 14 A third opening K3 is formed in the first insulator layer PV11. A fourth opening K4 is formed in the second insulator layer PV12. The third opening K3 and the fourth opening K4 communicate to form a plurality of second grooves C2. The second grooves C2 are located in the border area NA. The sidewall of the second insulator layer PV12 near the fourth opening K4 extends beyond the sidewall of the first insulator layer PV11 near the third opening K3, forming a second undercut structure U2.

[0059] The first metal layer M1 is located in a portion of the frame area NA and is separated at the second undercut structure U2, forming multiple fan-out traces M13. The fan-out traces M13 are located on the side of the second insulator layer PV12 away from the first insulator layer PV11. The gap between two adjacent fan-out traces M13 overlaps with the second groove C2.

[0060] In this embodiment, in the first insulator layer PV11, while forming the first opening K1 in the pixel area AA, a third opening K3 can also be formed simultaneously in the border area NA. In the second insulator layer PV12, while forming the second opening K2 in the pixel area AA, a fourth opening K4 can also be formed simultaneously in the border area NA. That is, the first groove C1 and the second groove C2 can be formed using the same photomask, reducing production costs.

[0061] In this embodiment, while fabricating the first electrode M11 located in the pixel area AA, a fan-out trace M13 can also be fabricated in the border area NA. Since two adjacent fan-out traces M13 are separated by the second undercut structure U2, no etchant is required during the formation of each fan-out trace M13. Therefore, each fan-out trace M13 will not experience linewidth loss.

[0062] Please see Figure 15 In related technologies, during the design phase, the linewidth of each fan-out trace M13 is L1', and the spacing between two adjacent fan-out traces M13 is L2'. However, due to linewidth loss during etching, the actual linewidth of each fan-out trace M13 is L1a, and the spacing between two adjacent fan-out traces M13 is L2a. The actual linewidth L1a of the formed fan-out trace M13 is smaller than the designed linewidth L1', resulting in increased resistance. Since the linewidths of multiple fan-out traces M13 are uncontrollable, the consistency of resistance among them cannot be guaranteed. Furthermore, the actual spacing L2a between two adjacent fan-out traces M13 is larger than the designed spacing L2', making it impossible to achieve a high-density fan-out trace design, thus failing to meet the requirements of narrow-bezel display panels.

[0063] Please see Figure 14In this embodiment, since there is no linewidth loss in the bezel area NA, the actual linewidth of the formed fan-out trace M13 is consistent with the designed linewidth of the fan-out trace M13. This ensures that the resistance of the actual formed fan-out trace M13 is the same as the designed resistance, making the linewidth of multiple fan-out traces M13 controllable. This improves the consistency of the resistance of multiple fan-out traces M13, ensuring the consistency of the voltage of each pixel in the plane, and thus improving the uniformity of the display effect. On the other hand, since there is no linewidth loss, the actual spacing between two adjacent fan-out traces M13 is equal to the designed spacing between two adjacent fan-out traces M13. Therefore, by reducing the spacing between two adjacent fan-out traces M13 during the design phase, a high-density fan-out trace M13 design can be achieved, meeting the requirements of narrow bezel display panels and improving the display effect.

[0064] Please see Figure 14 Optionally, in a plan view of the array substrate 100, the spacing L2 between two adjacent fan-out traces M13 is greater than or equal to 0.3 micrometers, and the width L1 of the fan-out trace M13 is greater than or equal to 1.5 micrometers.

[0065] In this embodiment, since there is no linewidth loss in the fan-out traces M13 of the border area NA, the spacing L2 between two adjacent fan-out traces M13 can be significantly reduced, achieving a high-density fan-out trace design to meet the requirements of a narrow border. This embodiment can reduce the spacing between two adjacent fan-out traces M13 to a minimum of 0.3 micrometers, achieving a dense trace design that is impossible to achieve through etching processes.

[0066] Optionally, the spacing L2 between two adjacent fan-out traces M13 can be 0.3 micrometers, 0.35 micrometers, 0.4 micrometers, 0.45 micrometers, 0.5 micrometers, 0.55 micrometers, 0.6 micrometers, 0.65 micrometers, 0.7 micrometers, 0.75 micrometers, 0.8 micrometers, 0.85 micrometers, 0.9 micrometers, 0.95 micrometers, 1 micrometer, or more.

[0067] In this embodiment, since there is no linewidth loss in the fan-out trace M13 of the border area NA, the consistency of the resistance of multiple fan-out traces M13 can be improved, thereby ensuring the consistency of the voltage of individual pixels in the plane and improving the uniformity of the display effect.

[0068] Optionally, the width L1 of the fan-out trace M13 can be 1.5 micrometers, 1.55 micrometers, 1.6 micrometers, 1.65 micrometers, 1.7 micrometers, 1.75 micrometers, 1.8 micrometers, 1.85 micrometers, 1.9 micrometers, 1.95 micrometers, 2 micrometers, or more.

[0069] Please see Figure 14 Optionally, the portion of the first transparent conductive layer located in the frame area NA is interrupted at the second undercut structure U2 to form a third pad layer 23. The third pad layer 23 is located between the fan-out trace M13 and the second insulator layer PV12.

[0070] In this embodiment, the third pad 23 adds a new current path, thereby reducing the resistance of each fan-out trace M13 and thus reducing the power consumption of the display panel.

[0071] Please see Figure 16 Optionally, the array substrate 100 further includes a second insulating layer PV2, a semiconductor layer 3, a third insulating layer PV3, and a second metal layer M2.

[0072] The second insulating layer PV2 is disposed on the side of the first insulating layer PV1 away from the substrate 1, and covers the first transparent electrode layer 2 and the first metal layer M1.

[0073] Semiconductor layer 3 is disposed on the side of the second insulating layer PV2 away from the substrate 1 and located in pixel region AA. Semiconductor layer 3 includes a first conductor portion 31, a channel 32, and a second conductor portion 33 connected in sequence. The first conductor portion 31 overlaps with the edge of the first common electrode 22. The channel 32 overlaps with the first electrode M11.

[0074] A third insulating layer PV3 is disposed on the side of semiconductor layer 3 away from substrate 1. A third groove C3 and a fourth groove C4 are provided in the third insulating layer PV3. The third groove C3 and the fourth groove C4 are located in pixel region AA. The third groove C3 exposes the first conductor portion 31. The fourth groove C4 exposes the second conductor portion 33.

[0075] The second metal layer M2 includes a second electrode M21 and a third electrode M22. The second electrode M21 is disposed in the third groove C3 and connected to the first conductor portion 31. The third electrode M22 is disposed in the fourth groove C4 and connected to the second conductor portion 33.

[0076] In this embodiment, the first electrode M11 serves as the gate, and the second insulating layer PV2 serves as the gate insulating layer. The material of the semiconductor layer 3 can be a metal oxide, such as indium gallium zinc oxide. The material of the semiconductor layer 3 can also be amorphous silicon (a-Si), etc., and the material of the semiconductor layer 3 is not limited here. The second electrode M21 and the third electrode M22 formed by the second metal layer M2 can serve as the output and input electrodes of the thin-film transistor. A method similar to that used to form the first electrode M11 can be used to reduce the linewidth loss of the second electrode M21 and the third electrode M22, and improve the consistency of the performance of multiple thin-film transistor devices within the pixel area AA. For the specific method of forming the first electrode M11, please refer to the following embodiments.

[0077] This application proposes a method for fabricating an array substrate 100, which, after step S19, further includes the following steps: Step S21: Please refer to Figure 17 A second insulating layer PV2 and a semiconductor material layer are sequentially formed on the side of the first insulating layer PV1 away from the substrate 1. The second insulating layer PV2 covers the first transparent electrode layer 2 and the first metal layer M1.

[0078] Step S22: Please refer to Figure 18 A third organic photoresist material PR3 is formed on the semiconductor material layer. After the third organic photoresist material PR3 is exposed and developed using a second ordinary photomask, the third organic photoresist material PR3 covers the portion of the second insulating layer PV2 located in the non-opening region AA2.

[0079] Step S23: Please refer to Figure 19 The portion of the second insulating layer PV2 exposed to the third organic photoresist material PR3 is removed by etching to form a semiconductor layer 3, which is located in the non-opening region AA2.

[0080] Step S24: Please refer to Figure 20 The third organic photoresist material PR3 covering the non-opening area AA2 was removed by peeling.

[0081] Optionally, the third insulating layer PV3 includes a third insulator layer PV32 and a fourth insulator layer PV33 sequentially stacked on the side of the semiconductor layer 3 away from the substrate 1. A fifth opening K5 and a sixth opening K6 are formed in the third insulator layer PV32 at intervals. A seventh opening K7 and an eighth opening K8 are formed in the fourth insulator layer PV33 at intervals. The fifth opening K5 communicates with the seventh opening K7, forming a third groove C3. The sixth opening K6 communicates with the eighth opening K8, forming a fourth groove C4.

[0082] The sidewall of the fourth insulator layer PV33 near the seventh opening K7 extends beyond the sidewall of the third insulator layer PV32 near the fifth opening K5, forming the third undercut structure U3.

[0083] The sidewall of the fourth insulator layer PV33 near the eighth opening K8 extends beyond the sidewall of the third insulator layer PV32 near the sixth opening K6, forming the fourth undercut structure U4.

[0084] The second metal layer M2 is separated at the third undercut structure U3 and the fourth undercut structure U4, forming the second electrode M21 and the third electrode M22.

[0085] In this application, on the one hand, the third insulating layer can be patterned using a third photomask to form a third groove with a third undercut structure and a fourth groove with a fourth undercut structure. The second metal layer subsequently formed on the third insulating layer is interrupted at the third and fourth undercut structures, forming the second and third electrodes respectively, thus eliminating the need for additional photomasks and etching methods to form the second and third electrodes. Therefore, this application uses only one photomask to pattern the third insulating layer and the second metal layer, reducing the number of photomasks required and lowering production costs. On the other hand, since the second metal layer is not formed by etching, the linewidth loss of the second and third electrodes can be reduced, solving the problem of linewidth loss caused by etching agents, making the linewidth of the second and third electrodes controllable, and improving the device stability of the transistor.

[0086] In this embodiment, the method for forming the first groove C1 is the same as that for the first insulating layer PV1. A fourth organic photoresist material is formed on the side of the third insulating layer PV3 away from the substrate 1. The fourth organic photoresist material is exposed and developed using a third photomask to pattern the third insulating layer PV3, thereby forming a third groove C3 with a third undercut structure U3 and a fourth groove C4 with a fourth undercut structure U4 in the third insulating layer PV3. The second metal layer M2 is separated at the third undercut structure U3 and the fourth undercut structure U4, forming a second electrode M21, a third electrode M22, and a second electrode to be etched. The second electrode M21 is located in the third groove C3, the third electrode M22 is located in the fourth groove C4, and the second electrode to be etched is located on the side of the fourth insulating layer PV33 away from the third insulating layer PV32.

[0087] After forming the second metal layer M2, a fifth organic photoresist material with leveling properties is coated on one side of the substrate 1. Because the leveling fifth organic photoresist material flows from higher to lower potentials, the thickness of the fifth organic photoresist material above the second electrode to be etched is less than the thickness of the fifth organic photoresist material above the second electrode M21 and the third electrode M22. The fifth organic photoresist material is then processed using a vacuum chamber drying (VCD) process to evaporate the solvent, forming a third photoresist on the second electrode M21, a fourth photoresist on the third electrode M22, and a fifth photoresist on the second electrode to be etched. Because the step differences between the upper surfaces of the second electrode M21 and the third electrode M22 and the upper surface of the second electrode to be etched are significant, the third and fourth photoresists are separated by these step differences, and the thicknesses of the third and fourth photoresists are both greater than the thickness of the fifth photoresist. The third, fourth, and fifth photoresists are subjected to an ashing process. Since the thicknesses of the third and fourth photoresists are greater than that of the fifth photoresist, a portion of the third and fourth photoresists can still be retained even after the fifth photoresist is completely removed by the ashing process. The second electrode to be etched is removed by etching. Because the second electrode M21 and the third electrode M22 are covered with the third and fourth photoresists respectively, the second electrode M21 and the third electrode M22 are not etched. After the second electrode to be etched is removed, the third and fourth photoresists on the second electrode M21 and the third electrode M22 are removed by a photoresist stripping process. In the above process, only one photomask is used when forming the third groove C3 and the fourth groove C4, which reduces the number of photomasks used and lowers production costs.

[0088] Optionally, before stripping the third and fourth photoresists, the fourth insulator layer PV33 can also be removed to improve the flatness of the film layer above the second metal layer M2.

[0089] Optionally, the third insulating layer PV3 further includes a fifth insulating layer PV31 disposed on the side of the third insulating layer PV32 near the semiconductor layer 3.

[0090] The fifth insulator layer PV31 has a ninth opening K9 and a tenth opening K10 that are spaced apart.

[0091] The ninth opening K9, the fifth opening K5, and the seventh opening K7 are connected to form the third groove C3.

[0092] The tenth opening K10, the sixth opening K6, and the eighth opening K8 are connected to form the fourth groove C4.

[0093] The material of the third insulator layer PV32 contains nitrogen and silicon. The materials of the fourth insulator layer PV33 and the fifth insulator layer PV31 contain oxygen and silicon.

[0094] In this embodiment, materials with different etching selectivity are required to form the third undercut structure U3 and the fourth undercut structure U4. In one embodiment, the material of the third insulator layer PV32 is silicon nitride, and the material of the fourth insulator layer PV33 is silicon oxide.

[0095] However, if the third insulator layer PV32, which is made of silicon nitride, is in direct contact with the semiconductor layer 3, which is made of metal oxide, the silicon nitride will affect the hole concentration of the oxide, resulting in a decrease in the device stability of the transistor.

[0096] Therefore, in this embodiment, a fifth insulator layer PV31 is provided on the side of the third insulator layer PV32 close to the semiconductor layer 3. The material of the fifth insulator layer PV31 is silicon oxide. The fifth insulator layer PV31 can separate the third insulator layer PV32 and the semiconductor layer 3, reduce the contact area between the third insulator layer PV32 and the semiconductor layer 3, thereby reducing the influence of silicon nitride on the oxide hole concentration and improving the device stability of the transistor.

[0097] This application proposes a method for manufacturing an array substrate 100, which, after step S24, further includes the following steps: Step S31: Please refer to Figure 21 A third insulating layer PV3 is formed on the side of the second metal layer M2 away from the substrate 1. The third insulating layer PV3 includes a fifth insulator layer PV31, a third insulator layer PV32, and a fourth insulator layer PV33 stacked sequentially.

[0098] Step S32: Please refer to Figure 22 A fourth organic photoresist material is formed on the side of the third insulating layer PV3 away from the substrate 1. The fourth organic photoresist material is exposed and developed through a third photomask to pattern the third insulating layer PV3, thereby forming a third groove C3 with a third undercut structure U3 and a fourth groove C4 with a fourth undercut structure U4 in the third insulating layer PV3.

[0099] Step S33: Please refer to Figure 23The second metal layer M2 is separated at the third undercut structure U3 and the fourth undercut structure U4, forming the second electrode M21, the third electrode M22, and the second electrode to be etched. The second electrode M21 is located in the third groove C3, the third electrode M22 is located in the fourth groove C4, and the second electrode to be etched is located on the side of the fourth insulator layer PV33 away from the third insulator layer PV32. After forming the second metal layer M2, a fifth organic photoresist material with leveling properties is coated on one side of the substrate 1. Because the fifth organic photoresist material with leveling properties flows from a higher potential to a lower potential, the thickness of the fifth organic photoresist material above the second electrode to be etched is less than the thickness of the fifth organic photoresist material above the second electrode M21 and the third electrode M22. The fifth organic photoresist material is then processed using a vacuum chamber drying (VCD) process to evaporate the solvent in the fifth organic photoresist material, forming the third photoresist on the second electrode M21, the fourth photoresist on the third electrode M22, and the fifth photoresist on the second electrode to be etched. Because the steps between the upper surfaces of the second electrode M21 and the third electrode M22 and the upper surface of the second electrode to be etched are relatively large, the third and fourth photoresists are separated by this step difference, and the thicknesses of the third and fourth photoresists are both greater than the thickness of the fifth photoresist. An ashing process is applied to the third, fourth, and fifth photoresists. Since the thicknesses of the third and fourth photoresists are greater than the thickness of the fifth photoresist, when the fifth photoresist is completely removed by the ashing process, a portion of the third and fourth photoresists can still be retained. The second electrode to be etched is removed by etching. Because the second electrode M21 and the third electrode M22 are covered with the third and fourth photoresists respectively, the second electrode M21 and the third electrode M22 will not be etched. After the second electrode to be etched is removed, the third and fourth photoresists on the second electrode M21 and the third electrode M22 are removed by a photoresist stripping process. In the above process, only one mask is used when forming the third groove C3 and the fourth groove C4, which can reduce the number of mask used by at least one and reduce production costs.

[0100] Optionally, before stripping the third and fourth photoresists, the fourth insulator layer PV33 can be removed by etching, thereby reducing the depth of the third groove C3 and the fourth groove C4 to improve the flatness of the film layer above the second metal layer M2.

[0101] Optionally, after removing the second electrode to be etched, a portion of the third and fourth photoresists can be retained to improve the flatness of the overlying film. During the subsequent formation of the pixel electrode 5, the pixel electrode 5 passes through the third photoresist and is electrically connected to the second electrode M21. The materials of the third and fourth photoresists can be organic planarizing materials.

[0102] Please see Figure 24 Optionally, the array substrate 100 also includes a fourth insulating layer PV4 and a pixel electrode 5.

[0103] The fourth insulating layer PV4 includes a sixth insulator layer PV41 and a seventh insulator layer PV42, which are sequentially stacked on the side of the third insulating layer PV3 away from the substrate 1. A first via D1 is formed in the sixth insulator layer PV41. The first via D1 exposes the second electrode M21. A plurality of eleventh openings K11 are formed in the seventh insulator layer PV42 at intervals. The plurality of eleventh openings K11 overlap with the first common electrode 22. One eleventh opening K11 communicates with the first via D1.

[0104] The pixel electrode 5 includes a first connecting portion 51 and a plurality of branch electrodes 52. The first connecting portion 51 is electrically connected to the plurality of branch electrodes 52 respectively. The first connecting portion 51 is disposed in the first through hole D1 and connected to the second electrode M21. The branch electrodes 52 are disposed in the eleventh opening K11.

[0105] In this embodiment, the etching selectivity of the sixth insulator layer PV41 is different from that of the seventh insulator layer PV42. The etching rate of the sixth insulator layer PV41 is slower, which can prevent the part of the sixth insulator layer PV41 located in the opening region AA1 from being etched through, causing the pixel electrode 5 to be short-circuited with the second metal layer M2.

[0106] In this embodiment, the pixel electrode 5 further includes a trunk electrode, which is connected to multiple branch electrodes 52, and the connecting portion is electrically connected to the trunk electrode. This embodiment can use a method similar to that used to form the first electrode M11 to reduce the linewidth loss of the branch electrodes 52, improve the consistency of multiple pixel electrodes 5 within the pixel area AA, thereby improving the uniformity of the display effect. For a detailed method for forming the pixel electrode 5, please refer to subsequent embodiments.

[0107] Optionally, the fourth insulating layer PV4 further includes an eighth insulator layer PV43. The eighth insulator layer PV43 is located on the side of the seventh insulator layer PV42 away from the sixth insulator layer PV41. Multiple spaced-apart twelfth openings K12 are formed in the eighth insulator layer PV43. The twelfth openings K12 communicate with the eleventh openings K11, forming fifth grooves C5. The multiple fifth grooves C5 are located in the pixel area AA.

[0108] The sidewall of the eighth insulator layer PV43 near the twelfth opening K12 extends beyond the sidewall of the seventh insulator layer PV42 near the eleventh opening K11, forming the fifth undercut structure U5.

[0109] The pixel electrode 5 is separated at the fifth undercut structure U5, forming multiple branch electrodes 52.

[0110] In this embodiment, on the one hand, the fourth insulating layer can be patterned using a fourth photomask to form a fifth groove with a fifth undercut structure. Pixel electrodes subsequently formed on the fourth insulating layer are all separated at the fifth undercut structure, forming multiple branch electrodes, thus eliminating the need for additional photomasks and etching methods to form multiple branch electrodes. Therefore, this application uses only one photomask to complete the patterning of the fourth insulating layer and pixel electrodes, reducing the number of photomasks required and lowering production costs. On the other hand, since the pixel electrodes are not formed by etching, the linewidth loss of the branch electrodes can be reduced, solving the linewidth loss problem caused by etching with etchants, making the linewidth of the branch electrodes controllable and improving display uniformity.

[0111] In this embodiment, the method for forming the first groove C1 in the first insulating layer PV1 is the same as that for forming the first groove C1. A sixth organic photoresist material is formed on the side of the fourth insulating layer PV4 away from the substrate 1. The sixth organic photoresist material is exposed and developed using a fourth halftone mask to pattern the fourth insulating layer PV4, thereby forming multiple fifth grooves C5 with a fifth undercut structure U5 and a first via D1 in the fourth insulating layer PV4. The pixel electrode 5 is separated at the fifth undercut structure U5, forming a first connection portion 51, multiple branch electrodes 52, and multiple third electrodes to be etched. The first connection portion 51 is disposed in the first via D1, the branch electrodes 52 are located in the fifth grooves C5, and the third electrodes to be etched are disposed on the side of the eighth insulating layer PV43 away from the seventh insulating layer PV42.

[0112] After forming pixel electrode 5, a leveling seventh organic photoresist material is coated on one side of substrate 1. Because the leveling seventh organic photoresist material flows from higher to lower potentials, the thickness of the seventh organic photoresist material above the third electrode to be etched is less than the thickness of the seventh organic photoresist material above the branch electrode 52. The seventh organic photoresist material is then processed using a vacuum chamber drying (VCD) process to evaporate the solvent, forming a sixth photoresist on the branch electrode 52 and a seventh photoresist on the third electrode to be etched. Due to the significant step difference between the upper surface of the branch electrode 52 and the upper surface of the third electrode to be etched, the sixth and seventh photoresists are separated by this step difference, and the thickness of the sixth photoresist is greater than that of the seventh photoresist. An ashing process is then applied to the sixth and seventh photoresists. Because the thickness of the sixth photoresist is greater than that of the seventh photoresist, a portion of the sixth photoresist can still be retained when the seventh photoresist is completely removed by the ashing process. The third electrode to be etched is removed by etching. Since the branch electrode 52 is covered with the sixth photoresist, the branch electrode 52 is not etched. After the third electrode to be etched is removed, the sixth photoresist on the branch electrode 52 is removed by a photoresist stripping (PR Strip) process. In the above process, only one photomask is used when forming the third insulating layer PV3, which can reduce the number of photomasks used and reduce production costs.

[0113] Optionally, the eighth insulator layer PV43 can also be removed before stripping the sixth photoresist to improve the flatness of the film layer above the pixel electrode 5.

[0114] Alternatively, after removing the third electrode to be etched, the sixth photoresist can be retained to improve the flatness of the film layer above the pixel electrode 5. The material of the sixth photoresist can be an organic planarizing material.

[0115] In the above-mentioned method for manufacturing the array substrate 100, only four photomasks are used from the process of forming the first electrode M11, the process of forming the common electrode to the process of forming the pixel electrode 5. Compared with traditional technology, this greatly reduces the number of photomasks used and lowers production costs.

[0116] Optionally, the material of the sixth insulator layer is silicon oxide, the material of the seventh insulator layer is silicon nitride, and the material of the eighth insulator layer is silicon oxide.

[0117] This application proposes a method for manufacturing an array substrate 100, which, after step S33, further includes the following steps: Step S41: Please refer to Figure 25A fourth insulating layer PV4 is formed on the side of the third insulating layer PV3 away from the substrate 1. The fourth insulating layer PV4 includes a sixth insulating layer PV41, a seventh insulating layer PV42, and an eighth insulating layer PV43 stacked sequentially.

[0118] Step S42: Please refer to Figure 26 A sixth organic photoresist material is formed on the side of the fourth insulating layer PV4 away from the substrate 1. The sixth organic photoresist material is exposed and developed through a fourth halftone mask to pattern the fourth insulating layer PV4, thereby forming a plurality of fifth grooves C5 with a fifth undercut structure U5 and a first via D1 in the fourth insulating layer PV4.

[0119] Step S43: Please refer to Figure 27 The pixel electrode 5 is separated at the fifth undercut structure U5, forming a first connecting portion 51, multiple branch electrodes 52, and multiple third electrodes to be etched. The first connecting portion 51 is located within the first via D1, the branch electrodes 52 are located within the fifth groove C5, and the third electrodes to be etched are located on the side of the eighth insulator layer PV43 away from the seventh insulator layer PV42. After forming the pixel electrode 5, a leveling seventh organic photoresist material is coated on one side of the substrate 1. Because the leveling seventh organic photoresist material flows from a higher potential to a lower potential, the thickness of the seventh organic photoresist material above the third electrodes to be etched is less than the thickness of the seventh organic photoresist material above the branch electrodes 52. The seventh organic photoresist material is then processed using a vacuum chamber drying (VCD) process to evaporate the solvent in the seventh organic photoresist material, forming a sixth photoresist located on the first branch electrode 52 and a seventh photoresist located on the third electrodes to be etched. Because of the significant step difference between the upper surface of the branch electrode 52 and the upper surface of the third electrode to be etched, the sixth and seventh photoresists are separated by this step difference, and the thickness of the sixth photoresist is greater than that of the seventh photoresist. An ashing process is used on the sixth and seventh photoresists. Since the thickness of the sixth photoresist is greater than that of the seventh photoresist, a portion of the sixth photoresist can still be retained when the seventh photoresist is completely removed by the ashing process. The third electrode to be etched is removed by etching; since the branch electrode 52 is covered by the sixth photoresist, it is not etched. After the third electrode to be etched is removed, the sixth photoresist on the branch electrode 52 is removed by a photoresist stripping process. In the above process, only one photomask is used when forming the third insulating layer PV3, which reduces the number of photomasks used and lowers production costs.

[0120] Optionally, the eighth insulator layer PV43 can also be removed before stripping the sixth photoresist to improve the flatness of the film layer above the pixel electrode 5.

[0121] Please see Figure 28 Optionally, a thirteenth opening K13 is also formed in the first insulator layer PV11. A fourteenth opening K14 is also formed in the second insulator layer PV12. The thirteenth opening K13 and the fourteenth opening K14 are connected to form a sixth groove C6. The sixth groove C6 is located on one side of the first groove C1 and is formed by the same photomask.

[0122] The sidewall of the second insulator layer PV12 near the fourteenth opening K14 extends beyond the sidewall of the first insulator layer PV11 near the thirteenth opening K13, forming the sixth undercut structure U6.

[0123] The first transparent electrode layer 2 is interrupted at the sixth undercut structure U6. A second pad layer 24 is formed, which is disposed in the sixth groove C6.

[0124] The first metal layer M1 is interrupted at the sixth undercut structure U6 to form the first transfer electrode M14. The first transfer electrode M14 is located in the sixth groove C6 and is disposed on the side of the second pad layer 24 away from the substrate 1.

[0125] The first adapter electrode M14 is electrically connected to the first common electrode 22.

[0126] In this embodiment, the first common electrode 22 is powered by the first adapter electrode M14. Since the sixth groove C6 and the first groove C1 can be fabricated using the same photomask, no additional cost is incurred. The first adapter electrode M14 can be electrically connected to the first common electrode 22 by switching the wiring through the second metal layer M2. Alternatively, the first adapter electrode M14 can be electrically connected to the first common electrode 22 layer by switching the wiring through the second metal layer M2 and the pixel electrode 5.

[0127] Optionally, the sixth groove C6 is located in the border area NA.

[0128] Please see Figure 29 In one embodiment, the first transfer electrode M14 is switched through the second metal layer M2 to achieve electrical connection between the first transfer electrode M14 and the first common electrode 22.

[0129] Optionally, a second via D2 and a third via D3 are formed in the second insulating layer PV2 at intervals. The second via D2 exposes the first common electrode 22. The third via D3 exposes the first transition electrode M14.

[0130] The third insulator layer PV32 also has a fifteenth opening K15 and a sixteenth opening K16 formed at intervals. The fourth insulator layer PV33 also has a seventeenth opening K17 and an eighteenth opening K18 formed at intervals.

[0131] The second through hole D2, the fifteenth opening K15, and the seventeenth opening K17 are connected to form the first adapter hole P1.

[0132] The third through hole D3, the sixteenth opening K16, and the eighteenth opening K18 are connected to form the second adapter hole P2.

[0133] The first adapter hole P1, the second adapter hole P2, the third groove C3, and the fourth groove C4 are formed by the same mask template.

[0134] The second metal layer M2 also includes a second transfer electrode M23 and a third transfer electrode M24, with the second transfer electrode M23 and the third transfer electrode M24 being electrically connected.

[0135] The second adapter electrode M23 is located inside the first adapter hole P1 and is connected to the first common electrode 22.

[0136] The third adapter electrode M24 is located inside the second adapter hole P2 and is connected to the first adapter electrode M14.

[0137] In this embodiment, when forming the third groove C3 and the fourth groove C4 using the third mask, the third mask can be replaced with a halftone mask, simultaneously forming the first transition hole P1 and the second transition hole P2, thereby avoiding the need for additional mask templates and reducing production costs. The first transition electrode M14 can be electrically connected to the first common electrode 22 through the third transition electrode M24 and the second transition electrode M23. In this embodiment, the second transition electrode M23 and the third transition electrode M24 can be electrically connected by connecting the seventeenth opening K17 and the eighteenth opening K18.

[0138] In another embodiment, the first transition electrode M14 can also be switched through the second metal layer M2 and the pixel electrode 5 to achieve electrical connection between the first transition electrode M14 and the first common electrode 22 layer.

[0139] Please see Figure 30 The sixth insulator layer PV41 also has a fourth via D4 and a fifth via D5 spaced apart. The fourth via D4 exposes the second transition electrode M23. The fifth via D5 exposes the third transition electrode M24.

[0140] The seventh insulator layer PV42 also has a nineteenth opening K19, which is connected to the fourth through hole D4 and the fifth through hole D5.

[0141] The first through hole D1, the fourth through hole D4, the fifth through hole D5, the eleventh opening K11, and the nineteenth opening K19 are formed through the same mask template.

[0142] The pixel electrode 5 also includes a second connecting part 53, which is disposed in the nineteenth opening K19, the fourth via D4 and the fifth via D5, and connects the second adapter electrode M23 and the third adapter electrode M24.

[0143] In this embodiment, during the patterning process of the fourth insulating layer PV4 using the fourth mask, the fourth mask can be replaced with a halftone mask, and the first via D1, the fourth via D4, the fifth via D5, the eleventh opening K11, and the nineteenth opening K19 can be formed, thereby avoiding the need for additional masking and reducing production costs.

[0144] Compared to the previous embodiment, which mainly uses an opaque second metal layer M2 for line replacement, this embodiment mainly uses a light-transmitting pixel electrode 5 for line replacement, which can improve the light transmittance of the array substrate 100 and improve the display effect.

[0145] Optionally, the array substrate 100 further includes a fifth insulating layer and a second transparent electrode layer.

[0146] The fifth insulating layer includes a ninth insulator layer and a tenth insulator layer, which are sequentially stacked on the side of the fourth insulating layer PV4 away from the substrate 1. A sixth via is formed in the ninth insulator layer. The sixth via exposes the second connection portion 53. A twentieth opening is formed in the tenth insulator layer. The twentieth opening communicates with the sixth via.

[0147] The second transparent electrode layer includes a second connecting portion 53 and a second common electrode. The second common electrode is disposed within the twentieth opening. The second connecting portion 53 is disposed within the sixth through hole and connects the second common electrode and the second connecting portion 53.

[0148] In this embodiment, the method for forming the second transparent electrode layer is the same as the method for forming the pixel electrode 5, and will not be described in detail here. The pixel electrode 5 can form a storage capacitor with the first common electrode 22 and the second common electrode respectively, which can increase the storage capacitance of the transistor and thus improve the display effect.

[0149] The second common electrode can also be powered through the first adapter electrode M14, thereby improving the utilization rate of the frame traces and enabling one first adapter electrode M14 to simultaneously power the first common electrode 22 and the second common electrode, thus achieving a narrow frame design.

[0150] Optionally, the material of the ninth insulator layer is silicon oxide, and the material of the tenth insulator layer is silicon nitride.

[0151] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0152] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0153] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0154] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An array substrate having a pixel region, characterized in that, The array substrate includes: Substrate; The first insulating layer includes a first insulator layer and a second insulator layer stacked sequentially on one side of the substrate. A first opening is formed in the first insulator layer, and a second opening is formed in the second insulator layer. The first opening and the second opening communicate to form a first groove. The first groove is located in the pixel area. The sidewall of the second insulator layer near the second opening extends beyond the sidewall of the first insulator layer near the first opening, forming a first undercut structure. A first transparent electrode layer is disposed on one side of the substrate. The portion of the first transparent electrode layer located in the pixel area is separated at the first undercut structure to form a first pad layer and a first common electrode. The first pad layer is disposed within the first groove, and the first common electrode is disposed on the side of the second insulator layer away from the first insulator layer. The first metal layer includes a first electrode located in the pixel region, the first electrode being located within the first groove and disposed on the side of the first pad layer away from the substrate.

2. The array substrate as described in claim 1, characterized in that, The array substrate also has a border area, which is located on at least one side of the pixel area; A third opening is formed in the first insulator layer, and a fourth opening is formed in the second insulator layer. The third opening and the fourth opening communicate to form a plurality of second grooves. The second grooves are located in the frame area. The sidewall of the second insulator layer near the fourth opening extends beyond the sidewall of the first insulator layer near the third opening, forming a second undercut structure. The first metal layer is located in a portion of the frame area and is separated at the second undercut structure to form multiple fan-out traces. The fan-out traces are located on the side of the second insulator layer away from the first insulator layer, and the gap between two adjacent fan-out traces overlaps with the second groove.

3. The array substrate as described in claim 2, characterized in that, In a plan view of the array substrate, the spacing between two adjacent fan-out traces is greater than or equal to 0.3 micrometers, and the width of the fan-out trace is greater than or equal to 1.5 micrometers.

4. The array substrate as described in claim 1, characterized in that, The array substrate further includes: A second insulating layer is disposed on the side of the first insulating layer away from the substrate, and covers the first transparent electrode layer and the first metal layer; A semiconductor layer is disposed on the side of the second insulating layer away from the substrate and located in the pixel region. The semiconductor layer includes a first conductor portion, a channel, and a second conductor portion connected in sequence. The first conductor portion overlaps with the edge of the first common electrode, and the channel overlaps with the first electrode. A third insulating layer is disposed on the side of the semiconductor layer away from the substrate. The third insulating layer has a third groove and a fourth groove, which are located in the pixel area. The third groove exposes the first conductor portion, and the fourth groove exposes the second conductor portion. The second metal layer includes a second electrode and a third electrode. The second electrode is disposed in the third groove and connected to the first conductor portion. The third electrode is disposed in the fourth groove and connected to the second conductor portion.

5. The array substrate as described in claim 4, characterized in that, The third insulating layer includes a third insulator layer and a fourth insulator layer stacked sequentially on the side of the semiconductor layer away from the substrate. A fifth opening and a sixth opening are formed in the third insulator layer at intervals. A seventh opening and an eighth opening are formed in the fourth insulator layer at intervals. The fifth opening communicates with the seventh opening to form the third groove. The sixth opening communicates with the eighth opening to form the fourth groove. The sidewall of the fourth insulator layer near the seventh opening extends beyond the sidewall of the third insulator layer near the fifth opening, forming a third undercut structure; The sidewall of the fourth insulator layer near the eighth opening extends beyond the sidewall of the third insulator layer near the sixth opening, forming a fourth undercut structure. The second metal layer is separated at the third undercut structure and the fourth undercut structure to form the second electrode and the third electrode.

6. The array substrate as described in claim 5, characterized in that, The third insulating layer further includes a fifth insulating layer disposed on the side of the third insulating layer near the semiconductor layer; The fifth insulator layer has a ninth opening and a tenth opening that are spaced apart. The ninth opening, the fifth opening, and the seventh opening are connected to form the third groove; The tenth opening, the sixth opening, and the eighth opening are connected to form the fourth groove; The material of the third insulator layer contains nitrogen and silicon, while the materials of the fourth and fifth insulator layers contain oxygen and silicon.

7. The array substrate as described in claim 5, characterized in that, The array substrate further includes: The fourth insulating layer includes a sixth insulator layer and a seventh insulator layer sequentially stacked on the side of the third insulating layer away from the substrate. A first via is formed in the sixth insulator layer, exposing the second electrode. A plurality of spaced eleventh openings are formed in the seventh insulator layer, overlapping the first common electrode, and one of the eleventh openings communicates with the first via. The pixel electrode includes a first connecting portion and a plurality of branch electrodes. The first connecting portion is electrically connected to the plurality of branch electrodes respectively. The first connecting portion is disposed in the first via and connected to the second electrode. The branch electrodes are disposed in the eleventh opening.

8. The array substrate as claimed in claim 7, characterized in that, The fourth insulating layer also includes an eighth insulator layer, which is located on the side of the seventh insulator layer away from the sixth insulator layer. The eighth insulator layer has a plurality of spaced twelfth openings, which communicate with the eleventh opening to form fifth grooves. The plurality of fifth grooves are located in the pixel area. The sidewall of the eighth insulator layer near the twelfth opening extends beyond the sidewall of the seventh insulator layer near the eleventh opening, forming a fifth undercut structure. The pixel electrode is separated at the fifth undercut structure to form a plurality of the branch electrodes.

9. The array substrate as claimed in claim 7, characterized in that, A thirteenth opening is also formed in the first insulator layer, and a fourteenth opening is also formed in the second insulator layer. The thirteenth opening and the fourteenth opening are connected to form a sixth groove. The sixth groove is located on one side of the first groove and is formed by the same mask template. The sidewall of the second insulator layer near the fourteenth opening extends beyond the sidewall of the first insulator layer near the thirteenth opening, forming a sixth undercut structure; The first transparent electrode layer is separated at the sixth undercut structure to form a second pad layer, and the second pad layer is disposed in the sixth groove; The first metal layer is separated at the sixth undercut structure to form a first transfer electrode. The first transfer electrode is located in the sixth groove and is disposed on the side of the second pad layer away from the substrate. The first adapter electrode is electrically connected to the first common electrode.

10. The array substrate as claimed in claim 9, characterized in that, The second insulating layer has a second via and a third via spaced apart, the second via exposing the first common electrode and the third via exposing the first transition electrode; The third insulator layer also has a fifteenth and a sixteenth opening spaced apart, and the fourth insulator layer also has a seventeenth and an eighteenth opening spaced apart. The second through hole, the fifteenth opening, and the seventeenth opening are connected to form a first transition hole; The third through hole, the sixteenth opening, and the eighteenth opening are connected to form a second transition hole; The first adapter hole, the second adapter hole, the third groove, and the fourth groove are formed by the same photomask. The second metal layer further includes a second transfer electrode and a third transfer electrode, wherein the second transfer electrode is electrically connected to the third transfer electrode; The second adapter electrode is disposed in the first adapter hole and connected to the first common electrode; The third adapter electrode is disposed in the second adapter hole and is connected to the first adapter electrode.

11. The array substrate as claimed in claim 10, characterized in that, The sixth insulator layer also has a fourth via and a fifth via formed at intervals, the fourth via exposing the second transition electrode and the fifth via exposing the third transition electrode; The seventh insulator layer also has a nineteenth opening, which is connected to the fourth through hole and the fifth through hole respectively; The first via, the fourth via, the fifth via, the eleventh opening, and the nineteenth opening are formed through the same photomask. The pixel electrode further includes a second connecting portion, which is disposed in the nineteenth opening, the fourth via, and the fifth via, and connects the second adapter electrode and the third adapter electrode.

12. The array substrate as claimed in claim 11, characterized in that, The array substrate further includes: The fifth insulating layer includes a ninth insulator layer and a tenth insulator layer stacked sequentially on the side of the fourth insulating layer away from the substrate. A sixth via is formed in the ninth insulator layer, and the sixth via exposes the second connection portion. A twentieth opening is formed in the tenth insulator layer, and the twentieth opening communicates with the sixth via. The second transparent electrode layer includes a second connecting portion and a second common electrode. The second common electrode is disposed in the second tenth opening, and the second connecting portion is disposed in the sixth through hole and connects the second common electrode and the second connecting portion.

13. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-12.

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