A control system for suppressing voltage and current spikes at the output of a power amplifier

Abstract

The application provides a control system for inhibiting voltage and current spikes of a power amplifier output, which comprises a PS, a PL signal processing module and a high-voltage power circuit; wherein: the PS is configured to receive bus signals issued by an upper computer, perform digital Gaussian filtering on the bus signals and then transmit the signals to the PL signal processing module; meanwhile, the PS collects and uploads relevant data of the power amplifier; the PL signal processing module is configured to receive the signals processed by the digital Gaussian filtering and perform preprocessing on the signals; and the PL signal processing module transmits the processed signals to the high-voltage power circuit to control the high-voltage power circuit to perform power conversion operation on the load. The method provided by the application adjusts the parameters of the digital Gaussian filter, so that the phase jump of the signal is smoothly transitioned, the voltage and current spikes of the power amplifier output are inhibited, the stress of the high-voltage power circuit device in the later stage is reduced, the output power in the later stage is effectively improved, and the stability of the power amplifier is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital signal processing, in particular to a control system for suppressing output voltage and current spikes of a power amplifier. BACKGROUND

[0002] In the current fields of underwater detection, communication, navigation and ocean resource exploration, underwater acoustic systems are indispensable core tools. Its working principle is to convert electrical signals into acoustic signals in water through underwater acoustic transducers, and receive the returned acoustic signals. The power amplifier is the core device for driving various loads (such as transducers, antennas, speakers), and its performance directly determines the efficiency of the entire system.

[0003] With the development of technology, the power demand of power amplifier system in the field of underwater acoustic is increasing, especially in the communication system, sonar system, etc. The significance of improving its output power is significant. In the underwater acoustic detection system, the power amplifier drives the transducer to radiate sound waves, and its output power directly affects the sound source level (radiated sound power level) of the transducer. In the process of power amplification, suppressing the voltage and current spikes at the output end of the power amplifier to improve the effective output power of the power amplifier is always the core research direction in the field of underwater acoustic technology.

[0004] In the field of underwater acoustic communication, signals generated, modulated or transmitted will inevitably produce phase jump phenomenon due to factors such as modulation method (such as PSK, BPSK phase modulation), burst switching (such as multi-frequency signal switching, pulse signal starting) or load disturbance. Phase jump phenomenon is a step change in the phase of the signal in a very short time (such as 180° mutation), which will cause a sharp jump in the signal waveform in the time domain (such as the instantaneous reversal of the sine signal), and then introduce a large number of high-frequency harmonic components through Fourier transform (i.e. the "spectral diffusion" effect of phase jump). When the power amplifier processes these signals, the envelope fluctuation caused by the phase jump characteristics of the signal will cause a large voltage and current impact on the output of the power amplifier, which will trigger the protection action stop, such as the transformer is prone to magnetic saturation short circuit at the voltage and current spike jump, resulting in the original side current of the transformer increasing sharply and triggering the protection action. When the power amplifier output triggers the protection, it often does not reach the maximum output power required by the design, and cannot meet the design requirements of the transducer emission sound source level.

[0005] Therefore, realizing high-quality and high-power signal amplification is the key to the work of the power amplifier. How to effectively suppress the voltage and current spikes of the power amplifier output caused by the phase jump of the signal, so that the output power of the power amplifier is further improved and can stably drive the transducer to meet the corresponding sound source level, is an important means to improve the performance of underwater acoustic system. SUMMARY

[0006] The application provides a control system for suppressing power amplifier output voltage and current spikes.

[0007] The application provides a control system for suppressing power amplifier output voltage and current spikes.

[0008] The system comprises a PS, a PL signal processing module and a high-voltage power circuit.

[0009] The PS is configured to receive a bus signal issued by an upper computer, perform digital Gaussian filtering processing on the bus signal and transmit the processed signal to the PL signal processing module; meanwhile, collect and upload relevant data of the power amplifier.

[0010] The PL signal processing module is configured to receive the signal processed by the PS through digital Gaussian filtering, perform preprocessing on the signal, and transmit the processed signal to the high-voltage power circuit to control the high-voltage power circuit to perform power conversion operation on the load.

[0011] Optionally, the PS comprises a configuration management module, a network data interaction module and a digital Gaussian filter processing module.

[0012] The configuration management module is configured to receive a bus signal issued by an upper computer, perform initialization and configuration management on the PS according to the bus signal, convert the bus signal into a network data packet, and forward the network data packet to the network data interaction module.

[0013] The network data interaction module is configured to receive the network data packet sent by the configuration management module, perform frame format analysis and preprocessing on the network data packet, and send the signal data processed to the digital Gaussian filter processing module.

[0014] The digital Gaussian filter processing module is configured to receive the signal data sent by the network data interaction module, perform digital Gaussian filtering processing on the signal data, and send the signal data processed to the PL signal processing module.

[0015] Optionally, the configuration management module comprises a peripheral device driver initialization unit, an interrupt initialization unit, a memory configuration management unit and a data encapsulation forwarding unit.

[0016] The peripheral device driver initialization unit is configured to perform peripheral device driver initialization processing on the PS according to the received bus control signal.

[0017] The interrupt initialization unit is configured to configure the interrupt priority parameter of the network data interaction module according to the received bus control signal.

[0018] The memory configuration management unit is configured to divide the functional partitions of the DDR3 memory and manage the partition access rights according to the received bus control signal.

[0019] The data encapsulation and forwarding unit is configured to encapsulate the received bus data signal into a network data packet according to a preset frame format and forward the network data packet to the network data interaction module.

[0020] Optionally, the network data interaction module comprises a data verification unit and a preprocessing unit, and the network data packet comprises a digital Gaussian filter parameter group, a phase jump signal, a transmission start-stop command, and a transmission power level parameter to be transmitted; wherein:

[0021] The data verification unit is configured to perform verification and elimination processing on the received network data packet, filter valid signal data frames, parse the valid signal data frames according to a preset frame format protocol, extract various signal data, and store the various signal data in corresponding divided partitions of the DDR3 memory.

[0022] The preprocessing unit is configured to call the phase jump signal stored in the corresponding partition of the DDR3 memory, perform boundary extension and outlier filtering preprocessing on the phase jump signal, and send the preprocessed phase jump signal, the digital Gaussian filter parameter group, the transmission start-stop command, and the transmission power level parameter stored in the corresponding partition of the DDR3 memory to the digital Gaussian filter processing module after being aggregated.

[0023] Optionally, the digital Gaussian filter processing module comprises a parameter group switching unit, a filter coefficient calling unit, a window data reading unit, a multiply-accumulate operation unit, a sliding window processing unit, an error calibration unit, and a block iteration processing unit; wherein:

[0024] The parameter group switching unit is configured to receive the transmission power level parameter and the transmission start-stop command, determine the appropriate filter parameter specification according to the transmission power level parameter, switch to the corresponding filter parameter group in combination with the trigger signal of the transmission start-stop command, and call the filter coefficient plug-in pre-stored in the DDR3 memory that matches the current power level.

[0025] The filter coefficient calling unit is configured to call the filter coefficient plug-in pre-stored in the DDR3 memory that matches the current power level based on the filter parameter group determined by the parameter group switching unit.

[0026] The window data reading unit is configured to read the current window N-point data from the DDR3 ring buffer with the current data point to be processed as the center, and call preset extension data to intercept window data matching the Gaussian kernel size for boundary data points.

[0027] The multiply-accumulate operation unit is configured to read N-point filter coefficients corresponding to the current filter parameter group from the DDR3 memory coefficient area, and perform accumulation operation after multiplying the window data with the corresponding filter coefficients point by point to obtain the filter value of the current data point;

[0028] The sliding window processing unit is configured to slide the data processing window to the next data point to be processed, trigger the multiply-accumulate operation unit to repeatedly perform multiply-accumulate operation until the filter operation of all data points in the current data block is completed.

[0029] The error calibration unit is configured to perform calibration processing on the rounding error and truncation error generated in the filter operation process; perform abnormal value filtering processing on the calibrated filter data again to prevent the filter data from being wrong; and write the final calibrated filter result to the DDR3 memory filter result area.

[0030] The block iteration processing unit is configured to read the next block of preprocessed data from the DDR3 memory, and trigger the parameter group switching unit, the window data reading unit, the multiply-accumulate operation unit, the sliding window processing unit and the error calibration unit in turn to repeatedly perform the above processing steps until all the block preprocessed data is completed.

[0031] Optionally, the PS and PL signal processing modules of the system realize bidirectional data interaction through an AXI bus; the PL signal processing module includes a data processing module, a PWM modulation module and a PLL phase-locked loop module; wherein:

[0032] The data processing module is configured to receive the filtered signal data transmitted by the digital Gaussian filter processing module, perform preprocessing on the filtered signal data and transmit the preprocessed signal data to the PWM modulation module; at the same time, collect various operating data inside the power amplifier and transmit the operating data to the PS through the AXI bus.

[0033] The PWM modulation module is configured to receive the transformed signal data issued by the data processing module, convert the transformed signal data into a PWM driving signal, and send the PWM driving signal to the high-voltage power circuit to drive the high-voltage power circuit to perform power conversion on the load.

[0034] The PLL phase-locked loop module is configured to generate and output relevant clock signals required by all processing logics in the system to realize timing synchronization of the modules.

[0035] Optionally, the data processing module in the PL signal processing module includes a data verification unit and an amplitude limiting transformation unit; wherein:

[0036] The data verification unit is configured to receive the filtered signal data transmitted by the digital Gaussian filter processing module, perform validity verification processing on the filtered signal data, and transmit the signal data that passes the verification to the amplitude limiting transformation unit.

[0037] The amplitude limiting conversion unit is configured to receive the checked signal data transmitted by the data checking unit, perform amplitude limiting conversion processing on the checked signal data, and transmit the amplitude-converted signal data to the PWM modulation module.

[0038] The present application has the following beneficial effects:

[0039] The method provided by the present application adjusts the parameters of the digital Gaussian filter, so that the phase jump of the signal is smoothly transitioned, the sharp peaks of the output voltage and current of the power amplifier are suppressed, the stress of the high-voltage power circuit device in the later stage is reduced, the output power in the later stage is effectively improved, and the stability of the power amplifier is improved. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 The fitting time-domain waveform and phase change diagram of the jump signal of each power level are provided for the embodiments of the present application; Figure 1 (a) is a fitting time-domain waveform diagram of the jump signal of each power level; Figure 1 (b) is a fitting time-domain waveform diagram of the jump signal of each power level;

[0041] Figure 2 The details of the fitting time-domain waveform and phase change diagram of the jump signal of each power level are provided for the embodiments of the present application; Figure 2 (a) is a fitting time-domain waveform diagram of the jump signal of each power level; Figure 2 (b) is a fitting time-domain waveform diagram of the jump signal of each power level;

[0042] Figure 3 The frequency spectrum characteristic diagram of the signal before and after the digital Gaussian filtering of each power level is provided for the embodiments of the present application;

[0043] Figure 4 The structural block diagram of a control system for suppressing the sharp peaks of the output voltage and current of the power amplifier is provided for the embodiments of the present application;

[0044] Figure 5 The structural block diagram of the configuration management module is provided for the embodiments of the present application;

[0045] Figure 6 The structural block diagram of the network data interaction module is provided for the embodiments of the present application;

[0046] Figure 7 The structural block diagram of the digital Gaussian filter processing module is provided for the embodiments of the present application;

[0047] Figure 8 The structural block diagram of the data processing module is provided for the embodiments of the present application. DETAILED DESCRIPTION

[0048] In order to facilitate the understanding of those skilled in the art, the present application is further illustrated below in conjunction with examples and drawings, and the content mentioned in the embodiments is not a limitation on the present application.

[0049] The phase jump phenomenon of the signal is essentially a sharp mutation of the time-domain waveform of the signal, which further causes "spectrum diffusion" in the frequency domain. The phase jump phenomenon of the signal can cause the signal waveform to produce an abrupt edge at the time of the jump (such as a sine signal instantaneously jumping from a positive peak to a negative peak), which is not expected to occur at the output end of the actual power amplifier power, and is easy to cause spectrum leakage and is extremely easy to cause power amplifier output voltage and current spikes and further trigger protection shutdown and even damage the device.

[0050] The digital Gaussian filter is a low-pass filter in the frequency domain, which can effectively suppress high-frequency components in the signal. The jump of the signal (mutation in the time domain) usually corresponds to high-frequency components. By selecting a Gaussian filter with a suitable bandwidth to suppress these high-frequency components, the frequency spectrum of the signal can be controlled from the frequency domain, reducing the spectrum diffusion caused by the jump, thereby improving the phase continuity of the signal.

[0051] The present application provides a control system for suppressing power amplifier output voltage and current spikes, which is composed of two parts: a digital Gaussian filter simulation model design on a MATLAB simulation platform and a digital Gaussian filter program design on a digital processor platform ZYNQ series Soc.

[0052] The steps of the digital Gaussian filter simulation model design on the MATLAB simulation platform include:

[0053] 1. Analysis of the characteristics of the digital Gaussian filter shows that the digital Gaussian filter is a typical LTI system, and the filtering process is equivalent to the convolution of the input signal and the discrete Gaussian kernel. The discrete domain , wherein is the discrete Gaussian kernel (the weight decays exponentially with distance). The LTI system does not introduce new frequency components, but only suppresses noise by weighted averaging, which cannot be canceled by the weight of the surrounding stationary signal, thereby preserving the step trend of the jump. The discrete-time Fourier transform (DTFT) of the discrete Gaussian kernel is approximately a Gaussian low-pass function: , wherein is the standard deviation of the Gaussian kernel, Ts=1 / fs is the sampling period, is the angular frequency. Its cutoff frequency , by adjusting , the frequency characteristics of the jump can be accurately matched, and the noise reduction and jump preservation can be balanced. The digital Gaussian filter is a linear filter that realizes signal smoothing and noise reduction by convolving the input signal with the discrete Gaussian function as the filter kernel (unit impulse response). Assuming that the phase of the signal is , the signal after the Gaussian filter is where is a Gaussian kernel, denotes convolution. Convolution operation is actually a weighted average of the signal, and the weight is determined by the Gaussian kernel. In the vicinity of the jump point, the weighted average will mix the phase value of the point with the phase values of the surrounding points, thereby smoothing the jump. In signal processing, it is usually desirable that the filter does not introduce phase distortion. The Gaussian filter is an even function, so its phase response is zero, but the usual convolution will introduce delay. In order to achieve zero-phase filtering, bidirectional filtering (i.e. forward filtering and then reverse filtering, such as using the filtfilt function) can be used, which can obtain a zero-phase shift filtering result.

[0054] 2. Design a digital Gaussian filter model using the MATLAB simulation platform to analyze the characteristics of the band phase jump signal and the signal after filtering by the digital Gaussian filter. Since the output voltage and current spikes of the power amplifier are caused by signal phase jump, the voltage and current jump spikes are larger when the output power is larger, so a smoother filter is needed. The designed model can dynamically adjust the parameters of the digital Gaussian filter according to the power level, so that the power amplifier can maintain low distortion of the original signal at low power output, and maintain smaller phase jump spikes and smoother transition at high power output. The specific design steps are as follows:

[0055] 1. Generate phase jump signals of different power levels

[0056] Use MATLAB simulation to generate the excitation signal UI1, which is a signal carrying phase jump and can simulate the phase jump signal at the input end of the power amplifier. Its characteristic parameters are sampling frequency Fs=96Khz, sampling total time T_sum=1e-2s, carrier signal F0=2Khz. At 0.2*T_sum, 0.4*T_sum, 0.6*T_sum, 0.8*T_sum, the jump angles of 140°, -120°, -180°, -270° are generated. Based on the excitation signal UI1, use the correlation coefficients Coeff1=0.2, Coeff2=0.5, Coeff3=1 to generate three low, medium and high power level jump signals Uo1, Uo2, Uo3.

[0057] The gaussdesign function can be used to call the function kernel for filtering, and the characteristic parameters are the bandwidth-symbol time product bt, the filter truncation symbol length span, and the sample number of the symbol sps. A suitable bt value is determined for each power level. The larger the span, the closer the filter is to the ideal Gaussian filter, but the calculation amount increases. The sps is consistent with the oversampling rate of the system. The bt value is selected based on the voltage level, and the bandwidth is determined by the bt product. The smaller the bt product, the wider the bandwidth of the filter, the wider the time-domain pulse, and the better the smoothing effect. The larger the bt product, the narrower the frequency-domain bandwidth of the filter, and the steeper the pulse shaping.

[0058] The parameters of the digital Gaussian filter of three power levels are designed. A larger bt value is selected for the low power level to maintain signal quality, and the design parameters are calculated as bt=0.88, span=6, and sps3=8. A medium bt value is selected for the medium power level to balance filtering and signal quality, and the design parameters are calculated as bt=0.78, span=6, and sps3=8. A smaller bt value is selected for the high power level because the phase jump of the signal when the power amplifier performs high-power output will cause greater voltage and current stress and spikes, and therefore more smoothing filtering is needed. The design parameters are calculated as bt=0.68, span=6, and sps3=8. The above parameters are set respectively, and the digital Gaussian filter is used to perform digital filtering on the power signals of the three levels Uo1, Uo2, and Uo3. The digitally filtered signals are subjected to group delay compensation by the filtflt function, which is a zero-phase forward-backward filtering function and can eliminate the phase offset caused by the ordinary filter function.

[0059] The Hilbert transform is used on Uo1, Uo2, and Uo3 respectively to obtain the wrapped phase , wherein the range is Then, the instantaneous phase is obtained by unwrapping the wrapped phase. The phase unwrapping is performed on the signals of the three power levels Uo1, Uo2, and Uo3, and the linear phase degree is calculated. ,

[0060] The total square sum (the total fluctuation degree of the phase) , and the phase mean .

[0061] The time-domain waveforms and phase changes of the jump signals of the power levels are shown in Figure 1 , Figure 2 . Figure 1 (a) is a comparison waveform of the phase jump signals before and after digital Gaussian filtering of different power levels, Figure 1(b) is the phase angle (radian) of the signal jump moment. Figure 2 Expand the figure for details, Figure 2 (a) The phase jump is enlarged and clear, and the sharp peaks of the signals before and after digital Gaussian filtering at the phase jump moment change obviously. From the time domain, the jump point filtered by the digital Gaussian filter has a smooth transition, which is conducive to reducing the stress of the power amplifier output voltage and current and suppressing the voltage and current sharp peaks. Figure 2 (b) is the phase linearity of the signals before and after digital Gaussian filtering of each power level. The linear phase degrees R1^2 of the Uo1 signal and the filtered signal are 0.9991 and 0.9991, respectively. The linear phase degrees R2^2 of the Uo2 signal and the filtered signal are 0.9991 and 0.9993, respectively. The linear phase degrees R3^2 of the Uo3 signal and the filtered signal are 0.9991 and 0.9990, respectively. The closer R^2 is to 1, the better the linearity is. The filtered signals all meet the linear phase characteristics.

[0062] The spectral characteristics of the signals before and after digital Gaussian filtering of each power level are analyzed, as shown in Figure 3 From the frequency domain, the signal spectrum filtered by the digital Gaussian filter has no other frequency components, retains the original frequency information, and enables low-distortion transmission of effective information.

[0063] The digital Gaussian filter coefficient is derived

[0064] Based on the characteristics of the ZYNQ series Soc, the digital Gaussian filter parameters designed on the MATLAB simulation platform can be easily imported into the ZYNQ digital processor platform for implementation. The related design parameters of the digital Gaussian filter can be exported using the fopen function and the fprintf function to generate a coe file, which can facilitate the digital processor to update and call.

[0065] To solve the above technical problems, as shown in Figure 4 The control system for suppressing the voltage and current sharp peaks of the power amplifier adopts a PS (processing system) plus a PL signal processing module, and its specific working process is as follows:

[0066] The PS (Processing System) is the core of the power amplifier output peak suppression control system. Its core value lies in the precise execution of host computer instructions and the high-quality optimization of phase jump signals through the modular cooperation of "configuration-analysis-filtering", providing reliable input for the subsequent PL signal processing module and suppressing voltage and current peaks in the power conversion process from the source. The PS is configured to receive bus signal data issued by the host computer, perform digital Gaussian filter processing on the signal data, and transmit it to the PL signal processing module. At the same time, it obtains the running data of the power amplifier (such as output parameters, fault status, etc.) through a dedicated AXI communication interface and uploads it to the host computer, forming a closed-loop control of "instruction issuance-state feedback".

[0067] To achieve the above functions, as shown in Figure 4 The PS integrates three core submodules, namely the configuration management module, the network data interaction module, and the digital Gaussian filter processing module. The functions of each submodule are closely connected, forming a complete signal processing link. The specific configuration and implementation are as follows:

[0068] Configuration management module: system initialization and data conversion core

[0069] The configuration management module is the basic guarantee module for the startup and data input of the PS. It is responsible for converting the bus signal of the host computer into internal data recognizable by the system and completing the initialization configuration of hardware resources. The module is configured to receive bus signals issued by the host computer, perform comprehensive initialization and resource management of the PS according to the configuration instructions in the signal, encapsulate the data part of the signal into standardized network data packets, and forward them to the network data interaction module. As shown in Figure 5 The module integrates a peripheral driver initialization unit, an interrupt initialization unit, a memory configuration management unit, and a data encapsulation forwarding unit. The functions of each unit are as follows:

[0070] The peripheral driver initialization unit is configured to extract the peripheral configuration instructions in the bus control signal, perform driver initialization processing on various peripherals of the PS (such as bus interfaces, data acquisition interfaces, DDR memory controllers, etc.), and make the peripheral hardware enter the working state according to the preset protocol, ensuring smooth hardware paths for data transmission and acquisition.

[0071] The interrupt initialization unit is configured to set the interrupt priority of the network data interaction module according to the interrupt configuration parameters in the bus control signal. By setting the data reception, analysis, and other key tasks as high priority, it ensures that network data processing is not blocked when multiple modules are concurrent, improving the real-time performance of the system.

[0072] The memory configuration management unit is configured to respond to memory planning instructions in the bus control signals, perform functional partitioning of DDR3 memory, clearly define dedicated partitions such as parameter configuration area, raw signal area, ring buffer, and filtering result area, and configure independent read and write permissions and address mappings for each partition to avoid data storage conflicts between different modules and improve memory access efficiency.

[0073] The data encapsulation and forwarding unit is configured to: separate the data portion and control commands from the bus signals, encapsulate the data signals into network data packets according to a preset frame format (including frame header, data type, valid data, and check bits), and forward them to the network data interaction module through the internal high-speed link, providing standardized input for subsequent parsing and processing.

[0074] Network data interaction module: Data verification and preprocessing hub

[0075] The network data interaction module is a crucial link between the configuration management module and the digital Gaussian filter processing module. Its core function is to filter valid data, optimize signal quality, and complete data integration. This module is configured to: receive network data packets sent by the configuration management module, perform frame format parsing and preprocessing, and transmit the compliant signal data to the digital Gaussian filter processing module. Figure 6 As shown, it integrates a data verification unit and a preprocessing unit. The network data packets it processes cover digital Gaussian filter parameter sets, phase transition signals, transmit start / stop commands, and transmit power level parameters. The functions of each unit are as follows:

[0076] The data verification unit is configured to: perform integrity verification on the received network data packets using the CRC cyclic redundancy check algorithm, and remove invalid data packets with transmission errors or broken frame structures; parse valid data frames according to the preset frame format protocol, accurately extract four types of core data, and store them in the corresponding pre-partitioned partitions of DDR3 memory according to the memory partitioning rules, while recording the storage address for subsequent retrieval.

[0077] The preprocessing unit is configured to: call the phase transition signal stored in DDR3 memory through memory address index and perform targeted preprocessing on it—use a symmetric extension algorithm to complete the boundary de-extension to avoid boundary distortion in subsequent filtering; filter outliers and remove distorted data points through threshold judgment method; after preprocessing, summarize the optimized phase transition signal with the filter parameter group, transmit start / stop command and power level parameters stored in DDR3 memory to form a complete filter input dataset and send it to the digital Gaussian filter processing module.

[0078] The digital Gaussian filter processing module is a core functional module for realizing signal noise reduction optimization of the PS, and its core value lies in dynamically matching filter parameters and suppressing noise in phase jump signals through accurate operation to provide high-quality signals for subsequent power control. The module is configured as a whole to receive signal data transmitted by the network data interaction module, and transmit the results after performing digital Gaussian filter processing to the PL signal processing module. As shown in Figure 7 The seven functional units, i.e., the parameter group switching unit, the filter coefficient calling unit, the window data reading unit, the multiply-accumulate operation unit, the sliding window processing unit, the error calibration unit and the block iteration processing unit, are integrated inside, and work in cooperation to form a pipeline processing link, and the specific function implementations are as follows:

[0079] The parameter group switching unit is configured to receive the transmission power level parameter and the transmission start-stop command in the summary data, determine the filter bandwidth, smoothing coefficient and other specifications according to the power level parameter, and automatically switch to the corresponding filter parameter group in combination with the trigger logic of the transmission start-stop command, so as to ensure accurate matching of the filter configuration and the system working condition.

[0080] The filter coefficient calling unit is configured to call the target digital filter coefficient plug-in pre-stored in the corresponding power level partition through the DDR3 memory high-speed interface, taking the parameter group determined by the parameter group switching unit as an index, and ensure the coefficient integrity through a verification mechanism during calling.

[0081] The window data reading unit is configured to read N-point continuous data (N is consistent with the Gaussian kernel size) from the DDR3 ring buffer area with the current data point to be processed as the center; for the boundary data points, the preset symmetric extension data is called to fill the window, and finally the standardized window data matching the Gaussian kernel is formed.

[0082] The multiply-accumulate operation unit is configured to read the N-point filter coefficient corresponding to the current parameter group, multiply the window data and the coefficient point by point through a hardware acceleration architecture, and then accumulate to quickly obtain the filter value of the current data point, with the operation delay controlled in the microsecond level to meet the real-time requirement.

[0083] The sliding window processing unit is configured to slide the window along the signal sequence by one point after the processing of the current data point is completed, trigger the multiply-accumulate operation unit to repeatedly perform operation, and complete the processing of all data points in the current data block until the continuous filtering of the signal is realized.

[0084] The error calibration unit is configured to perform error calibration on the filter value of the current data block, correct the rounding error by using the rounding method and correct the truncation error by using the low-bit completion method; after calibration, the abnormal values are filtered again, and finally the high-quality results are written into the DDR3 filter result area.

[0085] The block iteration processing unit is configured to read the next block of data to be processed as a process control core, trigger parameter group re-switching preferentially if a power level or start-stop command update is detected, and then trigger each functional unit to repeat the processing procedure in turn until all block data is completed filtering.

[0086] The PL signal processing module is a key execution unit for connecting the PS and the high-voltage power circuit of the system, and the core value lies in converting the high-quality digital filtered signal output by the PS into a control signal that can directly drive the power device, while realizing real-time feedback of the operating state of the power amplifier. It builds a bidirectional data interaction link with the PS through the AXI bus, which not only guarantees the high speed of signal transmission, but also realizes closed-loop feedback of operating data. The PL signal processing module as a whole is configured to receive the signal data processed by the digital Gaussian filter and output by the PS, and perform preprocessing suitable for the high-voltage power circuit; transmit the processed driving signal to the high-voltage power circuit to accurately control its power conversion operation on the load.

[0087] To realize the above functions, as shown in Figure 4 The PL signal processing module internally integrates a data processing module, a PWM modulation module, and a PLL phase-locked loop module, which work in cooperation and are respectively responsible for signal optimization, drive generation, and timing control. The specific configuration and implementation are as follows:

[0088] Data processing module:

[0089] The data processing module is the "signal input hub and data feedback core" of the PL, responsible for interfacing the PS output signal and collecting the power amplifier state. As a whole, it is configured to receive the filtered signal data transmitted by the digital Gaussian filter processing module, perform preprocessing on the data, and transmit the data to the PWM modulation module; at the same time, it acquires various operating data (such as output voltage, current, device temperature, fault identification, etc.) of the power amplifier through a dedicated acquisition interface, and transmits the data back to the PS through the AXI bus, providing a basis for closed-loop regulation and control of the PS and the upper computer. As shown in Figure 8 The module internally integrates a data verification unit and an amplitude limiting and conversion unit, and the functions of each unit are as follows:

[0090] The data verification unit is configured to receive the filtered signal data transmitted by the PS, and perform validity verification using a dual verification mechanism of frame header matching + CRC verification - first filter the target data frame through the frame header identifier, then perform CRC verification on the data frame to eliminate error code data that may be introduced during transmission; real-time transmit the valid signal data that passes the verification to the amplitude limiting and conversion unit to ensure the reliability of the subsequent processing data.

[0091] The amplitude limiting and converting unit is configured to receive the checked signal data transmitted by the data checking unit, perform preprocessing on the input characteristics of the high-voltage power circuit, control the signal amplitude in the safe driving range of the power module through the amplitude limiting algorithm to avoid damage to the power device caused by the over-amplitude signal, and perform signal format conversion to convert the digital signal output by the PS into parallel data format that can be directly operated in the PL; and transmit the standardized signal data after amplitude limiting and conversion to the PWM modulation module to provide adaptive input for accurate modulation.

[0092] The PWM modulation module is the "power generation unit" of the PL, and its core function is to convert the optimized signal into a PWM driving signal recognizable by the high-voltage power circuit. The PWM modulation module is configured to receive the converted signal data issued by the data processing module, convert it into a PWM driving signal with adjustable duty cycle based on the power control instruction (such as the output power level) through the built-in PWM generator, and send the PWM driving signal to the high-voltage power circuit through the optocoupler isolation interface to accurately control the on-off timing and duty cycle of the power switch tube such as IGBT and MOSFET in the module, thereby driving the high-voltage power circuit to perform stable power conversion on the load according to the preset requirements and suppressing the generation of voltage and current spikes from the control level.

[0093] The PLL phase-locked loop module is the "timing control core" of the PL, which is configured to generate a reference clock through an external crystal oscillator, and output related clock signals (such as PS-PL interaction clock, PWM modulation clock, and data acquisition clock) required by all processing logics in the system after frequency multiplication and frequency division processing by the phase-locked loop circuit. The phase deviation of all clock signals is controlled within 1ns to ensure that the timing of data interaction between PS and PL, PWM modulation and power switch action, and running data acquisition is strictly synchronized, avoiding power signal conversion distortion and spike problems caused by timing disorder.

[0094] In summary, the method disclosed in the present application adjusts the parameters of the digital Gaussian filter to achieve smooth transition at the phase jump of the signal, thereby suppressing the voltage and current spikes of the power amplifier output, reducing the stress of the high-voltage power circuit device in the later stage, effectively improving the output power in the later stage, and improving the stability of the power amplifier.

[0095] The above embodiments are the preferred implementation schemes of the present application, and in addition to this, the present application can also be implemented in other ways, and any obvious substitutions without departing from the technical concept of the present application are within the protection scope of the present application.

[0096] In order to make the improvement of the present application more convenient for those skilled in the art to understand, some drawings and descriptions of the present application have been simplified, and some other elements have also been omitted in the present application file for the sake of clarity, and those skilled in the art should realize that these omitted elements can also constitute the content of the present application.

Claims

1. A control system for suppressing voltage and current spikes at the output of a power amplifier, characterized by, The system comprises a PS, a PL signal processing module and a high-voltage power circuit; wherein: The PS is configured to receive a bus signal issued by an upper computer, perform digital Gaussian filtering processing on the bus signal, and transmit the processed signal to the PL signal processing module; meanwhile, the PS collects and uploads relevant data of a power amplifier; The PL signal processing module is configured to receive the signal processed by the PS, perform preprocessing on the signal, and transmit the preprocessed signal to the high-voltage power circuit to control the high-voltage power circuit to perform power conversion operation on a load; The PS comprises a configuration management module, a network data interaction module and a digital Gaussian filter processing module; The digital Gaussian filter processing module comprises a parameter group switching unit, a filter coefficient calling unit, a window data reading unit, a multiplication and accumulation operation unit, a sliding window processing unit, an error calibration unit and a block iteration processing unit; wherein: The parameter group switching unit is configured to receive a transmission power level parameter and a transmission start-stop command, determine an adaptive filter parameter specification according to the transmission power level parameter, switch to a corresponding filter parameter group in combination with a trigger signal of the transmission start-stop command; The filter coefficient calling unit is configured to call a filter coefficient plug-in pre-stored in a DDR3 memory and matched with a current power level based on the filter parameter group determined by the parameter group switching unit; The window data reading unit is configured to read current window N-point data from a DDR3 ring buffer with a current data point to be processed as a center, and intercept window data matched with a Gaussian kernel size by calling preset extension data for boundary data points; The multiplication and accumulation operation unit is configured to read N-point filter coefficients corresponding to the current filter parameter group from a coefficient area of the DDR3 memory, multiply the window data with the corresponding filter coefficients point by point, and perform accumulation operation to obtain a filter value of the current data point; The sliding window processing unit is configured to slide the data processing window to the next data point to be processed, trigger the multiplication and accumulation operation unit to repeatedly perform multiplication and accumulation operation until the filter operation of all data points in the current data block is completed; The error calibration unit is configured to perform calibration processing on rounding errors and truncation errors generated in the filter operation process, perform abnormal value filtering processing on the calibrated filter data again to prevent errors in the filtered data, and write the final calibrated filter result to a filter result area of the DDR3 memory; The block iteration processing unit is configured to read next block preprocessed data from the DDR3 memory, trigger the parameter group switching unit, the window data reading unit, the multiplication and accumulation operation unit, the sliding window processing unit and the error calibration unit in sequence to repeatedly perform the above processing steps until all block preprocessed data is completed. The configuration management module is configured to receive a bus signal issued by an upper computer, perform initialization and configuration management on the PS according to the bus signal, receive and convert the bus signal into a network data packet, and forward the network data packet to the network data interaction module; 2. The system of claim 1, wherein, ​ ​ The network data interaction module is configured to receive the network data packet sent by the configuration management module, perform frame format analysis and preprocessing on the network data packet, and send the signal data after the analysis and preprocessing to the digital Gaussian filter processing module. The digital Gaussian filter processing module is configured to receive the signal data sent by the network data interaction module, perform digital Gaussian filter processing on the signal data, and send the signal data after the filter processing to the PL signal processing module.

3. The system of claim 2, wherein, The configuration management module includes a peripheral driver initialization unit, an interrupt initialization unit, a memory configuration management unit, and a data encapsulation forwarding unit; wherein: The peripheral driver initialization unit is configured to perform peripheral driver initialization processing on the PS according to the received bus control signal; The interrupt initialization unit is configured to configure the interrupt priority parameters of the network data interaction module according to the received bus control signal; The memory configuration management unit is configured to divide the functional partitions of the DDR3 memory and manage the partition access permissions according to the received bus control signal; The data encapsulation forwarding unit is configured to encapsulate the received bus data signal into a network data packet according to a preset frame format, and forward the network data packet to the network data interaction module.

4. The system of claim 3, wherein, The network data interaction module includes a data verification unit and a preprocessing unit, and the network data packet includes a digital Gaussian filter parameter group, a phase jump signal, a transmission start-stop command, and a transmission power level parameter to be transmitted; wherein: The data verification unit is configured to perform verification and rejection processing on the received network data packet, and screen valid signal data frames; analyze the valid signal data frames according to a preset frame format protocol, extract various signal data, and store the various signal data in corresponding divided partitions of the DDR3 memory respectively; The preprocessing unit is configured to call the phase jump signal stored in the corresponding partition of the DDR3 memory, perform boundary extension and outlier filtering preprocessing on the phase jump signal, and send the phase jump signal after the preprocessing, together with the digital Gaussian filter parameter group, the transmission start-stop command, and the transmission power level parameter stored in the corresponding partition of the DDR3 memory, to the digital Gaussian filter processing module.

5. The system of claim 4, wherein, The PS and the PL signal processing module of the system realize bidirectional data interaction through an AXI bus; the PL signal processing module includes a data processing module, a PWM modulation module, and a PLL phase-locked loop module; wherein: The data processing module is configured to receive the filtered signal data transmitted by the digital Gaussian filter processing module, perform preprocessing on the signal data, and transmit the preprocessed signal data to the PWM modulation module; at the same time, collect various operating data inside the power amplifier, and transmit the operating data to the PS through the AXI bus; The PWM modulation module is configured to receive the transformed signal data issued by the data processing module, convert the signal data into a PWM driving signal, and send the PWM driving signal to a high-voltage power circuit to drive the high-voltage power circuit to perform power conversion on a load; The PLL phase-locked loop module is configured to generate and output related clock signals required by all processing logics in the system to realize timing synchronization of the modules.

6. The system of claim 5, wherein, The data processing module in the PL signal processing module includes a data verification unit and a limiting and transforming unit; wherein: The data checking unit is configured to receive the filtered signal data transmitted by the digital Gaussian filter processing module, perform validity checking processing on the filtered signal data, and transmit the signal data that passes the checking to the amplitude conversion unit. The amplitude conversion unit is configured to receive the checked signal data transmitted by the data checking unit, perform amplitude conversion processing on the checked signal data, and transmit the signal data that has undergone the amplitude conversion to the PWM modulation module.

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