Low-delay sampler structure and method for high-speed data processing
By combining transconductance modules, pre-latch network modules, unlock network modules, and strong latch network modules, the problem of balancing sampling delay and power consumption in high-speed data processing is solved, and a low-latency, high-stability sampler design is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-23
- Publication Date
- 2026-03-27
AI Technical Summary
Existing samplers suffer from sampling delay issues in high-speed data processing, making it difficult to achieve an ideal balance between low power consumption and high performance.
A combined structure of transconductance module, pre-latch network module, unlock network module and strong latch network module is adopted. By switching between pseudo-reset and latching stages, the unlock network module provides a low impedance path for pre-sampling and preliminary amplification, and the strong latch network module ensures stable latching and reduces sampling delay.
It significantly shortens the signal sampling delay, meets the timing requirements of high-speed data processing, and maintains low power consumption, thereby improving the stability and efficiency of the sampler.
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Figure CN121749984A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of integrated circuit design technology, specifically relating to a low-latency sampler structure and method for high-speed data processing. This low-latency sampler can be widely used in electronic systems that require high-precision timing control, including but not limited to high-speed communication equipment, high-performance computing units, optoelectronic signal processing modules, analog-to-digital converters, and various integrated circuits that require fast data sampling. Background Technology
[0002] In high-speed integrated circuit design, the sampler, as a critical timing control unit, directly impacts the overall performance of the data acquisition, transmission, and processing system. While traditional sampler designs have achieved some optimization in terms of speed and power consumption, sampling delay becomes increasingly prominent in high-speed data processing scenarios, becoming a major bottleneck restricting system performance improvement. This limitation is particularly pronounced in applications with stringent timing requirements, such as high-speed communication, very large-scale integrated circuits, and optoelectronic signal processing.
[0003] Existing improvement solutions mainly reduce latency by transforming the transmission gate structure or compressing the critical path, but these methods often come at the cost of increased design complexity or reduced power consumption, making it difficult to achieve an ideal balance between low power consumption and high performance. Therefore, there is an urgent need in the field for a sampler solution that can significantly reduce sampling latency while maintaining low power consumption. Summary of the Invention
[0004] To address the shortcomings of existing technologies, this application aims to provide a low-latency sampler structure and method for high-speed data processing. It seeks to solve the problem that existing samplers reduce latency by transforming the transmission gate structure or compressing the critical path, but often at the cost of increased design complexity or power consumption, making it difficult to achieve an ideal balance between low power consumption and high performance.
[0005] This application relates to a low-latency sampler structure for high-speed data processing, comprising: a transconductance module, a pre-latch network module, an unlock network module, and a strong latch network module; The pre-latch network module and the unlock network module are connected to the transconductance module; the pre-latch network module is connected to the strong latch network module. During the pseudo-reset phase, the unlock network module is in the on state and the strong latch network module is in the off state; the unlock network module and the pre-latch network module are connected in parallel to form an equivalent low impedance network unit; the transconductance module is used to input the sampling signal and the reference level signal to drive the equivalent low impedance network unit; the pre-latch network module is used to pre-sample the sampling signal when its output node starts charging and discharging according to the sampling signal and the reference level signal. During the latching phase, the unlocking network module is in the off state, the strong latching network module is in the on state, the transconductance module is used to drive the pre-latching network module to perform preliminary amplification of the sampled signal; the strong latching network module is used to stably latch the sampled signal under the drive of the pre-latching network module.
[0006] In some implementations, the transconductance module includes a first transistor, a second transistor, and a tail current source; The sources of the first and second transistors are connected to the drains of the tail current source, and the drains are connected to the pre-latch network module and the unlock network module; the source of the tail current source is grounded; the gate of the first transistor is used to input the sampling signal; the gate of the second transistor is used to input the reference level signal; the gate of the tail current source is used to input the fixed bias current; during the pseudo-reset phase, the first and second transistors are used to generate a current signal based on the difference between the sampling signal and the reference level signal, driving the equivalent low impedance network unit; during the latching phase, the first and second transistors are used to drive the pre-latch network module to initially amplify the sampling signal.
[0007] In some implementations, the pre-latch network module includes a cross-coupled fourth transistor and a fifth transistor; the drain of the fourth transistor is connected to the drain of the first transistor; the drain of the fifth transistor is connected to the drain of the second transistor; and the sources of the fourth and fifth transistors are connected to a power supply. During the pseudo-reset phase, the fourth and fifth transistors are used to enhance the changing trend of the node voltage through cross-coupling feedback, so that the output node presamples the sampling signal during the pseudo-reset phase. During the latching phase, the fourth transistor and the fifth crystal are used to drive the strong-lock network module with node voltage to generate a pull-down start signal.
[0008] In some implementations, the unlocking network module includes a sixth transistor and a seventh transistor. During the pseudo-reset phase, the sixth and seventh transistors are used to turn on the gate when the clock signal is high. The drain of the sixth transistor is connected to the drain of the first transistor, and the drain of the seventh transistor is connected to the drain of the second transistor. The sources of the sixth and seventh transistors are connected to the power supply, forming an equivalent low-impedance network cell for charging and discharging the output node of the transconductance module, thereby causing the node voltage of the pre-latch network module to begin to change.
[0009] In some implementations, the strong latch network module includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; The gates of the eighth and ninth transistors are connected to the drains of the fourth and fifth transistors, respectively; the tenth and twelfth transistors are connected to form the first inverter, and the eleventh and thirteenth transistors are connected to form the second inverter. The first and second inverters are cross-coupled to form a strong positive feedback latch unit. The drain of the eighth transistor is connected to the drain of the tenth transistor; the drain of the ninth transistor is connected to the drain of the eleventh transistor; the source of the fourteenth transistor is connected to the power supply, and its drain is connected to the source of the twelfth and thirteenth transistors. During the latching phase, the gate of the fourteenth transistor is used to receive the inverted clock signal, and the node potential connected to its drain is pulled high. The strong positive feedback latch unit is activated to stably latch the sampled signal.
[0010] In some implementations, the transconductance module includes a first transistor, a second transistor, a tail current source, a third transistor, a fourth transistor, and a sixth transistor; The first and second transistors form a differential pair, and the third and fourth transistors form another differential pair. The sources of the first and second transistors are connected to the drain of the tail current source; the sources of the third and fourth transistors are connected to the drain of the sixth transistor; the two differential pairs are used to input the sampling signal and the reference level signal, respectively.
[0011] In some implementations, the strong latch network module further includes a fifteenth transistor, a sixteenth transistor, a first inverter, and a second inverter to improve latching speed; The input of the first inverter is connected to the drain of the fourth transistor, and the input of the second inverter is connected to the drain of the fifth transistor. The output of the first inverter is connected to the gate of the fifteenth transistor. The drain of the fifteenth transistor is connected to the drain of the twelfth transistor, and its source is connected to the drain of the fourteenth transistor. The output of the second inverter is connected to the gate of the sixteenth transistor. The drain of the sixteenth transistor is connected to the drain of the thirteenth transistor, and its source is connected to the drain of the fourteenth transistor.
[0012] The second aspect of this application relates to a method for operating a low-latency sampler structure for high-speed data processing, specifically: During the pseudo-reset phase, clock control is used to unlock the network module and disable the strong latch network module; the sampling signal and the reference level signal are input to the transconductance module, which in turn drives the equivalent low impedance network module, causing the output node of the pre-latch network module to charge and discharge, and pre-sample the sampling signal; During the latching phase, the clock-controlled unlocking network module is turned off and the strong latching network module is turned on. The transconductance module is used to drive the pre-latching network module to achieve preliminary amplification of the sampled signal so that the strong latching network module can stably latch it.
[0013] Overall, the technical solutions conceived in this application have the following beneficial effects compared with the prior art: Compared to the traditional "full reset-latch" mode, this application provides a low-latency sampler for high-speed data processing. During the pseudo-reset phase, the unlocking network module and the pre-latch network module are connected in parallel to form an equivalent low-impedance network unit. Based on this, the transconductance module can drive the equivalent low-impedance network unit, enabling the pre-latch module to pre-sample the sampled signal during the pseudo-reset phase. Simultaneously, during the latching phase, the transconductance module drives the pre-latch network module to initially amplify the sampled signal, significantly shortening the signal sampling delay. Furthermore, the design of the strong latch network module ensures the stability of the sampler output, meeting the timing requirements of high-speed data processing. Attached Figure Description
[0014] Figure 1 This is a schematic diagram of the sampler structure architecture provided in the embodiments of this application.
[0015] Figure 2 This is a schematic diagram of the sampler circuit structure provided in the first embodiment of this application.
[0016] Figure 3 This is a schematic diagram of the sampler circuit structure provided in the second embodiment of this application.
[0017] Figure 4 This is a schematic diagram of the sampler circuit structure provided in the third embodiment of this application.
[0018] Figure 5 This is a simulation result comparing the circuit of the second embodiment provided in this application with a traditional sampler circuit. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0020] In this application, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A existing alone, A and B existing simultaneously, and B existing alone. In this application, the symbol " / " indicates that the related objects are in an "or" relationship, for example, A / B means A or B.
[0021] In this application, the terms “first” and “second” are used to distinguish different objects, rather than to describe a specific order of objects.
[0022] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.
[0023] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more.
[0024] The embodiments of this application are described below with reference to the accompanying drawings.
[0025] like Figure 1 As shown, this application provides a low-latency sampler structure for high-speed data processing, including a transconductance module, a pre-latch network module, an unlock network module, and a strong latch network module; the sampling clock controls the unlock network module and the strong latch network module to realize the switching of the circuit working stages and complete the data sampling and latching function.
[0026] The operation of the low-latency sampler consists of two stages: Pseudo-reset phase: The clock-controlled unlock network module is turned on, and the strong latch network module is turned off; the sampling signal and the reference level are input to the transconductance module, which drives the equivalent low-impedance network unit composed of the unlock network module and the pre-latch network module connected in parallel; since the strong latch network module is turned off, the sampler output is in a reset state, while the output node of the pre-latch network module has started charging and discharging according to the sampling signal, that is, the sampling signal has been pre-sampled. Therefore, a faster response can be achieved in the next working phase of the sampler, thereby reducing the sampling delay; Latching phase: The clock-controlled unlocking network module is turned off, and the strong latching network module is turned on; at this time, the transconductance module drives the pre-latching network module to complete the initial pre-latching, realize signal amplification, and quickly turn on the strong latching network module to achieve stable latching; Compared to the traditional sampler's operating mode, namely the full reset-latch operating mode, the sampler proposed in this application can respond to the sampling signal more quickly and reduce sampling delay.
[0027] First Embodiment Figure 2 This is the first embodiment provided in this application, applicable to single-ended signal sampling that requires a reference level, and differential signal sampling that does not require a reference level; The transconductance module includes a first transistor M1, a second transistor M2, and a tail current source (implemented here using a fixed-bias third transistor M3). Figure 2 In this process, the sampling signal and the reference level are input from the gates of the first transistor M1 and the second transistor M2, respectively; The pre-latch network module includes a cross-coupled fourth transistor M4 and a fifth transistor M5; the drains of the fourth transistor M4 and the fifth transistor M5 are connected to the drains of the first transistor M1 and the second transistor M2, respectively; the sources of the fourth transistor M4 and the fifth transistor M5 are connected to the power supply VDD. The unlocking network module includes a sixth pull-up transistor M6 and a seventh pull-up transistor M7 with clock-controlled gates. The drains are connected to the drains of the first transistor M1 and the second transistor M2, respectively, and the source is connected to the power supply VDD. The strong latch network module includes transistors M8 (eighth), M9 (ninth), M10 (tenth), M11 (eleventh), M12 (twelfth), M13 (thirteenth), and M14 (fourteenth). The output of the pre-latch network module drives the gates of transistors M8 and M9, generating a pull-down start signal. Transistors M10 and M12 are connected to form an inverter, and the same applies to transistors M11 and M13. The two pairs of inverters are cross-coupled to form a strong positive feedback latch unit. Transistor M14 is controlled by a clock (inverted CKB), with its source connected to the power supply VDD and its drain connected to the sources of transistors M12 and M13, controlling the turn-on and turn-off of the strong latch network module. The specific work process is described as follows: (1) False reset phase: During the pseudo-reset phase, the clock signal controls the unlocking network module to turn on, while the strong latching network module turns off. Transconductance module operation: The sampling signal is input from the gate of the first transistor M1, and the reference level is input from the gate of the second transistor M2; the first transistor M1 and the second transistor M2 together with the tail current source M3 constitute the transconductance module. At this time, the tail current source M3 provides a fixed bias current, and the first transistor M1 and the second transistor M2 generate a current signal according to the difference between the sampling signal and the reference level. Unlocking network module operation: The high level of the clock signal turns on the gates of the sixth transistor M6 and the seventh transistor M7, connecting the unlocking network module (sixth transistor M6 and seventh transistor M7) to the drain of the transconductance module. Since the sources of the sixth transistor M6 and the seventh transistor M7 are connected to the power supply VDD, their conduction forms an equivalent low impedance path, which quickly charges and discharges the output node of the transconductance module, thereby causing the node voltage of the pre-latch network module to start changing. The function of the pre-latch network module: The fourth transistor M4 and the fifth transistor M5 form a cross-coupled pre-latch network, and their drains are connected to the drains of the first transistor M1 and the second transistor M2, respectively. The fourth transistor M4 and the fifth transistor M5 enhance the trend of voltage signal change through cross-coupling feedback, so that the output node starts to pre-sample the sampling signal in the pseudo-reset stage, and the charging and discharging process lays the foundation for the fast response of the next stage. Output status: Since the strong latch network is off during this stage (the fourteenth transistor M14 is off), the sampler's output node is disconnected and remains in the reset state.
[0028] (2) Locking phase During the latching phase, the clock signal controls the unlocking network module to turn off, while the strong latching network module turns on. Transconductance module and pre-latch network module: The sixth transistor M6 and the seventh transistor M7 in the unlock network module are turned off under the action of the clock signal, cutting off the low impedance path; at this time, the first transistor M1 and the second transistor M2 in the transconductance module continue to drive the fourth transistor M4 and the fifth transistor M5 in the pre-latch network module to complete the initial amplification of the sampled signal; Start-up of the strong latch network module: The output node voltage of the pre-latch network module drives the gates of the eighth transistor M8 and the ninth transistor M9 in the strong latch network module to generate a pull-down start signal; the tenth transistor M10 and the twelfth transistor M12, as well as the eleventh transistor M11 and the thirteenth transistor M13, form two pairs of cross-coupled inverters to form a strong positive feedback latch unit. When the fourteenth transistor M14 is turned on by the inverted clock CKB, the node potential connected to its drain is quickly pulled up, the strong positive feedback latch unit is activated, and the rapid and stable latching of the sampled signal is completed. Output state: Due to the high gain characteristics of the strong positive feedback unit, the output node of the sampler quickly reaches a stable state and latches the sampled signal.
[0029] Second Embodiment Furthermore, such as Figure 3 The second embodiment of this application is shown. Based on the first embodiment, the transconductance module is improved to a fully differential form to realize the sampling and latching of the fully differential signal with reference level. The first transistor M1 and the second transistor M2 form a differential pair, and the fifth transistor M5 with fixed bias is used as the tail current source. The third transistor M3, the fourth transistor M4 and the sixth transistor M6 similarly form another differential pair with tail current. The positive and negative terminals of the sampling signal and the reference signal are respectively input by the two differential pairs. The working principle of other network modules is the same as that of the first embodiment.
[0030] Third Embodiment Furthermore, such as Figure 4The third embodiment provided in this application, based on the second embodiment, adds a first inverter INV1 and a pull-up thirteenth transistor M13, a second inverter INV2 and a pull-up fourteenth transistor M14 to the strong latch network module. Its function is to increase the pull-up latch branch of the strong latch network and further improve the latching speed. In actual design, the parameters of the first inverter INV1, the second inverter INV2, the thirteenth transistor M13 and the fourteenth transistor M14 are reasonably designed to achieve a trade-off between node parasitic effects and pull-up speed.
[0031] Figure 5 The diagram shows a comparison of simulation results between the second embodiment of this application and a conventional sampler. The first row of waveforms represents the sampling signal and the sampling clock waveform. The second row represents the sampling results of the two samplers. The red line represents the low-latency sampler proposed in this application, and the blue line represents the conventional sampler. The vertical dashed line indicates the clock level transition time. Both samplers enter the latching stage simultaneously. It can be seen that the time for the proposed sampler to reach the effective level (VDD / 2) is reduced by 30% compared to the conventional structure.
[0032] Compared to the traditional "full reset-latch" mode, this application provides a low-impedance path during the pseudo-reset phase by unlocking the network module. Combined with the signal amplification characteristics of the pre-latch network module, the signal sampling delay is significantly shortened. At the same time, the design of the strong latch network module ensures the stability of the sampler output and meets the timing requirements of high-speed data processing.
[0033] It should be understood that expressions such as “comprising” and “may include” used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as “comprising” and / or “having” are to be interpreted as indicating a particular characteristic, number, operation, constituent element, component, or combination thereof, but not to exclude the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.
[0034] Furthermore, in this application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.
[0035] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium.
[0036] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A low-latency sampler architecture for high-speed data processing, characterized by, The transconductance module, the pre-latch network module, the unlock network module and the strong latch network module are connected in series. The pre-latch network module and the unlock network module are connected with the transconductance module; the pre-latch network module is connected with the strong latch network module. In the pseudo-reset phase, the unlock network module is in the open state, and the strong latch network module is in the closed state; the unlock network module and the pre-latch network module are connected in parallel to form an equivalent low-impedance network unit; the transconductance module is used for inputting a sampling signal and a reference level signal and driving the equivalent low-impedance network unit; the pre-latch network module is used for starting charging and discharging at its output node according to the sampling signal and the reference level signal to pre-sample the sampling signal. In the latch phase, the unlock network module is in the closed state, and the strong latch network module is in the open state; the transconductance module is used for driving the pre-latch network module to preliminarily amplify the sampling signal; the strong latch network module is used for stably latching the sampling signal under the driving of the pre-latch network module.
2. The low-latency sampler architecture of claim 1, wherein, The transconductance module comprises a first transistor, a second transistor and a tail current source. The sources of the first transistor and the second transistor are connected with the drain of the tail current source, and the drains thereof are connected with the pre-latch network module and the unlock network module; the source of the tail current source is grounded; the gate of the first transistor is used for inputting the sampling signal; and the gate of the second transistor is used for inputting the reference level signal. The gate of the tail current source is used for inputting a fixed bias current. In the pseudo-reset phase, the first transistor and the second transistor are used for generating a current signal according to the difference between the sampling signal and the reference level signal to drive the equivalent low-impedance network unit. In the latch phase, the first transistor and the second transistor are used for driving the pre-latch network module to preliminarily amplify the sampling signal.
3. The low-latency sampler architecture of claim 2, wherein, The pre-latch network module comprises cross-coupled fourth and fifth transistors; the drain of the fourth transistor is connected with the drain of the first transistor; the drain of the fifth transistor is connected with the drain of the second transistor; and the sources of the fourth and fifth transistors are connected with a power supply. In the pseudo-reset phase, the fourth and fifth transistors are used for enhancing the change trend of the node voltage through cross-coupled feedback, so that the output node pre-samples the sampling signal in the pseudo-reset phase; in the latch phase, the fourth and fifth transistors are used for driving the strong latch network module with the node voltage.
4. The low-latency sampler architecture of claim 3, wherein, The unlock network module comprises sixth and seventh transistors; in the pseudo-reset phase, the sixth and seventh transistors are used for being opened under the control of the high level of the clock signal; the drain of the sixth transistor is connected with the drain of the first transistor, the drain of the seventh transistor is connected with the drain of the second transistor, and the sources of the sixth and seventh transistors are connected with a power supply to form an equivalent low-impedance network unit, which is used for charging and discharging the output node of the transconductance module, so that the node voltage of the pre-latch network module starts to change.
5. The low-latency sampler architecture of claim 4, wherein, The strong latch network module comprises eighth, ninth, tenth, eleventh, twelfth, thirteenth and fourteenth transistors. The gates of the eighth transistor and the ninth transistor are connected with the drains of the fourth transistor and the fifth transistor respectively; the tenth transistor and the twelfth transistor are connected to form a first inverter, the eleventh transistor and the thirteenth transistor are connected to form a second inverter, the first inverter and the second inverter are cross-coupled to form a strong positive feedback latch unit, the drain of the eighth transistor is connected with the drain of the tenth transistor; the drain of the ninth transistor is connected with the drain of the eleventh transistor; the source of the fourteenth transistor is connected with the power supply, and the drain thereof is connected with the sources of the twelfth transistor and the thirteenth transistor; In the latch stage, the gate of the fourteenth transistor is used for receiving an inverted clock signal, the potential of the node connected with the drain thereof is pulled up, and the strong positive feedback latch unit is activated to stably latch the sampling signal.
6. The low-latency sampler architecture of claim 1, wherein, The transconductance module comprises a first transistor, a second transistor, a tail current source, a third transistor, a fourth transistor and a sixth transistor; The first transistor and the second transistor form a pair of differential pairs, the third transistor and the fourth transistor form another pair of differential pairs, and the sources of the first transistor and the second transistor are connected with the drain of the tail current source; the sources of the third transistor and the fourth transistor are connected with the drain of the sixth transistor; the two pairs of differential pairs are respectively used for inputting a sampling signal and a reference level signal.
7. The low-latency sampler architecture of claim 5, wherein, The strong latch network module further comprises a fifteenth transistor, a sixteenth transistor, a first inverter and a second inverter, which are used for improving the latch speed; The input of the first inverter is connected with the drain of the fourth transistor, and the input of the second inverter is connected with the drain of the fifth transistor; The output end of the first inverter is connected with the gate of the fifteenth transistor; the drain of the fifteenth transistor is connected with the drain of the twelfth transistor, and the source thereof is connected with the drain of the fourteenth transistor; The output end of the second inverter is connected with the gate of the sixteenth transistor; the drain of the sixteenth transistor is connected with the drain of the thirteenth transistor, and the source thereof is connected with the drain of the fourteenth transistor.
8. A method of operating a low-latency sampler structure according to any one of claims 1 to 7, characterized by, Specifically: In the pseudo-reset stage, the clock control unlocking network module is opened, and the strong latch network module is closed; the sampling signal and the reference level signal are input into the transconductance module, and then the equivalent low-impedance network module is driven, so that the output node of the pre-latch network module is charged and discharged, and the sampling signal is pre-sampled; In the latch stage, the clock control unlocking network module is closed, and the strong latch network module is opened; the transconductance module is used to drive the pre-latch network module, so as to realize the preliminary amplification of the sampling signal, so as to stably latch the strong latch network module.