Body-side all-in-one machine chip module design system based on multi-scale feature embedding fusion
By designing a multi-scale feature-embedded integrated chip module for body measurement, the scoring and data analysis of volleyball matches were optimized, solving the problems of scoring difficulties and insufficient teaching resources in volleyball matches, and achieving efficient and accurate scoring and data processing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-17
- Publication Date
- 2026-04-03
AI Technical Summary
In volleyball matches, there are difficulties in determining the point of contact and scoring. There is a shortage of teaching staff, which leads to inaccurate judgments and a lack of data analysis. Existing scoring equipment is costly and inefficient.
The design of a body-side integrated chip module based on multi-scale feature embedding fusion includes a chip data acquisition module, a module design module, and a creation module. The circuit component parameters are optimized through evolutionary algorithms, and fitness evaluation is performed by combining intelligent simulation and surrogate models. The chip layout is optimized to improve the scoring accuracy and efficiency.
It enables efficient and accurate scoring and data analysis in volleyball matches, reducing costs and improving teaching efficiency and data processing capabilities.
Smart Images
Figure CN121787352A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of chip module design technology, specifically relating to a body-side integrated chip module design system based on multi-scale feature embedding and fusion. Background Technology
[0002] A scoreboard is a tool used during competitions to record and calculate athletes' scores. Current improvements to scoreboards mainly involve replacing traditional paper scoreboards with electronic scoreboards, or using Bluetooth remote control. Alternatively, improvements can be made to the scoreboard's size, making it more compact and portable.
[0003] Among various ball sports, from a scoring perspective, football is the simplest, while tennis and basketball are the most complex. The applicant wants to point out that in volleyball, determining the boundary point and scoring presents certain challenges. Having worked on the front lines of physical education teaching for many years, specifically at the volleyball management center on campus, the applicant has observed the following shortcomings in current campus volleyball teaching and training: 1. There is a severe shortage of teaching staff, especially for referee positions within the curriculum. Students are readily available, but referees are difficult to find. Temporarily assigning students as linesmen or assistant referees often results in poor judgment and hinders training progress due to the students' lack of basic knowledge.
[0004] At the same time, due to cost constraints, current classroom teaching cannot be equipped with big data analysis instruments. Furthermore, due to the aforementioned shortage of manpower, there is often a lack of data analysis for the training session after the training session. Therefore, providing a chip module for physical assessment is a problem that needs to be solved. Summary of the Invention
[0005] This invention addresses the problems of existing technologies. The technical solution adopted in this application is: a body-side integrated chip module design system based on multi-scale feature embedding and fusion, comprising: The chip data acquisition module acquires information about the chip's electronic components, determines suitable electronic components and circuit topology based on requirements to achieve the specific functions required by the chip, and identifies two or more indicators of the chip as optimization targets. The chip module design module selects an encoding method to encode the circuit component parameters, representing N individuals in the evolutionary algorithm as decision variables; initializes N individuals, representing different circuit component parameters; evaluates the fitness of the initialized N individuals; obtains the results of the target circuit performance of the N individuals using intelligent simulation tools; performs the offspring generation operator operation in the evolutionary algorithm on the N individuals to obtain N offspring, and represents the component parameters of the N offspring; evaluates the fitness of the N offspring based on iterative selection; if the number of evolutionary iterations is odd, the fitness is evaluated using a realistic intelligent simulation tool; if the number of evolutionary iterations is even, the fitness is evaluated using an ensemble surrogate model. The chip creation module is responsible for creating and updating the optimal file. It establishes an optimal individual file to store N optimal individuals. In the initial state, the file contains some or all of the N individuals. Then, it updates the optimal individuals in the current file based on multi-model random sorting and Pareto dominance.
[0006] Furthermore, the chip data acquisition module first determines the defective chip layout information and the target chip layout scheme. The defective chip layout information includes multiple defective chip layout schemes under multiple chip layout defect types and defective chip layout description vectors corresponding to the multiple defective chip layout schemes. Each defective chip layout scheme corresponds to a defective chip layout description vector. The defective chip layout information and the target chip layout scheme are used to describe the layout status of the corresponding multilayer interconnect chips.
[0007] Furthermore, the defective chip layout scheme refers to a scheme with defective problems, which belong to the corresponding chip layout defect type. The chip layout defect type includes at least electromagnetic isolation defects and heat dissipation defects. The electromagnetic isolation defect refers to electromagnetic interference between multilayer stacked wirings. The defective chip layout scheme also has a corresponding optimized chip layout scheme. The optimized chip layout scheme refers to the scheme formed after optimizing the defects in the defective chip layout scheme. The target chip layout scheme belongs to the scheme with defective problems and needs to be optimized.
[0008] Furthermore, the target chip layout scheme is vectorized to output the target chip layout description vector corresponding to the target chip layout scheme.
[0009] Furthermore, the chip module design module performs knowledge graph determination processing based on the target chip layout description vector and the defective chip layout description vectors corresponding to the multiple defective chip layout schemes, and outputs the corresponding chip layout scheme graph. The chip scheme members in the chip layout scheme graph include a first chip scheme member and multiple second chip scheme members. The first chip scheme member corresponds to the target chip layout scheme, and each second chip scheme member corresponds to a defective chip layout scheme.
[0010] Furthermore, the chip creation module combines the deep chip layout vectors at multiple levels and performs multi-level second feature mining processing on the chip layout optimization vectors to obtain optimized chip layout vectors at multiple levels. The optimized chip layout vectors are used to reflect the feature information of the integrated chip to be optimized in the two dimensions of chip model data and chip layout optimization data.
[0011] Compared with the prior art, the advantages and positive effects of the present invention are as follows: This invention provides a chip module design system for a body-side integrated machine based on multi-scale feature embedding fusion, comprising: a chip data acquisition module, which acquires the electronic component information of the chip, determines suitable electronic components and circuit topology according to requirements to achieve the specific functions required by the chip; and determines two or more indicators of the chip as optimization targets; and establishes an optimal individual file to store N optimal individuals. In the initial state, the file contains some or all of the N individuals. Then, based on multi-model random sorting and Pareto dominance, the optimal individuals in the current file are updated. The restored chip model optimization data can optimize performance issues while ensuring matching with the original chip layout features. Moreover, no manual iteration is required during the optimization process. In various ball games, configuring the chip for big data analysis can effectively improve the efficiency and accuracy of sports score processing, thus improving the low efficiency and high cost of multi-chip integrated layout design in existing technologies. In other words, it has the advantages of reliability, efficiency, and cost-effectiveness in scheme optimization. Attached Figure Description
[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0013] Figure 1 This is a schematic diagram of the structure of the body-side integrated chip module design system based on multi-scale feature embedding and fusion according to the present invention. Detailed Implementation
[0014] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.
[0015] Numerous specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways than those described herein, and therefore the invention is not limited to the specific embodiments disclosed in the following specification.
[0016] Example 1, as Figure 1 As shown, this application provides a body-side integrated chip module design system based on multi-scale feature embedding and fusion, including: The chip data acquisition module acquires information about the chip's electronic components, determines suitable electronic components and circuit topology based on requirements to achieve the specific functions required by the chip, and identifies two or more indicators of the chip as optimization targets. The chip module design module selects an encoding method to encode the circuit component parameters, representing N individuals in the evolutionary algorithm as decision variables; initializes N individuals, representing different circuit component parameters; evaluates the fitness of the initialized N individuals; obtains the results of the target circuit performance of the N individuals using intelligent simulation tools; performs the offspring generation operator operation in the evolutionary algorithm on the N individuals to obtain N offspring, and represents the component parameters of the N offspring; evaluates the fitness of the N offspring based on iterative selection; if the number of evolutionary iterations is odd, the fitness is evaluated using a realistic intelligent simulation tool; if the number of evolutionary iterations is even, the fitness is evaluated using an ensemble surrogate model. The chip creation module is responsible for creating and updating the optimal file. It establishes an optimal individual file to store N optimal individuals. In the initial state, the file contains some or all of the N individuals. Then, it updates the optimal individuals in the current file based on multi-model random sorting and Pareto dominance.
[0017] The chip data acquisition module first determines the defective chip layout information and the target chip layout scheme. The defective chip layout information includes multiple defective chip layout schemes under multiple chip layout defect types and defective chip layout description vectors corresponding to the multiple defective chip layout schemes. Each defective chip layout scheme corresponds to a defective chip layout description vector. The defective chip layout information and the target chip layout scheme are used to describe the layout status of the corresponding multilayer interconnect chips. The defective chip layout scheme refers to a scheme with defect problems, which belong to the corresponding chip layout defect type. The chip layout defect types include at least electromagnetic isolation defects and heat dissipation defects. The electromagnetic isolation defect refers to electromagnetic interference between multilayer interconnect wirings. The defective chip layout scheme also has a corresponding optimized chip layout scheme. The optimized chip layout scheme is a scheme formed after optimizing the defects in the defective chip layout scheme. The target chip layout scheme is a scheme with defects that needs to be optimized. The target chip layout scheme is vectorized to output the target chip layout description vector corresponding to the target chip layout scheme. The chip module design module performs knowledge graph determination processing based on the target chip layout description vector and the defective chip layout description vectors corresponding to the multiple defective chip layout schemes, and outputs the corresponding chip layout scheme graph. The chip scheme members in the chip layout scheme graph include a first chip scheme member and multiple second chip scheme members. The first chip scheme member corresponds to the target chip layout scheme, and each second chip scheme member corresponds to a defective chip layout scheme. Based on the chip layout scheme map, among the multiple defective chip layout schemes, the relevant defective chip layout schemes corresponding to the target chip layout scheme are determined, and the optimized chip layout schemes corresponding to the relevant defective chip layout schemes are used as the basis for optimizing the defects in the target chip layout scheme.
[0018] The chip model data and chip layout optimization data of the integrated chip to be optimized are determined. The integrated chip to be optimized is an integrated chip that stacks multiple sub-chips and / or multiple devices on multiple cavities on the front and back sides of a substrate. The chip model data is formed by three-dimensional modeling of the integrated chip to be optimized. The chip layout optimization data is formed by simulation of the chip model data. The chip layout optimization data is used to reflect the performance problems of the integrated chip to be optimized. The performance problems include at least one of the following: problems related to airtightness, problems related to chip volume, problems related to structural stability, and problems related to heat dissipation. The chip model data and the chip layout optimization data are subjected to feature extraction processing respectively, and the chip layout vector corresponding to the chip model data and the chip layout optimization vector corresponding to the chip layout optimization data are output. The chip layout vector is subjected to multi-level first feature mining processing to output the deep chip layout vector of the integrated chip to be optimized at multiple levels, as reflected by the chip model data. The chip creation module combines the deep chip layout vectors at multiple levels and performs multi-level second feature mining processing on the chip layout optimization vectors to obtain optimized chip layout vectors at multiple levels. The optimized chip layout vectors are used to reflect the feature information of the integrated chip to be optimized in the two dimensions of chip model data and chip layout optimization data. The optimized chip layout vectors at the multiple levels are subjected to feature restoration processing to form chip model optimization data that integrates the chip layout feature information of the integrated chip to be optimized and the layout optimization data of the chip layout optimization data. The chip model optimization data is used to reflect the layout of the integrated chip after optimization. The chip model optimization data is obtained by mapping the optimized chip layout vector of the last level among the optimized chip layout vectors at the multiple levels to the original data space through a decoding neural network. The step of performing multi-level first feature mining processing on the chip layout vector and outputting the deep chip layout vector of the integrated chip to be optimized at multiple levels as reflected in the chip model data includes: using multiple intermediate feature output units in the deep feature mining model formed after optimization operations to perform multi-level first feature mining processing on the chip layout vector and outputting the deep chip layout vector of the integrated chip to be optimized at multiple levels as reflected in the chip model data; wherein, for the first feature mining processing of the chip layout vector at the first level, the first intermediate feature output unit among the multiple intermediate feature output units is used to perform the first feature mining processing of the chip layout vector at the first level, and outputting the deep chip layout vector of the integrated chip to be optimized at the first level as reflected in the chip model data; and, for the first feature mining processing of the chip layout vector at the a-th level, the a-th intermediate feature output unit among the multiple intermediate feature output units is used to perform the first feature mining processing of the deep chip layout vector at the b-th level at the a-th level, and outputting the deep chip layout vector of the integrated chip to be optimized at the a-th level as reflected in the chip model data, where ab=1, and a is greater than 1 and b is greater than or equal to 1; The intermediate feature output unit is a first gradient optimization unit, which includes gradient optimization relationships. The step of using multiple intermediate feature output units in the deep feature mining model formed through optimization operations to perform multi-level first feature mining processing on the chip layout vector, and outputting the deep chip layout vector of the integrated chip to be optimized at multiple levels as reflected in the chip model data, includes: using the gradient optimization relationships in each of the multiple intermediate feature output units to perform relation mapping processing on the chip layout vector to achieve multi-level first feature mining processing, thereby outputting the deep chip layout vector of the integrated chip to be optimized at multiple levels as reflected in the chip model data; wherein each first gradient optimization unit includes multiple convolutional sub-units, and for any first gradient optimization unit, after the input vector of the first gradient optimization unit undergoes convolution processing by the multiple convolutional sub-units, the resulting convolutional vector is aggregated with the input vector, and the result of the vector aggregation processing is used as the output vector of the first gradient optimization unit; The step of combining the deep chip layout vectors at multiple levels and performing multi-level second feature mining processing on the chip layout optimization vector to obtain optimized chip layout vectors at multiple levels includes: using an optimized feature mining model formed by optimization operations, combining the deep chip layout vectors at multiple levels, and performing multi-level second feature mining processing on the chip layout optimization vector to obtain optimized chip layout vectors at multiple levels; wherein the optimized feature mining model includes multiple cascaded second gradient optimization units, and for every two adjacent second gradient optimization units, a focused feature mining unit is configured between the two second gradient optimization units, so that the output vector of the previous second gradient optimization unit is processed by the focused feature mining unit and then output to the next second gradient optimization unit for corresponding processing, and the number of second gradient optimization units is the same as the number of first gradient optimization units in the deep feature mining model.
[0019] Taking a negative feedback amplifier circuit with a small-signal input signal as an example, the optimization focuses on two conflicting circuit performance indicators: low-frequency gain and output bandwidth. The maximum variation of group delay, another circuit performance indicator, is used as a constraint. In this amplifier circuit, the total number of variable-parameter components is 82. Specifically, 45 resistors have a variable range of 85 ohms to 115 ohms, 29 capacitors have a variable range of 12.75 volts to 17.25 volts, and 8 inductors have a variable range of 382.5 picohens to 517.5 picohens. The parameter variation accuracy of each component is 0.01.
[0020] The process of determining the variable parameter components is as follows: Remove the binding wires and photodiode models with unchangeable parameters from the negative feedback amplifier circuit to be optimized; remove the equivalent parasitic resistance with unchangeable parameters; determine the remaining variable parameter transistors, the components contained within the transistors, and the variable parameter components outside the transistors in the remaining integrated circuit. In this negative feedback amplifier circuit to be optimized, all transistors have changeable parameters; all resistors and capacitors within the transistors have changeable parameters; and all components outside the transistors except for the equivalent parasitic resistance have changeable parameters. After the above steps, a total of 82 variable parameter components are determined, including 45 resistors, 29 capacitors, and 8 inductors.
[0021] The process of determining the variable range of component parameters is as follows: without changing the circuit structure, considering the current selection problem and physical constraints, determine the range within which the variable component parameters can fluctuate around the initial value. In this negative feedback amplifier circuit to be optimized, without changing the current flow direction within the transistor, and considering that no short circuits or short circuit phenomena will occur elsewhere in the circuit, the final determination is that the variation range of all variable component parameters is 15% above and below the initial value.
[0022] The initial decision variables are set to the initial component parameters of the large-scale integrated circuit to be optimized. The range of variation of the decision variables is set to the variable range of the component parameters. A large-scale evolutionary algorithm is used to perform the first iteration of the initial decision variables to obtain a new set of decision variable values. The new decision variable values are then used as the circuit component parameters for actual simulation to obtain the corresponding circuit performance indicators, i.e., the optimization target values.
[0023] To ensure the rigor and superiority of the results, during the evolutionary process, every 5 iterations, the decision variables representing the circuit component parameters and the optimization objective of that iteration are again fed into the differential grouping module. The differential grouping module dynamically updates the grouping of the decision variables for each component parameter. For example, after the first iteration, the differential grouping information between the iterated population and the initial population can be input into the differential grouping module for the first grouping. After iterating 5 times using the results of the first grouping, the 6th generation population is obtained. The differential information between the 6th generation population and the 5th generation population is input into the differential grouping module to obtain the second grouping information. When the 6th generation population iterates to the 7th generation population, the second grouping is used.
[0024] The multi-chip integrated layout design method provided in this embodiment first determines chip model data and chip layout optimization data; second, it performs feature extraction processing on the chip model data and chip layout optimization data respectively, outputting chip layout vectors and chip layout optimization vectors; then, it performs multi-level first feature mining processing on the chip layout vectors, outputting deep chip layout vectors at multiple levels; further, it combines the deep chip layout vectors at multiple levels and performs multi-level second feature mining processing on the chip layout optimization vectors to obtain optimized chip layout vectors at multiple levels; finally, it performs feature restoration processing on the optimized chip layout vectors at multiple levels to form chip model optimization data. Based on the above, by combining deep chip layout vectors at multiple levels to perform multi-level second feature mining processing on the chip layout optimization vectors, the resulting multi-level optimized chip layout vectors can reflect the feature information of the integrated chip to be optimized in both chip model data and chip layout optimization data dimensions. In other words, it can represent both the original chip layout features and the features of the performance issues that need to be optimized, making the basis for feature restoration processing of the optimized chip layout vectors more reliable and sufficient. Therefore, the restored chip model optimization data can achieve performance optimization while ensuring matching with the original chip layout features. Moreover, no manual iteration is required during the optimization process, which can improve the problems of low efficiency and high cost in existing multi-chip integrated layout design. That is, it has the advantages of reliability, efficiency and cost in scheme optimization.
[0025] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.
Claims
1. A body-side integrated chip module design system based on multi-scale feature embedding and fusion, characterized in that, include: The chip data acquisition module acquires information about the chip's electronic components, determines suitable electronic components and circuit topology based on requirements to achieve the specific functions required by the chip, and identifies two or more indicators of the chip as optimization targets. The chip module design module selects an encoding method to encode the circuit component parameters, representing N individuals in the evolutionary algorithm as decision variables; initializes N individuals to represent different circuit component parameters; evaluates the fitness of the initialized N individuals; obtains the results of the target circuit performance of the N individuals using intelligent simulation tools; and performs the offspring generation operator operation in the evolutionary algorithm on the N individuals to obtain N offspring, and represents the component parameters of the N offspring. The fitness of N offspring is evaluated based on iterative selection. If the number of evolutionary iterations is odd, the fitness is evaluated using a realistic intelligent simulation tool. If the number of evolutionary iterations is even, the fitness is evaluated using an ensemble surrogate model. The chip creation module is responsible for creating and updating the optimal file. It establishes an optimal individual file to store N optimal individuals. In the initial state, the file contains some or all of the N individuals. Then, it updates the optimal individuals in the current file based on multi-model random sorting and Pareto dominance.
2. The body-side integrated chip module design system based on multi-scale feature embedding and fusion as described in claim 1, characterized in that, The chip data acquisition module first determines the defective chip layout information and the target chip layout scheme. The defective chip layout information includes multiple defective chip layout schemes under multiple chip layout defect types and defective chip layout description vectors corresponding to the multiple defective chip layout schemes. Each defective chip layout scheme corresponds to a defective chip layout description vector. The defective chip layout information and the target chip layout scheme are used to describe the layout status of the corresponding multilayer interconnect chips.
3. The body-side integrated chip module design system based on multi-scale feature embedding and fusion as described in claim 2, characterized in that, The defective chip layout scheme refers to a scheme with defective problems, which belong to the corresponding chip layout defect types. The chip layout defect types include at least electromagnetic isolation defects and heat dissipation defects. The electromagnetic isolation defect refers to electromagnetic interference between multilayer stacked wirings. The defective chip layout scheme also has a corresponding optimized chip layout scheme. The optimized chip layout scheme refers to the scheme formed after optimizing the defects in the defective chip layout scheme. The target chip layout scheme is a scheme with defects that needs to be optimized.
4. The body-side integrated chip module design system based on multi-scale feature embedding and fusion as described in claim 3, characterized in that, The target chip layout scheme is vectorized to output the target chip layout description vector corresponding to the target chip layout scheme.
5. The body-side integrated chip module design system based on multi-scale feature embedding and fusion as described in claim 1, characterized in that, The chip module design module performs knowledge graph determination processing based on the target chip layout description vector and the defective chip layout description vectors corresponding to the multiple defective chip layout schemes, and outputs the corresponding chip layout scheme graph. The chip scheme members in the chip layout scheme graph include a first chip scheme member and multiple second chip scheme members. The first chip scheme member corresponds to the target chip layout scheme, and each second chip scheme member corresponds to a defective chip layout scheme.
6. The body-side integrated chip module design system based on multi-scale feature embedding and fusion as described in claim 1, characterized in that, The chip creation module combines the deep chip layout vectors at multiple levels and performs multi-level second feature mining processing on the chip layout optimization vectors to obtain optimized chip layout vectors at multiple levels. The optimized chip layout vectors are used to reflect the feature information of the integrated chip to be optimized in the two dimensions of chip model data and chip layout optimization data.