Audio power amplifier circuit and audio power amplifier chip

Abstract

The invention provides an audio power amplifier circuit and an audio power amplifier chip, the audio power amplifier circuit comprises a PWM circuit, a duty ratio adjusting circuit and a driving circuit, the PWM circuit modulates a target audio signal into a PWM input signal based on a modulation signal, the duty ratio adjusting circuit generates a clock signal synchronized with the modulation signal, and the driving circuit drives the PWM input signal to rotate. The PWM input signal is used for receiving a clock signal and generating pulses between two adjacent edges based on the number of clock edges of the clock signal between the two adjacent edges of the PWM input signal so as to adjust the duty ratio of the PWM input signal and obtain a PWM output signal, and the driving circuit determines a driving output signal based on the PWM output signal and generates a pulse when the PWM output signal is at a first level. And charging a bootstrap capacitor in the driving circuit. According to the circuit, when a PWM input signal is maintained at a fixed level for a long time, a pulse signal can be inserted into the fixed level so as to charge the bootstrap capacitor, and the driving circuit can maintain stable high level output for a long time, so that the stability and reliability of the circuit are improved.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more particularly to audio power amplifier circuits and audio power amplifier chips. Background Technology

[0002] Existing audio power amplifier circuits typically consist of integrators, comparators, driver circuits, and gain modules. Among these, the driver circuit, as a critical component for output power, directly affects the efficiency and stability of the power amplifier. In the driver stage design of a dual N-type power transistor architecture, a bootstrap capacitor is connected in parallel between the gate and source of the upper power transistor to maintain a certain gate-source voltage Vgs when the upper power transistor needs to be turned on, thereby ensuring that the upper power transistor is fully turned on.

[0003] However, in the existing dual N-type power transistor architecture, when the upper power transistor is turned on for a long time, the charge stored on the bootstrap capacitor will gradually leak, causing the gate-source voltage Vgs of the upper power transistor to drop. Once the gate-source voltage Vgs of the upper power transistor is lower than its threshold voltage, the upper power transistor cannot maintain the on state, causing the driver stage to be unable to maintain a stable high-level output, affecting the reliability and stability of the circuit. Summary of the Invention

[0004] This disclosure provides an audio power amplifier circuit and an audio power amplifier chip, enabling the driving circuit to maintain a stable high-level output for a long time, thereby improving the reliability and stability of the circuit.

[0005] In a first aspect, this disclosure provides an audio power amplifier circuit, including a PWM circuit, a duty cycle adjustment circuit, and a drive circuit connected in sequence. The drive circuit includes an upper power transistor and a bootstrap capacitor connected between the gate and source of the upper power transistor. The drain of the upper power transistor is connected to the power supply voltage, and the source of the upper power transistor is connected to the output terminal of the drive circuit.

[0006] The PWM circuit is configured to receive a target audio signal and a modulation signal, and modulate the target audio signal into a PWM input signal based on the modulation signal; the duty cycle adjustment circuit is configured to generate a clock signal synchronized with the modulation signal, and generate pulses between two adjacent edges based on the number of clock edges between two adjacent edges of the PWM input signal to adjust the duty cycle of the PWM input signal to obtain a PWM output signal; the drive circuit is configured to determine a drive output signal based on the PWM output signal, and charge the bootstrap capacitor in the drive circuit when the PWM output signal is at a first level.

[0007] In some embodiments of this disclosure, the duty cycle adjustment circuit includes an edge detection circuit and a signal modulation circuit. The input terminal of the edge detection circuit is connected to the clock signal, the output terminal of the edge detection circuit is connected to the first input terminal of the signal modulation circuit, the second input terminal of the signal modulation circuit is connected to the output terminal of the PWM circuit, and the output terminal of the signal modulation circuit is connected to the input terminal of the drive circuit.

[0008] The edge detection circuit is configured to delay the clock signal to obtain a clock delay signal, determine an edge detection signal based on the clock delay signal and the clock signal, and extract a signal corresponding to a first target edge of the clock signal from the edge detection signal to obtain a first target edge detection signal.

[0009] The signal modulation circuit is configured to insert a corresponding first target edge detection signal between the first target edge and its next second target edge in the PWM input signal to obtain a first PWM output signal, wherein one of the rising edge and the falling edge is the first target edge and the other is the second target edge.

[0010] In some embodiments of this disclosure, the two output terminals of the edge detection circuit are connected one-to-one with the two first input terminals of the signal modulation circuit.

[0011] The edge detection circuit is further configured to extract a signal corresponding to the second target edge of the clock signal from the edge detection signal to obtain a second target edge detection signal.

[0012] The signal modulation circuit is further configured to insert a corresponding second target edge detection signal between the second target edge and its next first target edge in the first PWM output signal to obtain a second PWM output signal.

[0013] In some embodiments of this disclosure, the edge detection circuit includes a first inverter, a second inverter, a delay, an XOR gate, and a first NAND gate. The clock signal is connected to the input of the second inverter through the first inverter. The output of the second inverter is connected to the input of the delay, the first input of the XOR gate, and the first input of the first NAND gate. The output of the delay is connected to the second input of the XOR gate. The output of the XOR gate is connected to the second input of the first NAND gate. The output of the first NAND gate is connected to the first input of the signal modulation circuit.

[0014] In some embodiments of this disclosure, the edge detection circuit includes a first inverter, a second inverter, a third inverter, a delay, an XOR gate, a first NAND gate, and a second NAND gate. The clock signal is connected to the input terminal of the second inverter and the first input terminal of the second NAND gate through the first inverter. The output terminal of the second inverter is connected to the input terminal of the delay, the first input terminal of the XOR gate, and the first input terminal of the first NAND gate. The output terminal of the delay is connected to the second input terminal of the XOR gate. The output terminal of the XOR gate is connected to the second input terminal of the first NAND gate and the second input terminal of the second NAND gate. The output terminal of the second NAND gate is connected to the input terminal of the third inverter. The two first input terminals of the signal modulation circuit are respectively connected to the output terminal of the first NAND gate and the output terminal of the third inverter.

[0015] In some embodiments of this disclosure, the signal modulation circuit includes a first AND gate and a second AND gate; the first input terminal of the first AND gate is connected to the non-inverting output terminal of the PWM circuit, the first input terminal of the second AND gate is connected to the inverting output terminal of the PWM circuit, the second input terminals of the first AND gate and the second input terminal of the second AND gate are connected to the output terminal of the edge detection circuit, the output terminal of the first AND gate is connected to the non-inverting input terminal of the driving circuit, and the output terminal of the second AND gate is connected to the inverting input terminal of the driving circuit.

[0016] In some embodiments of this disclosure, the signal modulation circuit includes a first AND gate, a second AND gate, a first OR gate, and a second OR gate; the first input terminal of the first AND gate is connected to the non-inverting output terminal of the PWM circuit, the first input terminal of the second AND gate is connected to the inverting output terminal of the PWM circuit, the second input terminals of the first AND gate and the second input terminal of the second AND gate are connected to the first output terminal of the edge detection circuit, the output terminal of the first AND gate is connected to the first input terminal of the first OR gate, the output terminal of the second AND gate is connected to the first input terminal of the second OR gate, and the second input terminals of the first OR gate and the second input terminal of the second OR gate are connected to the second output terminal of the edge detection circuit.

[0017] In some embodiments of this disclosure, the driving circuit includes a first driving transistor, a second driving transistor, and a bootstrap capacitor. The first driving transistor and the second driving transistor are N-type metal-oxide-semiconductor field-effect transistors (NMOS). The drain of the first driving transistor is connected to the power supply voltage, the source of the first driving transistor is connected to the drain of the second driving transistor, the first plate of the bootstrap capacitor, and the output terminal of the driving circuit, the source of the second driving transistor is grounded, and the second plate of the bootstrap capacitor is connected to the gate of the first driving transistor. The first driving transistor and the second driving transistor are controlled by the PWM output signal. When the PWM output signal is at a first level, the first driving transistor is turned off and the second driving transistor is turned on, and the bootstrap capacitor is charged. When the PWM output signal is at a second level, the first driving transistor is turned on and the second driving transistor is turned off, and the bootstrap capacitor is discharged.

[0018] In some embodiments of this disclosure, the audio power amplifier circuit further includes a filter circuit connected to the input terminal of the PWM circuit; the filter circuit is configured to receive an audio input signal, adjust the common-mode voltage of the audio input signal, and amplify the audio input signal to obtain the target audio signal.

[0019] Secondly, this disclosure provides an audio power amplifier chip, including any of the audio power amplifier circuits provided in the first aspect.

[0020] The technical solution disclosed herein provides an audio power amplifier circuit, including a PWM circuit, a duty cycle adjustment circuit, and a drive circuit. The PWM circuit can receive a target audio signal and a modulation signal, and modulate the target audio signal into a PWM input signal based on the modulation signal. The duty cycle adjustment circuit can generate a clock signal synchronized with the modulation signal, and generate pulses between two adjacent edges based on the number of clock edges between two adjacent edges of the clock signal to adjust the duty cycle of the PWM input signal and obtain a PWM output signal. The drive circuit can determine the drive output signal based on the PWM output signal, and charge the bootstrap capacitor in the drive circuit when the PWM output signal is at a first level. In this way, when the PWM input signal is maintained at a fixed level for a long time, a pulse signal can be inserted into the fixed level to charge the bootstrap capacitor, keep the upper power transistor on, and enable the drive circuit to maintain a stable high-level output for a long time, thereby improving the stability and reliability of the circuit. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein: Figure 1 This is a schematic diagram of the structure of an audio power amplifier circuit according to an embodiment of the present disclosure.

[0022] Figure 2 This is a circuit diagram of a driving circuit provided in an embodiment of the present disclosure.

[0023] Figure 3 This is a circuit diagram of a PWM circuit provided in an embodiment of the present disclosure.

[0024] Figure 4 This is a circuit diagram of a duty cycle adjustment circuit provided in an embodiment of the present disclosure.

[0025] Figure 5 A signal schematic diagram of another duty cycle adjustment circuit provided in an embodiment of this disclosure.

[0026] Figure 6 This is a timing diagram of a duty cycle adjustment circuit provided in an embodiment of the present disclosure.

[0027] Figure 7 The following is a timing diagram of another duty cycle adjustment circuit provided in an embodiment of this disclosure.

[0028] Figure 8 This is a circuit diagram of another duty cycle adjustment circuit provided in an embodiment of the present disclosure.

[0029] Figure 9 This is a timing diagram of another duty cycle adjustment circuit provided in an embodiment of the present disclosure.

[0030] Figure 10 This is a schematic diagram of another audio power amplifier circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement “connecting” two or more parts together shall mean that the parts are joined directly together or joined through one or more intermediate components.

[0033] In this disclosure, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure can be combined with other embodiments.

[0034] Furthermore, the terms "first," "second," etc., in the specification, claims, or the accompanying drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0035] In this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three possibilities: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0036] In the description of this disclosure, unless otherwise stated, "multiple" and "at least two" mean two or more (including two), and similarly, "multiple groups" and "at least two groups" mean two or more (including two groups).

[0037] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0038] Figure 1 This is a schematic diagram of the structure of an audio power amplifier circuit according to an embodiment of the present disclosure, as shown below. Figure 1 As shown, the audio power amplifier circuit 100 includes a pulse width modulation (PWM) circuit 110, a duty cycle adjustment circuit 120, and a drive circuit 130.

[0039] In this circuit, the modulation signal input terminal of the PWM circuit 110 is connected to the modulation signal Vramp, the audio signal input terminal of the PWM circuit 110 is connected to the target audio signal (positive target audio signal VP and negative target audio signal VN), the output terminal of the PWM circuit 110 is connected to the input terminal of the duty cycle adjustment circuit 120 to output PWM input signals (positive PWM input signal PWMP_I and negative PWM input signal PWMN_I), and the output terminal of the duty cycle adjustment circuit 120 is connected to the input terminal of the drive circuit 130 to output PWM output signals (positive PWM output signal PWMP_O and negative PWM output signal PWMN_O).

[0040] Figure 2 This is a schematic diagram of the structure of a driving circuit according to an embodiment of the present disclosure, such as... Figure 2 As shown, the driving circuit 130 includes a first upper-side power transistor HS1, a first bootstrap capacitor Cboot1, a second upper-side power transistor HS2, and a second bootstrap capacitor Cboot2. The first bootstrap capacitor Cboot1 is connected between the gate and source of the first upper-side power transistor HS1, and the second bootstrap capacitor Cboot2 is connected between the gate and source of the second upper-side power transistor HS2. The drain of the first upper-side power transistor HS1 and the drain of the second upper-side power transistor HS2 are connected to the power supply voltage VDD. The source of the first upper-side power transistor HS1 is connected to the non-inverting output terminal of the driving circuit 130, and the source of the second upper-side power transistor HS2 is connected to the inverting output terminal of the driving circuit 130.

[0041] The PWM circuit 110 is configured to receive a positive-phase target audio signal VP, an inverted target audio signal VN, and a modulation signal Vramp, and based on the modulation signal Vramp, modulate the positive-phase target audio signal VP into a positive-phase PWM input signal PWMP_I and the inverted target audio signal VN into an inverted-phase PWM input signal PWMN_I.

[0042] The duty cycle adjustment circuit 120 is configured to generate a clock signal CLK synchronized with the modulation signal Vramp, generate pulses between two adjacent edges based on the number of clock edges between two adjacent edges of the clock signal CLK in the positive PWM input signal PWMP_I, thereby adjusting the duty cycle of the positive PWM input signal PWMP_I to obtain the positive PWM output signal PWMP_O, and generate pulses between two adjacent edges based on the number of clock edges between two adjacent edges of the clock signal CLK in the inverted PWM input signal PWMP_I, thereby adjusting the duty cycle of the inverted PWM input signal PWMP_I to obtain the inverted PWM output signal PWMP_O.

[0043] The drive circuit 130 is configured to determine the positive drive output signal VOP based on the positive PWM output signal PWMP_O, and charge the first bootstrap capacitor Cboot1 when the positive PWM output signal PWMP_O is at the first level; and to determine the inverted drive output signal VON based on the inverted PWM output signal PWMN_O, and charge the second bootstrap capacitor Cboot2 when the inverted PWM output signal PWMN_O is at the first level.

[0044] For example, Figure 3 This is a circuit diagram of a PWM circuit provided in an embodiment of the present disclosure, as shown below. Figure 3 As shown, the PWM circuit 110 includes a positive comparator CMPP and an inverting comparator CMPN. The first input terminal of the positive comparator CMPP and the first input terminal of the inverting comparator CMPN are connected to the modulation signal Vramp. The second input terminal of the positive comparator CMPP is connected to the positive target audio signal VP, and the second input terminal of the inverting comparator CMPN is connected to the inverting target audio signal VN.

[0045] The output of the positive comparator CMPP is connected to the positive input of the duty cycle adjustment circuit 120 to output the positive PWM input signal PWMP_I, and the output of the negative comparator CMPN is connected to the negative input of the duty cycle adjustment circuit 120 to output the negative PWM input signal PWMN_I.

[0046] Among them, the modulation signal Vramp can be a triangular wave signal or a sawtooth wave signal, the positive phase target audio signal VP and the negative phase target audio signal VN are analog signals, and the positive phase PWM input signal PWMP_I and the negative phase PWM input signal PWMN_I are digital signals.

[0047] The first input of a comparator can be a non-inverting input, and the corresponding second input is an inverting input, such as... Figure 3 As shown, the positive input signal of the positive comparator CMPP is the modulation signal Vramp, and the inverting input signal of the positive comparator CMPP is the positive target audio signal VP. The positive comparator CMPP can output a high level when the modulation signal Vramp is greater than the positive target audio signal VP, and output a low level when the modulation signal Vramp is less than the positive target audio signal VP, so as to obtain the positive PWM input signal PWMP_I.

[0048] The non-inverting input signal of the inverting comparator CMPN is the modulation signal Vramp, and the inverting input signal of the inverting comparator CMPN is the inverted target audio signal VN. The inverting comparator CMPN can output a high level when the modulation signal Vramp is greater than the inverted target audio signal VN, and output a low level when the modulation signal Vramp is less than the inverted target audio signal VN, so as to obtain the inverted PWM input signal PWMN_I.

[0049] Alternatively, the first input terminal of the comparator can be an inverting input terminal, and the corresponding first input terminal of the comparator can be a non-inverting input terminal. In this case, the inverting input signal of the non-inverting comparator CMPP is the modulation signal Vramp, and the non-inverting input signal of the non-inverting comparator CMPP is the non-inverting target audio signal VP. The non-inverting comparator CMPP can output a low level when the modulation signal Vramp is greater than the non-inverting target audio signal VP, and output a high level when the modulation signal Vramp is less than the non-inverting target audio signal VP, so as to obtain the non-inverting PWM input signal PWMP_I.

[0050] The inverting input signal of the inverting comparator CMPN is the modulation signal Vramp, and the non-inverting input signal of the inverting comparator CMPN is the inverted target audio signal VN. The inverting comparator CMPN can output a low level when the modulation signal Vramp is greater than the inverted target audio signal VN, and output a high level when the modulation signal Vramp is less than the inverted target audio signal VN, so as to obtain the inverted PWM input signal PWMN_I.

[0051] Thus, the PWM circuit 110 compares the positive-phase target audio signal VP and the negative-phase target audio signal VN with the modulation signal Vramp respectively, and performs analog-to-digital conversion on the positive-phase target audio signal VP and the negative-phase target audio signal VN respectively to obtain the positive-phase PWM input signal PWMP_I and the negative-phase PWM input signal PWMN_I.

[0052] Figure 4 This is a circuit diagram of a duty cycle adjustment circuit provided in an embodiment of the present disclosure. Figure 5 A circuit diagram of another duty cycle adjustment circuit provided in this disclosure embodiment is shown below. Figure 4 and Figure 5 As shown, the duty cycle adjustment circuit 120 includes an edge detection circuit 121 and a signal modulation circuit 122. The input terminal of the edge detection circuit 121 is connected to the clock signal CLK, the output terminal of the edge detection circuit 121 is connected to the first input terminal of the signal modulation circuit 122, the second input terminal of the signal modulation circuit 122 is connected to the output terminal of the PWM circuit 110, and the output terminal of the signal modulation circuit 122 is connected to the input terminal of the drive circuit 130.

[0053] The edge detection circuit 121 can delay the clock signal CLK to obtain the clock delay signal CLK_DLY. Based on the clock delay signal CLK_DLY and the clock signal CLK, the edge detection signal CLK_edge is determined. The signal corresponding to the first target edge of the clock signal CLK is extracted from the edge detection signal CLK_edge to obtain the first target edge detection signal.

[0054] The signal modulation circuit 122 can insert a corresponding first target edge detection signal between the first target edge and the next second target edge in the positive PWM input signal PWMP_I to obtain a first positive PWM output signal PWMP1_O, and insert a corresponding first target edge detection signal between the first target edge and the next second target edge in the inverted PWM input signal PWMN_I to obtain a first inverted PWM output signal PWMN1_O. Here, one of the rising edge and the falling edge is the first target edge, and the other is the second target edge.

[0055] For example, such as Figure 4 As shown, the edge detection circuit 121 includes a first inverter INV1, a second inverter INV2, a delay unit DELAY, an XOR gate, and a first NAND gate NAND1. The clock signal CLK is connected to the input of the second inverter INV2 via the first inverter INV1. The output of the second inverter INV2 is connected to the input of the delay unit DELAY, the first input of the XOR gate, and the first input of the first NAND gate NAND1. The output of the delay unit DELAY is connected to the second input of the XOR gate, the output of the XOR gate is connected to the second input of the first NAND gate NAND1, and the output of the first NAND gate NAND1 is connected to the first input of the signal modulation circuit 122.

[0056] The first inverter INV1 outputs an inverted clock signal CLK_TRI. The delay unit DELAY delays the clock signal CLK to obtain a delayed clock signal CLK_DLY. The XOR gate XORs the delayed clock signal CLK_DLY and the clock signal CLK to obtain an edge detection signal CLK_edge. Clearly, the edge detection signal CLK_edge includes both the rising and falling edge information of the clock signal CLK. The first NAND gate NAND1 performs a bitwise AND operation on the edge detection signal CLK_edge and the clock signal CLK to extract the rising edge information of the clock signal CLK from the edge detection signal CLK_edge, obtaining the rising edge detection signal High_edge.

[0057] Figure 6 A timing diagram of a duty cycle adjustment circuit provided in an embodiment of this disclosure is shown below. Figure 6As shown, when the clock signal CLK flips, the clock delay signal CLK_DLY flips at the delay time after the clock signal CLK flips, and the edge detection signal CLK_edge is high during the delay time; when the clock signal CLK does not flip, the edge detection signal CLK_edge is low.

[0058] The rising edge detection signal High_edge is low during the delay period when the clock signal CLK toggles to a high level, high during the delay period when the clock signal CLK toggles to a high level, and high when the clock signal CLK does not toggle. Compared to the period of the clock signal CLK, the delay time is relatively short; therefore, the rising edge detection signal High_edge can be understood as a negative pulse signal.

[0059] See also Figure 4 The signal modulation circuit 122 includes a first AND gate AND1 and a second AND gate AND2. The first input terminal of the first AND gate AND1 is connected to the non-inverting output terminal of the PWM circuit 110, and the first input terminal of the second AND gate AND2 is connected to the inverting output terminal of the PWM circuit 110. The second input terminals of the first AND gate AND1 and the second input terminals of the second AND gate AND2 are connected to the output terminal of the edge detection circuit 121. The output terminal of the first AND gate AND1 is connected to the non-inverting input terminal of the drive circuit 130, and the output terminal of the second AND gate AND2 is connected to the inverting input terminal of the drive circuit 130.

[0060] Between the rising edge and the next falling edge of the positive PWM input signal PWMP_I, PWMP_I is at a high level. When the rising edge detection signal High_edge is high, the first positive PWM output signal PWMP1_O output from the first AND gate AND1 is at a high level. When the rising edge detection signal High_edge is low, the first positive PWM output signal PWMP1_O output from the first AND gate AND1 is at a low level. Therefore, a negative pulse signal can be inserted into the high level of the positive PWM input signal PWMP_I for a long time to obtain the first positive PWM output signal PWMP1_O. Figure 6 As shown.

[0061] Between the rising edge and the next falling edge of the inverted PWM input signal PWMN_I, PWMN_I is at a high level. When the rising edge detection signal High_edge is high, the first inverted PWM output signal PWMN1_O output from the second AND gate AND2 is at a high level. When the rising edge detection signal High_edge is low, the first inverted PWM output signal PWMN1_O output from the second AND gate AND2 is at a low level. Therefore, a negative pulse signal can be inserted into the high level of the inverted PWM input signal PWMN_I for a long time to obtain the first inverted PWM output signal PWMN1_O. Figure 6 As shown.

[0062] Thus, the edge detection circuit 121 can extract the signal corresponding to the rising edge of the clock signal CLK from the edge detection signal CLK_edge to obtain the rising edge detection signal High_edge. The signal modulation circuit 122 can insert a negative pulse signal into the high level when the PWM input signal is kept at a high level for a long time by inserting the corresponding rising edge detection signal High_edge between the rising edge and the next falling edge in the PWM input signal, thereby reducing the duty cycle of the PWM input signal.

[0063] In other implementations, such as Figure 5 As shown, the edge detection circuit 121 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a delay DELAY, an XOR gate, and a NAND gate NAND2. The clock signal CLK is connected to the input of the second inverter INV2 and the first input of the NAND gate NAND2 via the first inverter INV1. The output of the second inverter INV3 is connected to the input of the delay DELAY and the first input of the XOR gate. The output of the delay DELAY is connected to the second input of the XOR gate. The output of the XOR gate is connected to the second input of the NAND gate NAND2. The output of the NAND gate NAND2 is connected to the first input of the signal modulation circuit 122 via the third inverter INV3.

[0064] The second NAND gate (NAND2) works in conjunction with the third inverter (INV3) to perform an AND operation on the edge detection signal CLK_edge and the inverted clock signal CLK_TRI, and then invert the signals to extract the falling edge information of the clock signal CLK from the edge detection signal CLK_edge, thus obtaining the falling edge detection signal Low_edge. Figure 7 As shown, Figure 7 The following is a timing diagram of another duty cycle adjustment circuit provided in an embodiment of this disclosure.

[0065] The falling edge detection signal Low_edge is high during the delay period when the clock signal CLK toggles to a low level, low during the delay period when the clock signal CLK toggles to a high level, and low when the clock signal CLK does not toggle. Therefore, the falling edge detection signal Low_edge can be understood as a positive pulse signal.

[0066] See also Figure 5 The signal modulation circuit 122 includes a first OR gate OR1 and a second OR gate OR2. The first input terminal of the first OR gate OR1 is connected to the non-inverting output terminal of the PWM circuit 110, and the first input terminal of the second OR gate OR2 is connected to the inverting output terminal of the PWM circuit 110. The second input terminals of the first AND gate AND1 and the second AND gate AND2 are connected to the output terminal of the edge detection circuit 121. The output terminal of the first OR gate OR1 is connected to the non-inverting input terminal of the drive circuit 130, and the output terminal of the second OR gate OR2 is connected to the inverting input terminal of the drive circuit 130.

[0067] Between the falling edge and the next rising edge of the positive PWM input signal PWMP_I, PWMP_I is at a low level. When the falling edge detection signal Low_edge is high, the first positive PWM output signal PWMP1_O output by the first OR gate OR1 is high; when the falling edge detection signal Low_edge is low, the first positive PWM output signal PWMP1_O output by the first OR gate OR1 is low. Therefore, a negative pulse signal can be inserted into the low level when the positive PWM input signal PWMP_I remains low for a long time to obtain the first positive PWM output signal PWMP1_O. Figure 7 As shown.

[0068] Between the falling edge and the next rising edge of the inverted PWM input signal PWMN_I, PWMN_I is at a low level. When the falling edge detection signal Low_edge is high, the first inverted PWM output signal PWMN1_O output from the second OR gate OR2 is high. Therefore, when the falling edge detection signal Low_edge is low, the first inverted PWM output signal PWMN1_O output from the second OR gate OR2 is low. Figure 7 As shown.

[0069] Thus, the edge detection circuit 121 can extract the signal corresponding to the falling edge of the clock signal CLK from the edge detection signal CLK_edge to obtain the falling edge detection signal Low_edge. The signal modulation circuit 122 can insert a positive pulse signal into the low level when the PWM input signal is kept at a low level for a long time by inserting the corresponding falling edge detection signal Low_edge between the falling edge and the next rising edge in the PWM input signal, thereby improving the duty cycle of the PWM input signal.

[0070] See also Figure 2 The driving circuit 130 also includes a first lower power transistor LS1 and a second lower power transistor LS2. The first upper power transistor HS1, the second upper power transistor HS2, the first lower power transistor LS1 and the second lower power transistor LS2 are N-type metal-oxide-semiconductor field-effect transistors (NMOS).

[0071] The source of the first upper power transistor HS1 is connected to the drain of the first lower power transistor LS1 and the non-inverting output terminal of the drive circuit 130. The sources of the first lower power transistor LS1 and the second lower power transistor LS2 are grounded. The gate of the first upper power transistor HS1 is connected to the non-inverting upper drive signal, and the gate of the first lower power transistor LS1 is connected to the non-inverting lower drive signal. The source of the second upper power transistor HS2 is connected to the drain of the second lower power transistor LS2 and the inverting output terminal of the drive circuit 130. The gate of the second upper power transistor HS2 is connected to the inverting upper drive signal, and the gate of the second lower power transistor LS2 is connected to the inverting lower drive signal.

[0072] Among them, the first upper power transistor HS1, the first lower power transistor LS1 and the first bootstrap capacitor Cboot1 constitute a driver stage with a dual N-type power transistor architecture, and the second upper power transistor HS2, the second lower power transistor LS2 and the second bootstrap capacitor Cboot2 constitute another driver stage with a dual N-type power transistor architecture.

[0073] The driving circuit 130 can process the first positive-phase PWM output signal PWMP1_O to obtain complementary positive-phase upper-side driving signals and positive-phase lower-side driving signals, and determine the positive-phase drive output signal VOP based on the positive-phase upper-side driving signals and positive-phase lower-side driving signals. The driving circuit 130 can also process the first inverted PWM output signal PWMN1_O to obtain complementary inverted upper-side driving signals and inverted lower-side driving signals, and determine the inverted drive output signal VON based on the inverted upper-side driving signals and inverted lower-side driving signals.

[0074] For example, the first upper power transistor HS_1 is turned on between the first target edge of the positive PWM input signal PWMP_I and its next second target edge, and the second upper power transistor HS_2 is turned on between the first target edge of the inverted PWM input signal PWMN_I and its next second target edge.

[0075] If the first target edge is a rising edge and the second target edge is a falling edge, and the first level is low, then the second level is high.

[0076] At this time, when the first positive phase PWM output signal PWMP1_O is at the second level, the positive phase upper drive signal is at the second level, the positive phase lower drive signal is at the first level, the first upper power transistor HS1 is turned on, the first lower power transistor LS1 is turned off, the first bootstrap capacitor Cboot1 is discharged, and the positive phase drive output signal VOP is at the second level; when the first positive phase PWM output signal PWMP1_O is at the first level, the positive phase upper drive signal is at the first level, the positive phase lower drive signal is at the second level, the first upper power transistor HS1 is turned off, the first lower power transistor LS1 is turned on, the first bootstrap capacitor Cboot1 is charged, and the positive phase drive output signal VOP is at the first level.

[0077] When the first inverted PWM output signal PWMN1_O is at the second level, the inverted upper drive signal is at the second level, the inverted lower drive signal is at the first level, the second upper power transistor HS2 is turned on, the second lower power transistor LS2 is turned off, the second bootstrap capacitor Cboot2 is discharged, and the inverted drive output signal VON is at the second level; when the first inverted PWM output signal PWMN1_O is at the first level, the inverted upper drive signal is at the first level, the inverted lower drive signal is at the second level, the second upper power transistor HS2 is turned off, the second lower power transistor LS2 is turned on, the second bootstrap capacitor Cboot2 is charged, and the inverted drive output signal VON is at the first level.

[0078] If the first target edge is a falling edge and the second target edge is a rising edge, then the first level is high and the second level is low.

[0079] When the first positive phase PWM output signal PWMP1_O is at the second level, the positive phase upper drive signal is at the first level, the positive phase lower drive signal is at the second level, the first upper power transistor HS1 is turned on, the first lower power transistor LS1 is turned off, the first bootstrap capacitor Cboot1 is discharged, and the positive phase drive output signal VOP is at the first level; when the first positive phase PWM output signal PWMP1_O is at the first level, the positive phase upper drive signal is at the second level, the positive phase lower drive signal is at the first level, the first upper power transistor HS1 is turned off, the first lower power transistor LS1 is turned on, the first bootstrap capacitor Cboot1 is charged, and the positive phase drive output signal VOP is at the second level.

[0080] When the first inverted PWM output signal PWMN1_O is at the second level, the inverted upper drive signal is at the first level, the inverted lower drive signal is at the second level, the second upper power transistor HS2 is turned on, the second lower power transistor LS2 is turned off, the second bootstrap capacitor Cboot2 is discharged, and the inverted drive output signal VON is at the first level; when the first inverted PWM output signal PWMN1_O is at the first level, the inverted upper drive signal is at the second level, the inverted lower drive signal is at the first level, the second upper power transistor HS2 is turned off, the second lower power transistor LS2 is turned on, the second bootstrap capacitor Cboot2 is charged, and the inverted drive output signal VON is at the second level.

[0081] In summary, the duty cycle modulation circuit provided in this embodiment can insert pulse signals into the fixed level when the PWM input signal is maintained at a fixed level for a long time, thereby charging the bootstrap capacitor to keep the upper power transistor on, so that the drive circuit can maintain a stable high-level output for a long time, thereby improving the stability and reliability of the circuit.

[0082] In some embodiments, Figure 8 A circuit diagram of another duty cycle adjustment circuit provided in this disclosure embodiment is shown below. Figure 8 As shown, the two output terminals of the edge detection circuit 121 are connected one-to-one with the two first input terminals of the signal modulation circuit 122.

[0083] The edge detection circuit 121 is also configured to extract the signal corresponding to the second target edge of the clock signal CLK from the edge detection signal CLK_edge to obtain the second target edge detection signal.

[0084] The signal modulation circuit 122 is further configured to insert a corresponding second target edge detection signal between the second target edge and the next first target edge in the first positive PWM output signal PWMP1_O to obtain a second positive PWM output signal PWMP2_O; and to insert a corresponding second target edge detection signal between the second target edge and the next first target edge in the first negative PWM output signal PWMN1_O to obtain a second negative PWM output signal PWMP2_O.

[0085] For example, in Figure 3 Based on the illustrated embodiment, the edge detection circuit 121 further includes a second NAND gate NAND2 and a third inverter INV3, and the signal modulation circuit 122 further includes a first OR gate OR1 and a second OR gate OR2, as shown. Figure 8 As shown.

[0086] In this circuit, the first input terminal of the second NAND gate NAND2 is connected to the input terminal of the first inverter INV1, the second input terminal of the second NAND gate NAND2 is connected to the output terminal of the XOR gate, the two first input terminals of the signal modulation circuit 122 are respectively connected to the output terminal of the first NAND gate NAND1 and the output terminal of the third inverter INV3, the first output terminal of the edge detection circuit 121 is the output terminal of the first NAND gate NAND1, and the second output terminal of the edge detection circuit 121 is the output terminal of the third inverter INV3.

[0087] The second input of the first AND gate AND1 and the second input of the second AND gate AND2 are connected to the first output of the edge detection circuit 121. The first input of the first OR gate OR1 is connected to the output of the first AND gate AND1. The first input of the second OR gate OR2 is connected to the output of the second AND gate AND2. The second input of the first OR gate OR1 and the second input of the second OR gate OR2 are connected to the second output of the edge detection circuit 121.

[0088] Edge detection circuit 121 can extract the signals corresponding to the rising edge and falling edge of clock signal CLK from edge detection signal CLK_edge, respectively, to obtain rising edge detection signal High_edge and falling edge detection signal Low_edge, such as... Figure 9 As shown, Figure 9 This is a timing diagram of another duty cycle modulation circuit provided in an embodiment of the present disclosure.

[0089] The signal modulation circuit 122 can insert a negative pulse signal into the high level when the PWM input signal is kept high for a long time by inserting a corresponding rising edge detection signal High_edge between the rising edge and the next falling edge of the PWM input signal, and can insert a positive pulse signal into the low level when the PWM input signal is kept low for a long time by inserting a corresponding falling edge detection signal Low_edge between the falling edge and the next rising edge of the PWM input signal.

[0090] In this way, when the PWM input signal is maintained at a fixed level for a long time, a negative pulse signal can be inserted into the high level and a positive pulse signal can be inserted into the low level, which can adjust the duty cycle of the PWM input signal bidirectionally to adapt to different driving circuits.

[0091] In some embodiments, Figure 10 This is a schematic diagram of another audio power amplifier circuit provided in an embodiment of the present disclosure, as shown below. Figure 10 As shown, in Figure 1 Based on the embodiment shown, the audio power amplifier circuit 100 further includes a filter circuit 140, the output of which is connected to the input of the PWM circuit 110.

[0092] The filter circuit 140 is configured to receive the positive-phase audio input signal VIP and the negative-phase audio input signal VIN, adjust the common-mode voltage of the positive-phase audio input signal VIP and the negative-phase audio input signal VIN, and amplify the positive-phase audio input signal VIP and the negative-phase audio input signal VIN to obtain the positive-phase target audio signal VP and the negative-phase target audio signal VN.

[0093] For example, the common-mode voltage of the positive-phase audio input signal VIP and the negative-phase audio input signal VIN is 0V, while the common-mode voltage required for the positive-phase target audio signal VP and the negative-phase target audio signal VN is a fixed level, such as VDD / 4 or VDD / 2, to match the operating point of the PWM circuit 110 and reduce circuit power consumption. The filter circuit 140 can use an adder circuit composed of an integrator and an operational amplifier, a level shifter circuit, or a biased filter network to modulate the common-mode voltage of the positive-phase audio input signal VIP and the negative-phase audio input signal VIN and amplify the signals for subsequent signal processing.

[0094] In addition, the audio power amplifier circuit 100 may also include a gain control circuit 150, which can dynamically adjust the amplification factor of the positive phase audio input signal VIP and the negative phase audio input signal VIN, as well as the amplitude of the positive phase target audio signal VP and the negative phase target audio signal VN, according to control commands or control signals.

[0095] The embodiments of this disclosure also provide an audio power amplifier chip, including the audio power amplifier circuit 100 of the embodiments of this disclosure.

[0096] The audio amplifier chip provided in this disclosure includes the audio amplifier circuit 100 provided in any of the above embodiments, and has the functional modules and beneficial effects of the audio amplifier circuit 100, which will not be described in detail here.

[0097] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, “example” is merely illustrative and should not be considered exclusive or extensive.

[0098] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. An audio power amplifier circuit, characterized in that, The device includes a pulse width modulation (PWM) circuit, a duty cycle adjustment circuit, and a drive circuit connected in sequence. The drive circuit includes an upper power transistor and a bootstrap capacitor connected between the gate and source of the upper power transistor. The drain of the upper power transistor is connected to the power supply voltage, and the source of the upper power transistor is connected to the output terminal of the drive circuit. The PWM circuit is configured to receive a target audio signal and a modulation signal, and modulate the target audio signal into a PWM input signal based on the modulation signal. The duty cycle adjustment circuit is configured to generate a clock signal synchronized with the modulation signal, and based on the number of clock edges between two adjacent edges of the clock signal, generate pulses between the two adjacent edges to adjust the duty cycle of the PWM input signal to obtain a PWM output signal. The driving circuit is configured to determine a driving output signal based on the PWM output signal, and to charge the bootstrap capacitor when the PWM output signal is at a first level.

2. The audio power amplifier circuit according to claim 1, characterized in that, The duty cycle adjustment circuit includes an edge detection circuit and a signal modulation circuit; The input terminal of the edge detection circuit is connected to the clock signal, the output terminal of the edge detection circuit is connected to the first input terminal of the signal modulation circuit, the second input terminal of the signal modulation circuit is connected to the output terminal of the PWM circuit, and the output terminal of the signal modulation circuit is connected to the input terminal of the drive circuit. The edge detection circuit is configured to delay the clock signal to obtain a clock delay signal, determine an edge detection signal based on the clock delay signal and the clock signal, and extract a signal corresponding to a first target edge of the clock signal from the edge detection signal to obtain a first target edge detection signal. The signal modulation circuit is configured to insert a corresponding first target edge detection signal between the first target edge and its next second target edge in the PWM input signal to obtain a first PWM output signal, wherein one of the rising edge and the falling edge is the first target edge and the other is the second target edge.

3. The audio power amplifier circuit according to claim 2, characterized in that, The two output terminals of the edge detection circuit are connected one-to-one with the two first input terminals of the signal modulation circuit; The edge detection circuit is further configured to extract a signal corresponding to the second target edge of the clock signal from the edge detection signal to obtain the second target edge detection signal; The signal modulation circuit is further configured to insert a corresponding second target edge detection signal between the second target edge and its next first target edge in the first PWM output signal to obtain a second PWM output signal.

4. The audio power amplifier circuit according to claim 2, characterized in that, The edge detection circuit includes a first inverter, a second inverter, a delay, an XOR gate, and a first NAND gate; The clock signal is connected to the input of the second inverter via the first inverter. The output of the second inverter is connected to the input of the delay, the first input of the XOR gate, and the first input of the first NAND gate. The output of the delay is connected to the second input of the XOR gate. The output of the XOR gate is connected to the second input of the first NAND gate. The output of the first NAND gate is connected to the first input of the signal modulation circuit.

5. The audio power amplifier circuit according to claim 3, characterized in that, The edge detection circuit includes a first inverter, a second inverter, a third inverter, a delay, an XOR gate, a first NAND gate, and a second NAND gate; The clock signal is connected to the input of the second inverter and the first input of the second NAND gate via the first inverter. The output of the second inverter is connected to the input of the delay unit, the first input of the XOR gate, and the first input of the first NAND gate. The output of the delay unit is connected to the second input of the XOR gate. The output of the XOR gate is connected to the second input of the first NAND gate and the second input of the second NAND gate. The output of the second NAND gate is connected to the input of the third inverter. The two first inputs of the signal modulation circuit are respectively connected to the output of the first NAND gate and the output of the third inverter.

6. The audio power amplifier circuit according to claim 2, characterized in that, The signal modulation circuit includes a first AND gate and a second AND gate; The first input terminal of the first AND gate is connected to the non-inverting output terminal of the PWM circuit, the first input terminal of the second AND gate is connected to the inverting output terminal of the PWM circuit, the second input terminals of the first AND gate and the second input terminal of the second AND gate are connected to the output terminal of the edge detection circuit, the output terminal of the first AND gate is connected to the non-inverting input terminal of the driving circuit, and the output terminal of the second AND gate is connected to the inverting input terminal of the driving circuit.

7. The audio power amplifier circuit according to claim 3, characterized in that, The signal modulation circuit includes a first AND gate, a second AND gate, a first OR gate, and a second OR gate; The first input terminal of the first AND gate is connected to the non-inverting output terminal of the PWM circuit, the first input terminal of the second AND gate is connected to the inverting output terminal of the PWM circuit, the second input terminals of the first AND gate and the second input terminal of the second AND gate are connected to the first output terminal of the edge detection circuit, the output terminal of the first AND gate is connected to the first input terminal of the first OR gate, the output terminal of the second AND gate is connected to the first input terminal of the second OR gate, and the second input terminals of the first OR gate and the second input terminal of the second OR gate are connected to the second output terminal of the edge detection circuit.

8. The audio power amplifier circuit according to any one of claims 1-7, characterized in that, The driving circuit also includes a lower power transistor, and the upper power transistor and the lower power transistor are N-type metal-oxide-semiconductor field-effect transistors (NMOS). The source of the upper power transistor is connected to the drain of the lower power transistor and the output terminal of the driving circuit. The source of the lower power transistor is grounded. The gate of the upper power transistor is connected to the upper driving signal, and the gate of the lower power transistor is connected to the lower driving signal. The driving circuit is further configured to determine the upper driving signal and the lower driving signal based on the PWM output signal, and to determine the driving output signal based on the upper driving signal and the lower driving signal. Specifically, when the PWM output signal is at the first level, the upper power transistor is turned off and the lower power transistor is turned on, and the drive output signal is at a high level; when the PWM output signal is at the second level, the upper power transistor is turned on and the lower power transistor is turned off, and the drive output signal is at a low level.

9. The audio power amplifier circuit according to any one of claims 1-7, characterized in that, The audio power amplifier circuit also includes a filter circuit connected to the input terminal of the PWM circuit; The filtering circuit is configured to receive an audio input signal, adjust the common-mode voltage of the audio input signal, and amplify the audio input signal to obtain the target audio signal.

10. An audio power amplifier chip, characterized in that, Includes the audio power amplifier circuit according to any one of claims 1-9.

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