On-chip network communication architecture system in noise environment

Abstract

The invention relates to the technical field of digital integrated circuit design, and discloses an on-chip network communication architecture system in a noise environment, which integrates two sets of independent ARQ and HARQ systems optimized aiming at different data bit widths at the same time, utilizes the characteristics of on-chip network wormhole exchange and sequential microchip transmission of a virtual channel, and improves the communication performance of the on-chip network. And a set of sequential storage and address-corresponding unified management strategy is designed. The sending buffer area and the receiving buffer area are consistent in depth and are in one-to-one correspondence in address, so that complex out-of-order management and sorting logic are eliminated fundamentally, the effect of'controlling complexity with simplicity 'is realized, and excellent balance among reliability, performance and hardware overhead can be realized in a network-on-chip in a high-noise environment.

Description

Technical Field

[0001] This application relates to the field of digital integrated circuit design technology, such as an on-chip network communication architecture system in a noisy environment. Background Technology

[0002] With the continuous advancement of digital integrated circuit process nodes, the number of transistors integrated has increased significantly, and multi-core systems-on-chips (SoCs) have become the mainstream design solution due to their energy efficiency and performance advantages. As the core communication architecture of multi-core SoCs, on-chip networks (ONCs) need to meet high-bandwidth communication requirements. However, process advancements have led to a reduction in the width and spacing of on-chip network interconnects, making them susceptible to transient errors caused by crosstalk, power supply noise, and other factors, seriously threatening chip reliability.

[0003] Existing on-chip network fault tolerance technologies mainly include noise reduction and error control technologies. Noise reduction technologies, such as increasing conductor width and inserting shielded wires, increase wiring area, and anti-crosstalk coding cannot resist non-crosstalk noise. Among error control technologies, forward error correction codes (FEC) have insufficient reliability and large redundant bit overhead in high-noise environments, while automatic repeat request (ARQ) leads to bandwidth waste due to frequent retransmissions in high-noise environments. Although hybrid automatic repeat request (HARQ) combines the advantages of FEC and ARQ, existing designs are not optimized for high-noise environments and have problems such as complex buffer management and unclear performance-area trade-offs, making it difficult to meet the comprehensive requirements of on-chip network reliability, high performance, and low area overhead in high-noise environments.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application. Summary of the Invention

[0005] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0006] The on-chip network communication architecture system provided in this disclosure can simplify buffer management logic while ensuring the reliability of on-chip network communication in high-noise environments, and achieve a flexible trade-off between performance and area. It solves the problems of complex buffer management, unclear performance-area trade-off, and difficulty in meeting the requirements of on-chip network reliability, high performance and low area overhead in existing solutions.

[0007] The on-chip network communication architecture system in a noisy environment disclosed herein includes an on-chip network main body and an error control system. The on-chip network itself adopts a wormhole switching router based on virtual channels and a 2D Mesh topology. The error control system includes a parallel ARQ error control system and a HARQ error control system, which are suitable for different data bit widths. Both the ARQ error control system and the HARQ error control system adopt a selective retransmission strategy and operate based on a unified buffer management strategy.

[0008] In some aspects, the buffer management strategy is to store encoded words in the transmit buffer in ascending address order according to the microchip input order, and the receive buffer has the same depth as the transmit buffer and the storage address corresponds one-to-one with the transmit buffer.

[0009] In some aspects, the aforementioned ARQ error control system is suitable for 34-bit data widths, with its transmitting end including a CRC5 encoder and its receiving end including a CRC5 decoder.

[0010] In some respects, the HARQ error control system described above is suitable for 57-bit data widths, and its transmitting end includes a Hamming code encoder and a CRC7 encoder in sequence.

[0011] In some aspects, the receiver of the aforementioned HARQ error control system includes a Hamming code decoder, a first CRC7 decoder / verifier, a second CRC7 decoder / verifier, and a receiver control unit. Among them, the Hamming code decoder is used to correct errors in the received encoded words; The first CRC7 decoder verifier is used to verify the data after error correction by the Hamming code decoder. The second CRC7 decoder verifier is used to verify the original data before the Hamming code decoder corrects errors. The receiving end control unit is configured to execute output data or request retransmission according to predefined decision rules based on the output results of the first CRC7 decoder and the second CRC7 decoder.

[0012] In some respects, the above-predefined decision rules are as follows: If the first CRC7 check result is correct, the check will pass and data will be output regardless of the second CRC7 check result. If both the first and second CRC7 check results are incorrect, the check is deemed to have failed and a retransmission is requested.

[0013] In some respects, the aforementioned unified buffer management strategy is implemented using pointers; The transmitting end control unit maintains three pointers: p_ack, p_tx, and p_tail, which respectively point to the address of the earliest coded word for which no ACK has been received, the address of the coded word to be sent, and the address to be written. The receiver control unit maintains a p_ack pointer, which points to the address of the encoded word to be confirmed.

[0014] In some aspects, the aforementioned virtual channel-based routers adopt a five-stage pipeline structure, including a write buffer stage, a route calculation stage, a virtual channel allocation stage, a cross-connect switch allocation stage, and a cross-connect switch traversal stage.

[0015] In some aspects, the aforementioned route calculation phase employs a negative-first fixed routing algorithm.

[0016] In some aspects, the aforementioned error control system is integrated into the on-chip network body.

[0017] The on-chip network communication architecture system for noisy environments provided in this disclosure can achieve the following technical effects: The on-chip network communication architecture system disclosed herein achieves an excellent balance between reliability, performance, and hardware overhead in on-chip networks operating in high-noise environments. Its core technical benefits include significantly improved communication reliability, optimized system performance and energy efficiency, and effective reduction in hardware complexity and area overhead. While ensuring on-chip network communication reliability in high-noise environments, it simplifies buffer management logic and achieves a flexible trade-off between performance and area.

[0018] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0019] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of an on-chip network communication architecture system in a noisy environment, provided by an embodiment of this disclosure; Figure 2 This is a schematic diagram of a 3×3 scale 2D Mesh topology provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of a five-stage pipeline workflow for a virtual channel router provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of the structure of an on-chip network communication device in a noisy environment, provided in an embodiment of this disclosure. Detailed Implementation

[0020] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0021] The terms "first," "second," etc., used in the embodiments of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0022] Unless otherwise stated, the term "multiple" means two or more.

[0023] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0024] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0025] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0026] The on-chip network communication architecture system in a noisy environment provided by the present disclosure will be described below with reference to the accompanying drawings.

[0027] Figure 1 This is a schematic diagram of an on-chip network communication architecture system in a noisy environment, provided by an embodiment of this disclosure.

[0028] like Figure 1 As shown, the on-chip network communication architecture system in a noisy environment may include an on-chip network main body 101 and an error control system 102; Among them, the on-chip network main body 101 adopts a wormhole switching router based on virtual channel and a 2D Mesh topology; The error control system 102 includes a parallel ARQ error control system 1021 and a HARQ error control system 1022, which are suitable for different data bit widths. Both the ARQ error control system and the HARQ error control system adopt a selective retransmission strategy and operate based on a unified buffer management strategy.

[0029] In some embodiments, the above buffer management strategy is to store encoded words in the transmit buffer in ascending address order according to the microchip input order, and the receive buffer has the same depth as the transmit buffer and the storage address corresponds one-to-one with the transmit buffer.

[0030] In some embodiments, the ARQ error control system described above is suitable for a 34-bit data width, with its transmitting end including a CRC5 encoder and its receiving end including a CRC5 decoder.

[0031] In some embodiments, the HARQ error control system described above is suitable for a 57-bit data width, and its transmitting end includes a Hamming code encoder and a CRC7 encoder in sequence.

[0032] In some embodiments, the receiver of the HARQ error control system described above includes a Hamming code decoder, a first CRC7 decoder and verifier, a second CRC7 decoder and verifier, and a receiver control unit. Among them, the Hamming code decoder is used to correct errors in the received encoded words; The first CRC7 decoder verifier is used to verify the data after error correction by the Hamming code decoder. The second CRC7 decoder verifier is used to verify the original data before the Hamming code decoder corrects errors. The receiving end control unit is configured to execute output data or request retransmission according to predefined decision rules based on the output results of the first CRC7 decoder and the second CRC7 decoder.

[0033] In some embodiments, the predefined decision rule is as follows: If the first CRC7 check result is correct, the check will pass and data will be output regardless of the second CRC7 check result. If both the first and second CRC7 check results are incorrect, the check is deemed to have failed and a retransmission is requested.

[0034] In some embodiments, the unified buffer management strategy described above is implemented using pointers; The transmitting end control unit maintains three pointers: p_ack, p_tx, and p_tail, which respectively point to the address of the earliest coded word for which no ACK has been received, the address of the coded word to be sent, and the address to be written. The receiver control unit maintains a p_ack pointer, which points to the address of the encoded word to be confirmed.

[0035] In some embodiments, the virtual channel-based router described above adopts a five-stage pipeline structure, including a write buffer stage, a route calculation stage, a virtual channel allocation stage, a cross switch allocation stage, and a cross switch traversal stage.

[0036] In some embodiments, the above-described route calculation phase employs a negative-first fixed routing algorithm.

[0037] In some embodiments, the above-described error control system may also be integrated into the on-chip network body.

[0038] Figure 2 This is a schematic diagram of a 3×3 2D Mesh topology provided in an embodiment of this disclosure. Figure 3 This is a schematic diagram of a five-stage pipeline workflow for a virtual channel router provided in this disclosure embodiment, combined with... Figure 2 and Figure 3 ,right Figure 1 The system will be described further in this paper.

[0039] Specifically, the on-chip network communication architecture system for noisy environments provided by this invention can be understood as a reliable on-chip network communication architecture for high-noise environments: The architecture includes the on-chip network core, the error control system, and the error injection simulation verification part; On-screen network main body: such as Figure 2 As shown, the on-chip network adopts a 3×3 2D Mesh topology, consisting of virtual channel routers based on a wormhole-based flow control strategy. Each virtual channel router includes input ports, output ports, input units, a downstream virtual channel allocation module, a downstream switch allocation module, and a crossbar switch. The input unit contains four virtual channels (each containing a FIFO buffer and a virtual channel control module), a route calculation module, a upstream virtual channel allocation module, and a upstream switch allocation module. The route calculation module uses a negative-first fixed routing algorithm, and each allocation module is implemented based on a round-robin arbitration strategy. Error control systems: including ARQ error control system and HARQ error control system; ARQ error control system: suitable for 34-bit data width scenarios, including a transmitter and a receiver; the transmitter includes a CRC5 encoder, a transmitter buffer, a transmitter control unit, and a multiplexer; the receiver includes a CRC5 decoder, a receiver buffer, a receiver control unit, and a multiplexer. HARQ error control system: suitable for 57-bit data width scenarios, including a transmitter and a receiver; the transmitter includes a (63,57) Hamming code encoder, a CRC7 encoder, a transmit buffer, a transmitter control unit and a multiplexer; the receiver includes a (63,57) Hamming code decoder, two CRC7 decoder checkers, a receive buffer, a receiver control unit and a multiplexer. Both ARQ and HARQ error control systems employ selective repeat strategy and are based on a unified buffer management strategy: the transmit buffer stores encoded words in incrementing address according to the microchip input order, the receive buffer has the same depth as the transmit buffer and the storage address corresponds to the transmit buffer, eliminating the need for complex address management and microchip sorting logic.

[0040] In a specific example, the implementation of the on-chip network reliability communication architecture may include a virtual channel router implementation, an ARQ error control system implementation, and a HARQ error control system implementation.

[0041] Virtual channel router implementation: such as Figure 2 As shown, the virtual channel router's workflow adopts a five-stage pipeline design. In the write buffer (BW) stage, the chip is written to the corresponding virtual channel FIFO; in the route calculation (RC) stage, only the head chip is executed, and the output port is determined based on the negative-first algorithm; the virtual channel allocation (VA) and cross switch allocation (SA) stages are arbitrated before and after each stage; in the cross switch traversal (ST) stage, the chip is forwarded according to the allocation result. ARQ error control system implementation: 34-bit microchips are encoded using CRC5 to generate 39-bit encoded words; the transmitting end control unit maintains three pointers: p_ack (the address of the earliest encoded word that has not received an ACK), p_tx (the address of the encoded word to be sent), and p_tail (the address to be written); the receiving end control unit maintains the p_ack pointer and the status register, and outputs the microchip according to the address if the verification is successful. The HARQ error control system is implemented as follows: The 57-bit microchip is encoded with (63,57) Hamming code (adding 6 bits of redundancy) and CRC7 code (adding 7 bits of redundancy) to generate a 70-bit code word; The receiving end first performs error correction by decoding Hamming code, and then verifies the data before and after error correction by two CRC7 checkers respectively, and makes a decision according to Table 1.

[0042] Table 1 HARQ Decoder Verifier Decision Rules

[0043] The on-chip network communication architecture system in noisy environments disclosed in this embodiment achieves an excellent balance between reliability, performance, and hardware overhead in on-chip networks in high-noise environments through a series of collaborative designs. The core technical effects it brings are specifically reflected in: Communication reliability is significantly improved. Dual protection: By integrating ARQ and HARQ systems in parallel, a targeted and robust fault-tolerance mechanism is provided for communication data of different importance and bit width.

[0044] Intelligent error correction: The innovative "dual CRC check and decision mechanism" of the HARQ system can intelligently identify and adopt successfully corrected data, which greatly reduces unnecessary retransmissions triggered by "correctable errors", thus maintaining efficient and reliable data transmission even in harsh channel environments.

[0045] System performance and energy efficiency optimization. Bandwidth and power consumption savings: The aforementioned "intelligent error correction" mechanism directly avoids a large number of redundant retransmission operations, significantly saving network bandwidth and power consumption of the transmission and reception functions.

[0046] Low latency characteristics are preserved: The ARQ path provides a fast channel for latency-sensitive data, while simplified HARQ management reduces processing latency, together ensuring the overall system response speed.

[0047] Hardware complexity and area overhead are effectively reduced. Management logic is simplified: The innovative "unified simplified buffer management strategy" utilizes the inherent ordered transmission characteristics of on-chip networks, eliminating complex out-of-order management and sorting logic. High cost-effectiveness: This design, with a relatively small hardware increment (two optimized systems), solves the problem of the huge area and complexity costs required by traditional solutions to achieve high reliability, achieving high cost-effectiveness.

[0048] In summary, this disclosure integrates two independent systems, ARQ and HARQ, optimized for different data bit widths. Leveraging the characteristics of on-chip network wormhole switching and the in-order transmission of microchips via virtual channels, it designs a unified management strategy based on sequential storage and address mapping. With consistent transmit and receive buffer depths and one-to-one address mapping, complex out-of-order management and sorting logic are fundamentally eliminated, achieving a "simplicity over complexity" effect. This enables an excellent balance between reliability, performance, and hardware overhead in on-chip networks operating in high-noise environments. This disclosure achieves three seemingly contradictory goals simultaneously in high-noise environments: "low data loss" (high reliability), "fast transmission" (high performance), and "low cost" (low overhead). While ensuring the reliability of on-chip network communication in high-noise environments, it simplifies buffer management logic and achieves a flexible trade-off between performance and area. It is suitable for scenarios in multi-core on-chip systems where communication reliability, performance, and area overhead need to be considered.

[0049] Combination Figure 4As shown in the illustration, this disclosure also provides an on-chip network communication device 400 for noisy environments, including a processor 404 and a memory 401. Optionally, the system may further include a communication interface 402 and a bus 403. The processor 404, communication interface 402, and memory 401 can communicate with each other via the bus 403. The communication interface 402 can be used for information transmission. The processor 404 can call logical instructions in the memory 401 to execute the on-chip network communication method for noisy environments corresponding to the system in the above embodiment.

[0050] Furthermore, the logic instructions in the aforementioned memory 401 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0051] The memory 401, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 404 executes functional applications and data processing by running the program instructions / modules stored in the memory 401, thereby realizing the on-chip network communication method under noisy conditions corresponding to the system in the above embodiments.

[0052] The memory 401 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 401 may include high-speed random access memory and may also include non-volatile memory.

[0053] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to execute the on-chip network communication method under noisy conditions corresponding to the system described above.

[0054] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0055] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0056] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. As used in the description of the embodiments, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “(the)” are intended to equally include the plural forms. Similarly, the term “and / or” as used herein means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the terms “comprise” and its variations “comprises” and / or “comprising” refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Unless otherwise specified, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes the element. In this document, each embodiment may focus on describing the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, then the relevant parts can be referred to the description of the method section.

[0057] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0058] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0059] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0060] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0061] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0062] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0063] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0064] The systems and technologies described herein can be implemented in computing systems that include back-end components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0065] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0066] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this disclosure can be achieved, and this is not limited herein.

[0067] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A network-on-chip communication architecture system for noisy environments, characterized in that, The architecture system includes an on-chip network and an error control system; The on-chip network main body adopts a wormhole switching router based on virtual channels and a 2D Mesh topology; The error control system includes a parallel ARQ error control system and a HARQ error control system, which are suitable for different data bit widths. Both the ARQ error control system and the HARQ error control system adopt a selective retransmission strategy and operate based on a unified buffer management strategy.

2. The architecture system according to claim 1, characterized in that, The buffer management strategy is that the transmit buffer stores encoded words in ascending address order according to the microchip input order, and the receive buffer has the same depth as the transmit buffer and the storage address corresponds one-to-one with the transmit buffer.

3. The architecture system according to claim 1, characterized in that, The ARQ error control system is suitable for 34-bit data width, and its transmitting end includes a CRC5 encoder, while the receiving end includes a CRC5 decoder and verifier.

4. The architecture system according to claim 1, characterized in that, The HARQ error control system is suitable for 57-bit data width, and its transmitting end includes a Hamming code encoder and a CRC7 encoder in sequence.

5. The architecture system according to claim 4, characterized in that, The receiver of the HARQ error control system includes a Hamming code decoder, a first CRC7 decoder and verifier, a second CRC7 decoder and verifier, and a receiver control unit. The Hamming code decoder is used to correct errors in the received encoded words. The first CRC7 decoder verifier is used to verify the data after error correction by the Hamming code decoder; The second CRC7 decoder verifier is used to verify the original data before error correction by the Hamming code decoder; The receiving end control unit is configured to execute output data or request retransmission according to predefined decision rules based on the output results of the first CRC7 decoder and the second CRC7 decoder.

6. The architecture system according to claim 5, characterized in that, The predefined decision rule is: When the first CRC7 check result is correct, the check passes and data is output regardless of the second CRC7 check result. If both the first CRC7 check result and the second CRC7 check result are incorrect, the check is deemed to have failed and a retransmission is requested.

7. The architecture system according to claim 1, characterized in that, The unified buffer management strategy is implemented using pointers; The transmitting end control unit maintains three pointers: p_ack, p_tx, and p_tail, which respectively point to the address of the earliest coded word for which no ACK has been received, the address of the coded word to be sent, and the address to be written. The receiver control unit maintains a p_ack pointer, which points to the address of the encoded word to be confirmed.

8. The architecture system according to claim 1, characterized in that, The virtual channel-based router adopts a five-stage pipeline structure, including a write buffer stage, a route calculation stage, a virtual channel allocation stage, a cross switch allocation stage, and a cross switch traversal stage.

9. The architecture system according to claim 8, characterized in that, The route calculation phase employs the negative-first fixed routing algorithm.

10. The architecture system according to claim 1, characterized in that, The error control system is integrated into the on-chip network body.

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