Transferable and low-power-consumption MCU (Microprogrammed Control Unit) device

Abstract

The invention relates to the field of microcontrollers, in particular to the field of industrial control, and specifically relates to an MCU device with portability and low power consumption. The MCU device with portability and low power consumption comprises an instruction architecture, a storage architecture and a pipeline architecture in the aspect of a kernel; an instruction architecture, a storage architecture and a pipeline architecture are simplified; in the aspect of peripherals, design is carried out according to requirements in current industrial scenes, modules such as a UART (Universal Asynchronous Receiver / Transmitter), an SPI (Serial Peripheral Interface) and a TMR0 are modularized, and implementation is carried out based on an SFR bus protocol; a simplified instruction system structure is used, and a PIC16F8X series instruction system is compatible; classifying the instruction into a file register byte-oriented operation type instruction, a file register bit-oriented operation type instruction, an immediate operand operation type instruction and a fixed coding format control type instruction according to different instruction types; in all the operation instructions, the operation code field is located in the highest bit field, and information report instruction types and function information are contained in the operation code field.

Description

Technical Field

[0001] This invention relates to the field of microcontrollers, particularly to the field of industrial control, and specifically to a portable and low-power MCU device. Background Technology

[0002] With technological advancements and societal evolution, society has undergone a profound transformation in recent years, albeit in a surprising way. Human society has experienced tremendous changes, from the initial mechanical and electronic industries to the subsequent electronic information age, and now to the intelligent age. Along with these changes, electronic products have shown increasingly prominent development trends, playing a more crucial role in our daily lives. To a certain extent, electronic products have become an indispensable part of modern life. Against the backdrop of rapid development in integrated circuits and internet technology, various electronic products have emerged in abundance, becoming an essential part of today's society. Currently, major companies worldwide are developing their own microcontroller products to meet market demands. With the development of industries such as the Internet of Things, automotive electronics, and industrial control, the downstream application demand for microcontrollers (MCUs) will continue to rise, providing ample room for market expansion in the MCU industry.

[0003] An MCU (Microcontroller Unit) is a system computer that integrates peripherals such as memory, input / output ports, timers, serial communication ports, and digital-to-analog converters (DACs). Its core is the Central Processing Unit (CPU). MCUs can handle various complex and large instructions and have powerful functional expansion capabilities. They can be classified according to the length of data the processor participates in a single operation, i.e., the bit width, including 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit. According to information published at CISA in 2020, 8-bit and 32-bit MCUs accounted for 43% and 54% of the market share in the domestic MCU market, respectively, making them the most widely used. 8-bit MCUs are widely used in basic fields such as low-to-mid-range industrial control due to their advantages such as security, stability, simple and flexible structure, ease of design, and low cost. Compared to 8-bit MCUs, 32-bit MCUs exhibit superior computing power and can handle a larger number of external devices simultaneously. Therefore, they are widely used in more high-end and complex scenarios such as smart homes and automotive electronics.

[0004] Initially, research on MCUs, both domestically and internationally, was constrained by the command and data processing capabilities of the processor core, resulting in relatively low computing speed and operating efficiency. However, with in-depth research into system architecture and chip technology, MCU performance and operating speed have been greatly improved. In today's rapidly developing microcontroller technology, MCUs have become a focus of attention due to their low power consumption and low cost. However, considering the overall development status both domestically and internationally, domestic research is still in its early stages and requires further in-depth exploration. Summary of the Invention

[0005] The purpose of this invention is to provide a portable and low-power MCU device that can achieve better performance.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A portable and low-power MCU device includes an instruction architecture, a memory architecture, and a pipeline architecture in its core; the instruction architecture, memory architecture, and pipeline architecture have been simplified.

[0008] In terms of peripherals, it is designed to meet the needs of current industrial scenarios, and modularizes modules such as UART, SPI and TMR0, and implements them based on the SFR bus protocol;

[0009] It uses a simplified instruction set architecture and is compatible with the PIC16F8X series instruction set.

[0010] Based on the different instruction types, they are classified into file register byte operation instructions, file register bit operation instructions, immediate value operation instructions, and fixed encoding format control instructions; in all operation instructions, the opcode field is located in the highest bit field, which contains the information of instruction type and function information.

[0011] Further improvements include: the low-memory architecture adopts the Haver structure and successfully achieves processor optimization through the internal microarchitecture design of the Core module, including the instruction memory area and the data memory area.

[0012] The instruction storage space has a depth of 8196, which improves instruction execution speed and reliability by allocating different sizes and numbers of regions on each memory location; the use of partitioning and address translation techniques makes the instruction storage widely applicable.

[0013] This device adopts a hardware architecture based on a memory management unit and an instruction manager. The instruction storage space is divided into four pages, each with a depth of 2048. When encountering addressing scenarios with large spans, various addressing modes are used to directly jump to the next address.

[0014] There is a mapping relationship between the instruction memory and registers. If there is no memory residue during program execution, the entire operating system needs to be reinitialized. After the system reset is completed, the program pointer will automatically point to the address of the reset vector, and then it will automatically jump to the entry point of the main program to continue executing the main program. The compiler will automatically assign a value to the entry point of the main program. If the main program encounters an error, and a new input or operation request occurs in the program, it needs to be rewritten and compiled to ensure the normal operation of the system. When the kernel executes the main program, once an interrupt occurs, the program pointer will automatically jump to the entry address of the interrupt routine, thereby ensuring the normal operation of the program.

[0015] Data storage is divided into four independent pages. Each page includes three register areas with special functions, a general-purpose register area, and a common mapping area. Each partition also has a dedicated function register area. To store registers with special functions, low-address units are installed on each page. These mainly include configuration registers of two types: kernel and peripheral. At a specific time, these special-function register areas read and write data files according to certain rules. General-purpose registers store software-defined variables and general data in the high-address units of each page.

[0016] A further improvement is made: the device adopts a double-layer shallow flow structure; wherein, the first flow line is used for finger fetching, and the second flow line is used for execution;

[0017] In the second pipeline, instruction decoding, operand fetching, execution, and write-back can be performed on the edges of the four clock cycles respectively.

[0018] Further improvements are made as follows: The low-end processor core and peripheral IP design are as follows:

[0019] The processor core comprises eight functional modules: dedicated register file module, program counter module, instruction decoder module, arithmetic unit module, controller module, interrupt control module, clock / reset management module, and stack module.

[0020] The main function of the dedicated register file module is to set working information for the kernel and peripheral devices, and to record various important flag signals generated during program execution in real time. This module consists of six registers with special functions, namely the indirect addressing mode register, program counter, status register, file select register, program counter and working register.

[0021] Further improvements are made as follows: The low-UART module design is as follows:

[0022] UART is an asynchronous transmitter that allows data to be transmitted normally without the need for a clock line by setting the transmission format and rate at the receiving and transmitting ends.

[0023] The device is configured with two types of registers: the first is the UART peripheral device register, which can be configured to control the UART operating mode; the second is the core interrupt register, which the kernel needs to access via interrupts when it needs to obtain external data.

[0024] The UART module of this device is a hardware circuit-based, software-configurable design. This module supports 8-bit and 9-bit data transmission modes, and provides optional parity bits and 1 stop bit. This module supports receive interrupt function. This module is configured with a custom protocol interface for data exchange with other devices.

[0025] The UART module consists of two parts: SFR bus control logic and UART transceiver control logic. The SFR bus control part is used to realize data transmission with the CPU. According to the CPU's instruction configuration, it allocates working registers related to the UART module, detects the corresponding status registers, and performs read and write operations on the transceiver registers. By using configuration information, the UART transceiver control logic transmits, receives, and buffers data information at different baud rates, detects whether errors occur in the transmitted data frames, and outputs the results as flag bits.

[0026] Further improvements are made to the low-SPI module design as follows:

[0027] The design of this module is divided into two parts: SFR bus control logic and SPI transceiver control logic. The SPI transceiver control logic includes the following modules: REGCON transmit signal control module, TRIG trigger control module, BAUDGEN clock divider module, RX data receive module, and TX data transmit module.

[0028] Further improvements are made as follows: The low-TMR0 module design is as follows:

[0029] The TMR0 module offers two driving modes: internal clock and external clock. With external clock driving, the trigger edge can be selected independently. The timer has an eight-bit prescaler and a counter register. The eight-bit prescaler can be programmed in software, and the counter register is read and written by the CPU. When the counter register overflows, an interrupt request is triggered.

[0030] 8. A portable and low-power MCU device according to claim 1, characterized in that: the GPIO module is designed as follows,

[0031] Two sets of GPIOs consisting of 8 pins are used. Each pin is controlled by the corresponding bit in the TRIS register. Input signals are represented by a high level, while output signals are represented by a low level. When setting the interrupt source, the enable signal is first passed to the RBIE bit of the INTCON register.

[0032] If you need to operate on a register, you can select different registers to perform the operation separately.

[0033] Further improvements are made as follows: The low WDT module design is as follows:

[0034] The WDT is a module used to detect the running status of the MCU program. This device uses a watchdog timer to detect the system. When the program runs abnormally, the overflow signal is sent to the frequency divider and a watchdog overflow signal is generated based on the division ratio. This watchdog signal is then input to the core's reset management module, which triggers a global reset. When the program runs normally, it will not trigger a reset.

[0035] Further improvements include: low-power design and enhancements.

[0036] (1) Operand isolation design

[0037] The ALU is a computing unit composed of 16 arithmetic circuits. Instructions are translated into ALU-type instructions and non-ALU-type instructions. The opcode, SRC1, and SRC2 operands contained in each instruction are transmitted to the ALU unit after the calculation is completed. After the calculation is completed, the ALU outputs the result and writes it to the target memory unit, while recording three flag bits. Before inputting the SRC1 and SRC2 operands, the device introduces an operand isolation register. This register can pre-compile the output according to the operation data input to the memory array before transmitting it to the decoding unit. Once the decoding unit detects that the current instruction is a non-ALU instruction, it will set the two source operands to zero and match the opcode with the NOP instruction, thereby completely terminating the operation in the ALU.

[0038] (2) Sleep Wake-up Mode

[0039] The device employs two wake-up methods. One method uses a watchdog timer, which continues to operate even when the system is in sleep mode. When the count overflows, it triggers a system reset, thus achieving timed wake-up. The other method initializes the system using a sleep enable signal after it enters sleep mode and then initiates sleep mode via an interrupt, which also achieves a certain degree of wake-up effect. Alternatively, an interrupt request can be used to trigger the crystal oscillator to restart, thereby achieving wake-up.

[0040] Due to the adoption of the above technical solution, the technical effects achieved by this invention are as follows:

[0041] This invention is compatible with the MAPLAB integrated development environment and has good portability. Furthermore, this invention improves the arithmetic unit by employing operand isolation, effectively reducing the dynamic power consumption of the MCU.

[0042] The performance of this invention has been optimized, and its actual use has yielded good results. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the MCU storage architecture of the present invention.

[0044] Figure 2 This is a timing diagram of the state machine architecture of the present invention.

[0045] Figure 3 This is a timing diagram of the multi-clock architecture of the present invention.

[0046] Figure 4 This is a schematic diagram of the two-stage production line of the present invention.

[0047] Figure 5 This is a UART design structure diagram of the present invention.

[0048] Figure 6 This invention relates to the operand isolation circuit of the ALU. Detailed Implementation

[0049] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0050] This invention relates to a portable and low-power MCU device, primarily comprising two parts: a core and peripherals. Regarding the core, this invention simplifies the instruction architecture, memory architecture, and pipeline architecture. Simultaneously, regarding the peripherals, this invention is designed to meet the needs of current industrial scenarios, modularizing modules such as UART, SPI, and TMR0, and implementing them based on the SFR bus protocol.

[0051] MCU architecture design:

[0052] (1) Instruction Architecture

[0053] To improve portability and reduce cost and power consumption, this innovation uses a simplified instruction set architecture, compatible with the PIC16F8X series instruction set, containing 35 instructions. Each instruction has a corresponding code block or byte table. Depending on the instruction type, they can be categorized into different classes such as file register byte operation instructions, file register bit operation instructions, immediate value operation instructions, and fixed encoding format control instructions. In all operation instructions, the opcode field is located in the highest bit segment, containing various information such as instruction type and function information.

[0054] (2) Memory Architecture

[0055] Currently, mainstream MCU architectures include Von Neumann and Haver, which are widely favored. This paper analyzes the structural differences and respective advantages and disadvantages of these two architectures, and proposes optimization schemes for both. The Von Neumann architecture does not strictly distinguish between instruction and data storage areas, simply using time-sharing multiplexing for computation, but this method is limited in processing speed. The Haver architecture, on the other hand, clearly separates instruction and data storage areas within the memory module, allowing the core to fetch data and instructions simultaneously within a clock cycle, significantly improving operating speed. This invention adopts the Haver architecture and successfully achieves processor optimization through microarchitectural design within the Core module. The specific steps are as follows: Figure 1 .

[0056] The instruction storage space provided in this invention has a depth of up to 8196, sufficient to accommodate a large number of instructions to meet the needs of various application scenarios. Instruction execution speed and reliability are improved by allocating regions of different sizes and numbers on each memory location. The use of partitioning and address translation techniques makes the instruction storage more widely applicable. Based on the analysis of existing systems, this invention designs a hardware architecture based on a memory management unit and an instruction manager. To improve efficiency, the instruction storage space is divided into four pages, each with a depth of 2048. In addressing scenarios with large spans, various addressing modes can be used to achieve direct jumps. Furthermore, because there is a mapping relationship between the instruction memory and registers, if there is no memory residue during program execution, the entire operating system needs to be reinitialized. Typically, after a system reset, the program pointer automatically points to the address of the reset vector, and then it automatically jumps to the main program's entry point to continue executing the main program. The compiler automatically assigns a value to the main program's entry point. If the main program encounters an error, and new input or operation requests appear in the program, it needs to be rewritten and compiled to ensure the system's normal operation. When the kernel executes the main program, once an interrupt occurs, the program pointer will automatically jump to the entry address of the interrupt routine, thus ensuring that the program works normally.

[0057] This invention divides data storage into four independent pages. Each page primarily includes three register areas with special functions, a general-purpose register area, and a common mapping area. Each partition has its own dedicated function register area. To store registers with special functions, low-address units are installed on each page; these mainly include configuration registers for the kernel and peripherals. At a specific time, these special-function register areas read and write data files according to certain rules. The general-purpose registers store software-defined variables and general data, stored in the high-address units of each page. This allows for fully independent processing of data in different pages. Furthermore, the mapping of the first page's 70H to 7FH to the entire page's common storage area allows data to be freely shared between storage units in different pages, achieving efficient data management.

[0058] (4) Pipeline architecture

[0059] To reduce costs, save space, and lower power consumption, this invention employs a two-layer shallow pipeline structure. The first pipeline is used for instruction fetching, and the second pipeline is used for execution. In the second pipeline, instruction decoding, operand fetching, execution, and write-back can be performed on the edges of four clock cycles, achieving high data processing efficiency. This design method not only achieves the requirements of saving space and reducing power consumption but also significantly improves speed. More importantly, it effectively solves the various logic problems caused by deep pipelines while reducing circuit complexity. Furthermore, this solution utilizes a simple shift register to implement all the above functions. See [link to documentation]. Figure 4 The production line of this invention uses a dual-level system.

[0060] Processor core and peripheral IP design:

[0061] The microprocessor core is the most crucial part of the MCU system, responsible for the important tasks of decoding, executing, storing, and writing back input instructions, thereby achieving accurate control of the entire system's operation. During the design process, the interrelationships and coordination between various functional areas must be fully considered to ensure the chip functions properly and achieves maximum efficiency. This invention is divided into eight functional modules: a dedicated register file module, a program counter module, an instruction decoding module, an arithmetic unit module, a controller module, an interrupt control module, a clock / reset management module, and a stack module.

[0062] The main function of the special register file module is to set up working information for the kernel and peripheral devices, and to record various important flag signals generated during program execution in real time. This module consists of six registers with special functions, as shown in Table 1.

[0063] Table 1 Kernel-related special function registers

[0064]

[0065] The main function of the program counter module is to analyze the decoding, calculation results, and external interrupts of the current instruction to determine the address of the next instruction, ensuring the normal operation of the system. Based on this, it then performs other corresponding operations to execute subsequent functions. The program counter consists of three parts: the instruction decoding module, the arithmetic unit module, and registers. The instruction decoding module is responsible for transmitting instruction information read from memory serially to the arithmetic unit module, so that the corresponding data values ​​can be calculated and sent to the registers for storage. This includes important information such as the opcode, operand address, immediate value, and destination address, enabling high-precision control over the operation of other modules. The execution control code module can extract key positions from the operation sequence, generate a new operation sequence based on that position, and finally merge it with the original operation sequence to form a complete operation sequence. By performing 16 operations on the two input source operands and the opcode, the arithmetic unit module can output the obtained operation results and important flag information in a unified manner, thereby achieving efficient data processing. The intermediate processing unit module is used to process the data generated by various operations and the control data obtained from multiple ports. Based on the interconnect bus, the controller module controls the read / write timing of special function registers, general-purpose registers, and the W register, and outputs corresponding read / write enable signals. The communication module transmits control data and status reports, as well as communication protocols with external devices. The interrupt control module has the ability to synchronize and respond to interrupt request signals from multiple interrupt sources, thereby generating system interrupt signals. The memory module is responsible for storing data and the status of devices connected to the memory interface. The status of devices connected to the memory interface, as well as the clock information from the external crystal oscillator, can be received by the clock / reset management module. This module can also generate multiple clock signals throughout the system, such as a reference clock, a four-phase clock, and an instruction cycle clock. These signals drive the entire system to work normally, manage the reset source, and ultimately obtain the system reset signal. The data storage module is typically used to store data formats and related parameters required by the application. Although the stack module has the ability to save subroutines and the instruction addresses before corresponding interrupts, it is important to note that it cannot be directly read or written by software.

[0066] UART module design:

[0067] As an asynchronous transmitter, UART ensures data transmission without the need for a clock line by setting the transmission format and rate at both the receiving and transmitting ends. This effectively reduces system overhead and improves system performance. To implement UART's transmit and receive functions, this invention configures two types of registers: the first is the UART peripheral device register, which allows configuration of the UART's operating mode; the second is the core interrupt register, which the kernel accesses via interrupts when it needs to obtain external data. This configuration of two registers fully adapts to the needs of kernel scheduling.

[0068] Based on this, the UART module of this invention is a configurable software design with hardware circuitry as the foundation. Furthermore, this module supports 8-bit and 9-bit data transmission modes, and provides optional parity bits and a 1-bit stop bit. In addition, this module also supports receive interrupt functionality, and its design diagram is shown below. Figure 5 As shown. A custom protocol interface is added on top of this, enabling data exchange with other devices. The scalability and flexibility of this module are significantly improved, providing more convenient conditions for system upgrades and modifications. This modular design in this invention not only saves hardware resources but also reduces development difficulty. The UART module consists of two parts: SFR bus control logic and UART transceiver control logic, and is an indispensable core component of this invention. The SFR bus control part is mainly used to realize data transmission with the CPU. According to the CPU's instruction configuration, the working registers related to the UART module can be allocated, the corresponding status registers can be detected, and read / write operations can be performed on the transceiver registers. By using configuration information, the UART transceiver control logic can realize the transmission and reception of data information at different baud rates and buffering functions, and can detect whether errors occur in the transmitted data frames, outputting the results as flag bits, providing reliable protection for data transmission.

[0069] SPI module design:

[0070] The SPI module design achieves software configurability based on hardware circuitry, supporting both master-slave transmission modes and four communication modes, and possessing interrupt reception capability. Furthermore, this module has the ability to exchange data with other peripheral devices, thus providing the system with more flexible and diverse application methods. Based on the operating principle of the SPI protocol and combined with the processor core in this invention, the module design is divided into two parts: SFR bus control logic and SPI transceiver control logic. By dividing these functional modules and combining them according to different logical relationships to form the overall system framework, the specific circuit design and analysis of each functional module on the chip are completed. The SPI transceiver control logic encompasses multiple modules, including the REGCON transmit signal control module, TRIG trigger control module, BAUDGEN clock divider module, RX data receive module, and TX data transmit module. Detailed functions of these modules are shown in Table 2.

[0071] Table 2 Functions of each module in the SPI transmit / receive control logic

[0072]

[0073]

[0074] TMR0 module design:

[0075] There are two main ways to implement timing functions in TMRO: timing and counting, which provide precise time control for the MCU. The principle of timing function is frequency division counting, while the counting method is based on pulse signals from external input. When this pulse signal changes periodically, the timing function is achieved.

[0076] The timer / counter module in this invention offers two driving methods: internal clock and external clock. Using an external clock allows for selection of the trigger edge. The timer internally includes an eight-bit prescaler and a count register. The eight-bit prescaler is programmable in software, while the count register can be read and written via the CPU. An interrupt request can be triggered when the count register overflows.

[0077] GPIO module design:

[0078] As an interface for microprocessors to communicate with the outside world, GPIO pins can not only be used for data input and output, but also be reused with other functional modules to save hardware resources, and can even realize interrupts in different working modes.

[0079] This invention employs two sets of GPIO pins, each consisting of eight pins. Each pin is controlled by a corresponding bit in the TRIS register. Input signals are represented by a high level, while output signals are represented by a low level. When setting the interrupt source, the enable signal must first be passed to the RBIE bit of the INTCON register to ensure that the interrupt request signal can be sent to the RBIF bit of INTCON. Furthermore, if an operation on a register is required, different registers can be selected for separate execution. In the specific implementation, this invention uses a method of mapping two registers to the same physical address to resolve logical conflicts between input and output directions.

[0080] WDT module design:

[0081] The Watchdog Timer (WDT) is a module specifically designed to monitor the running status of the MCU program to prevent deadlocks caused by program crashes. The WDT operates under the control of its reference clock. This invention proposes using a watchdog timer to detect system errors. When a program malfunctions, an overflow signal is sent to a frequency divider, which generates a watchdog overflow signal based on the division ratio. This watchdog signal is then input to the kernel's reset management module, triggering a global reset. When the program runs normally, no reset is triggered.

[0082] Low power consumption design and improvements:

[0083] (1) Operand isolation design

[0084] The ALU is a computing unit composed of 16 arithmetic circuits. When the input signal is inverted, it inevitably generates considerable switching power. To reduce this switching power consumption, each address in these registers needs to be assigned a corresponding operation flag so that the user knows their corresponding register value. Instructions are translated into ALU-type instructions and non-ALU-type instructions; this is the responsibility of the decoding unit. If execution of a certain type of instruction is required, the corresponding instruction can be selected from another type of instruction to achieve this purpose. When an ALU-type instruction arrives, the opcode, SRC1, and SRC2 operands contained in each instruction are transferred to the ALU unit after calculation. After the operation is completed, the ALU outputs the result and writes it to the target memory unit, while recording three flag bits. If a reinitialization or renaming operation is encountered, it returns to execute the next instruction. When the kernel receives a non-ALU-type instruction, it does not focus on the current ALU's running state; however, the ALU's source operand and opcode ports still access data for calculation and output the result. While this improves processing speed, it reduces the overall system performance. Unlike other ALU instructions, non-ALU instructions do not write the result and flag information to memory, thus avoiding interference with the normal operation of the kernel. This method allows the processor to have a good understanding of instruction execution, thereby improving processing speed. However, the existence of unused paths leads to persistent signal toggling, increasing the system's dynamic power consumption. Furthermore, using external memory requires recoding these operations, wasting resources and causing program errors. To reduce system toggling and dynamic power consumption, this invention introduces an operand isolation register before inputting the SRC1 and SRC2 operands, such as... Figure 6 As shown, this is to achieve more efficient operation. The register can pre-compile the output based on the operation data input to the memory array before transmitting it to the decoding unit. Once the decoding unit detects that the current instruction is a non-ALU instruction, it will set both source operands to zero and map the opcode to the NOP instruction, thereby completely terminating the operation within the ALU.

[0085] (2) Sleep Wake-up Mode

[0086] Once the system is configured, the MCU may remain idle for the remainder of the time. The kernel will only respond to and execute interrupt routines after peripheral modules send interrupt request signals to ensure normal system operation. Since the kernel itself does not have interrupt functionality, it must rely on other devices for auxiliary interrupt handling. When the system is idle, the kernel typically performs a series of operations, such as running infinite loops, jumping, fetching values, decoding, and executing, but these operations are ineffective and generate significant dynamic power consumption. Continuing these complex and tedious operations would consume even more power. Therefore, when the MCU is idle, a power-saving sleep mode can be used to replace these mechanical and meaningless operations, allowing the MCU to rest briefly and maintain a low power consumption level. During this process, data can be stored if necessary for future use. When control tasks need to be performed, the MCU can be woken up using interrupt requests or watchdog timers. In sleep mode, the sleep enable circuit must be activated before resuming operation. When the operating mode switches to sleep mode, the kernel needs to execute the SLEEP instruction. The MCU then decodes the sleep state, pulls the power signal high, and disables the four-phase clocks CLK_Q1, CLK_Q2, CLK_Q3, and CLK_Q4. The MCU's clock registers remain unchanged. This invention proposes two wake-up methods after entering sleep mode. One method uses a watchdog timer; even when the system is in sleep mode, the watchdog continues to work, but when the count overflows, it triggers a system reset, achieving a timed wake-up. The other method initializes the system using the sleep enable signal after it enters sleep mode, and then initiates sleep mode via an interrupt, achieving a certain degree of wake-up. The second method uses an interrupt request to trigger the crystal oscillator to restart, thus achieving wake-up. However, since the transition from the oscillation state to the stable state takes time, the interrupt request signal must remain high during this period until the system resumes normal operation; otherwise, wake-up will fail. If there is a high flag signal on the crystal oscillator at this time, it indicates that there is no fault or error information on the crystal oscillator, and no interrupt will occur. The interrupt request flag signal will only go low after the system is woken up and enters the interrupt routine.

[0087] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. An MCU device with portability and low power consumption, characterized by: In terms of the kernel, this includes instruction architecture, memory architecture, and pipeline architecture; The instruction architecture, storage architecture, and pipeline architecture have been simplified; In terms of peripherals, it is designed to meet the needs of current industrial scenarios, and modularizes modules such as UART, SPI and TMR0, and implements them based on the SFR bus protocol; It uses a simplified instruction set architecture and is compatible with the PIC16F8X series instruction set. Based on the different instruction types, they are classified into file register byte operation instructions, file register bit operation instructions, immediate value operation instructions, and fixed encoding format control instructions; in all operation instructions, the opcode field is located in the highest bit field, which contains the information of instruction type and function information.

2. The MCU device with portability and low power consumption according to claim 1, characterized in that: The memory architecture adopts the Haver structure and successfully achieves processor optimization through the internal microarchitecture design of the Core module, including the instruction storage area and the data storage area; The instruction storage space has a depth of 8196, which improves instruction execution speed and reliability by allocating different sizes and numbers of regions on each memory location; the use of partitioning and address translation techniques makes the instruction storage widely applicable. This device adopts a hardware architecture based on a memory management unit and an instruction manager. The instruction storage space is divided into four pages, each with a depth of 2048. When encountering addressing scenarios with large spans, various addressing modes are used to directly jump to the next address. There is a mapping relationship between the instruction memory and registers. If there is no memory residue during program execution, the entire operating system needs to be reinitialized. After the system reset is completed, the program pointer will automatically point to the address of the reset vector, and then it will automatically jump to the entry point of the main program and continue to execute the main program. The compiler will automatically assign a value to the entry point of the main program. If the main program encounters an error, and new input or operation requests appear in the program, it needs to be rewritten and compiled to ensure the normal operation of the system. When the kernel executes the main program, once an interrupt occurs, the program pointer will automatically jump to the entry address of the interrupt routine, thus ensuring that the program works normally. Data storage is divided into four independent pages. Each page includes three register areas with special functions, a general-purpose register area, and a common mapping area. Each partition also has a dedicated function register area. To store registers with special functions, low-address units are installed on each page. These mainly include configuration registers of two types: kernel and peripheral. At a specific time, these special-function register areas read and write data files according to certain rules. General-purpose registers store software-defined variables and general data in the high-address units of each page.

3. The MCU device with portability and low power consumption according to claim 1, characterized in that: The device employs a dual-layer shallow flow structure; the first flow line is used for finger fetching, and the second flow line is used for execution. In the second pipeline, instruction decoding, operand fetching, execution, and write-back can be performed on the edges of the four clock cycles respectively.

4. The MCU device with portability and low power consumption according to claim 1, characterized in that: The processor core and peripheral IP design are as follows. The processor core includes eight functional modules: dedicated register file module, program counter module, instruction decoding module, arithmetic unit module, controller module, interrupt control module, clock / reset management module, and stack module. The main function of the dedicated register file module is to set working information for the kernel and peripheral devices, and to record various important flag signals generated during program execution in real time. This module consists of six registers with special functions, namely the indirect addressing mode register, program counter, status register, file select register, program counter and working register.

5. The MCU device with portability and low power consumption according to claim 1, wherein: The UART module is designed as follows. UART is an asynchronous transmitter that allows data to be transmitted normally without the need for a clock line by setting the transmission format and rate at the receiving and transmitting ends. The device is configured with two types of registers: the first is the UART peripheral device register, which can be configured to control the UART operating mode; the second is the core interrupt register, which the kernel needs to access via interrupts when it needs to obtain external data. The UART module of this device is a hardware circuit-based, software-configurable design. This module supports 8-bit and 9-bit data transmission modes, and provides optional parity bits and 1 stop bit. This module supports receive interrupt function. This module is configured with a custom protocol interface for data exchange with other devices. The UART module consists of two parts: SFR bus control logic and UART transceiver control logic. The SFR bus control part is used to realize data transmission with the CPU. According to the CPU's instruction configuration, it allocates working registers related to the UART module, detects the corresponding status registers, and performs read and write operations on the transceiver registers. By using configuration information, the UART transceiver control logic transmits, receives, and buffers data information at different baud rates, detects whether errors occur in the transmitted data frames, and outputs the results as flag bits.

6. The MCU device with portability and low power consumption according to claim 1, wherein: The SPI module is designed as follows: The design of this module is divided into two parts: SFR bus control logic and SPI transceiver control logic. The SPI transceiver control logic includes the following modules: REGCON transmit signal control module, TRIG trigger control module, BAUDGEN clock divider module, RX data receive module, and TX data transmit module.

7. The MCU device with portability and low power consumption according to claim 1, wherein: The TMR0 module is designed as follows. The TMR0 module offers two driving modes: internal clock and external clock. With external clock driving, the trigger edge can be selected independently. The timer has an eight-bit prescaler and a counter register. The eight-bit prescaler can be programmed in software, and the counter register is read and written by the CPU. When the counter register overflows, an interrupt request is triggered.

8. The MCU device with portability and low power consumption according to claim 1, wherein: The GPIO module is designed as follows: Two sets of GPIOs consisting of 8 pins are used. Each pin is controlled by the corresponding bit in the TRIS register. Input signals are represented by a high level, while output signals are represented by a low level. When setting the interrupt source, the enable signal is first passed to the RBIE bit of the INTCON register. If you need to operate on a register, you can select different registers to perform the operation separately.

9. The MCU device with portability and low power consumption according to claim 1, wherein: The WDT module is designed as follows. The WDT is a module used to detect the running status of the MCU program. This device uses a watchdog timer to detect the system. When the program runs abnormally, the overflow signal is sent to the frequency divider and a watchdog overflow signal is generated based on the division ratio. This watchdog signal is then input to the core's reset management module, which triggers a global reset. When the program runs normally, it will not trigger a reset.

10. The MCU device with portability and low power consumption according to claim 1, wherein: Low power consumption design and improvements (1) Operand isolation design The ALU is a computing unit composed of 16 arithmetic circuits. Instructions are translated into ALU-type instructions and non-ALU-type instructions. The opcode, SRC1, and SRC2 operands contained in each instruction are transmitted to the ALU unit after the calculation is completed. After the calculation is completed, the ALU outputs the result and writes it to the target memory unit, while recording three flag bits. Before inputting the SRC1 and SRC2 operands, the device introduces an operand isolation register. This register can pre-compile the output according to the operation data input to the memory array before transmitting it to the decoding unit. Once the decoding unit detects that the current instruction is a non-ALU instruction, it will set the two source operands to zero and match the opcode with the NOP instruction, thereby completely terminating the operation in the ALU. (2) Sleep Wake-up Mode The device employs two wake-up methods. One method uses a watchdog timer, which continues to operate even when the system is in sleep mode. When the count overflows, it triggers a system reset, thus achieving timed wake-up. The other method initializes the system using a sleep enable signal after it enters sleep mode and then initiates sleep mode via an interrupt, which also achieves a certain degree of wake-up effect. Alternatively, an interrupt request can be used to trigger the crystal oscillator to restart, thereby achieving wake-up.

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