Load switch circuit with surge current suppression
By designing a load switching circuit with surge current suppression and employing current-limiting resistors and feedback control, the problem of insufficient current suppression in large capacitive load scenarios was solved, achieving efficient operation and improved stability of the circuit.
Patent Information
- Application Number
- CN202511934550.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-20
- Publication Date
- 2026-04-21
AI Technical Summary
Existing optimization solutions are insufficient for suppressing surge currents of large capacitive loads of hundreds of μF or more, and the additional voltage drop introduced by traditional current limiting circuits leads to a decrease in system efficiency, limiting the application of MOSFET load switches in large capacitive load scenarios.
Design a load switching circuit with surge current suppression. It adopts a main switching circuit, a switch current limiting circuit, a drive circuit and a feedback circuit. The current is limited at the moment of power-on by the current limiting resistor. The feedback control turns on the main switching circuit and turns off the switch current limiting circuit to achieve a low on-state voltage drop after the circuit is working normally.
It effectively suppresses instantaneous current upon power-on, and features a compact circuit size, low power consumption, long lifespan, and strong current-carrying capacity, thereby improving the operational stability and environmental adaptability of computer products.
Smart Images
Figure CN121907217A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power supply technology, specifically relating to a load switching circuit with surge current suppression. Background Technology
[0002] In computer power supply systems, load switches, as a key electronic control component, are typically deployed on the power supply path between the power source and the equipment. Their core function is to achieve precise power on / off management through electronic signals (such as MOSFETs or relays): when the equipment needs to enter a working state, the load switch automatically closes to establish a power supply path; while when the equipment is in standby or hibernation mode, the load switch quickly opens, cutting off the power supply to unnecessary circuits.
[0003] In traditional computer power supply system designs, relays are often used as the core control element for load switching. This approach is widely adopted due to its simple circuit structure and ease of implementation, but its application has significant limitations: relay load switches are only suitable for low-current output scenarios; if the output current is too high, it can easily lead to relay contact burning or coil overheating and damage. If a relay with a higher primary coil current carrying capacity is selected, a larger model is required, along with a sophisticated cooling system to prevent thermal failure. Furthermore, the inherent mechanical contact life of relays (typically hundreds of thousands of cycles) also limits their application in high-frequency switching scenarios. These factors collectively restrict the applicability of relay load switches in complex power supply systems.
[0004] In recent years, MOSFET-based load switching circuits have been widely used in computer power supply systems. This solution, centered on a P-channel MOSFET connected in series with its positive input, achieves millisecond-level precise control of the output power supply via a drive signal, exhibiting significant advantages over traditional relay solutions: device size is reduced by more than 60%, it can stably handle high current outputs of tens of amperes, and it has no mechanical contact lifespan limitations, with a theoretical lifespan exceeding one million cycles. However, when the load is capacitive and its capacitance exceeds 100μF, the capacitor charging current spike at the moment the MOSFET turns on can reach 5-10 times the rated current, potentially causing avalanche breakdown and load control failure. Existing optimization solutions have significant limitations: soft-start circuits achieve slow start-up by connecting a small capacitor (typically <100nF) in parallel at the gate and source terminals, but due to the capacitor value, their suppression effect on large capacitive loads of hundreds of μF or more is insufficient, and the prolonged start-up time easily leads to heat accumulation in the MOSFET; while traditional current limiting circuits can suppress spikes, the additional voltage drop introduced by the series resistor causes a 3-5% decrease in system efficiency. These technical bottlenecks have limited the further application of MOSFET load switches in high-capacitance load scenarios such as server power supplies and GPU power supplies, and breakthroughs are urgently needed by developing new circuits.
[0005] Therefore, it is necessary to design a load switch that will not damage the MOSFET when the load capacitance is large, thereby ensuring the safety and reliability of electronic devices. Summary of the Invention
[0006] (a) Technical problems to be solved
[0007] The technical problem to be solved by this invention is how to provide a load switching circuit with surge current suppression to address the obvious limitations of existing optimization schemes: soft-start circuits achieve slow start by connecting a small-capacity capacitor in parallel at the GS terminals, but due to the limited capacitance value, the suppression effect on large capacitive loads of several hundred μF or more is insufficient, and the extended start-up time easily leads to heat accumulation in the MOSFET; while traditional current limiting circuits can suppress spikes, the additional voltage drop introduced by the series resistor causes a 3-5% decrease in system efficiency.
[0008] (II) Technical Solution
[0009] To solve the above-mentioned technical problems, the present invention proposes a load switching circuit with surge current suppression, which includes: a main switching circuit, a switching current limiting circuit, a driving circuit 1, a driving circuit 2, and a feedback circuit.
[0010] When the input is powered on, the external ON / OFF signal is pulled from high level to low level. The driver circuit 2 outputs a low level to the MOSFET of the current limiting circuit, and the MOSFET turns on. The current flows through the MOSFET and then through the current limiting resistor to the output terminal. When the output voltage rises to a certain voltage, the feedback circuit FB signal controls the driver circuit 2 to turn off the MOSFET in the current limiting circuit. At the same time, the feedback circuit FB signal and the ON / OFF signal jointly control the driver circuit 1 to output a low level to the main switching circuit, so that the MOSFET in the main switching circuit turns on.
[0011] When the ON / OFF signal level goes high, the drive circuit 1 outputs a high level to the MOSFET of the main switch circuit, the main switch circuit is turned off, the drive circuit 2 outputs a high level, the MOSFET in the switch current limiting circuit is turned off, and finally no power is output.
[0012] (III) Beneficial Effects
[0013] This invention proposes a load switching circuit with surge current suppression. The circuit limits the output current at power-on instantaneously through a switching current limiting circuit. Feedback control activates the main switching circuit and deactivates the switching current limiting circuit, maintaining a low on-state voltage drop after normal operation. This circuit offers advantages such as compact size, low power consumption, long service life, high current carrying capacity, and high reliability, effectively improving the overall operational stability and environmental adaptability of computer products. Attached Figure Description
[0014] Figure 1 This is a block diagram of the present invention;
[0015] Figure 2 This is a schematic diagram of the load switch circuit of the present invention. Detailed Implementation
[0016] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0017] The purpose of this invention is to use discrete components and a current-limiting resistor to suppress current spikes during power-on. Once the circuit output voltage is normal, the parallel switching circuit is controlled to operate, achieving the advantages of small current spikes during power-on and low circuit losses after normal operation.
[0018] like Figure 1 The diagram shown is a block diagram of the entire machine. This invention provides a load switching circuit with surge current suppression, which mainly includes: a main switching circuit, a switching current limiting circuit, a drive circuit 1, a drive circuit 2, and a feedback circuit.
[0019] When the input is powered on, the external ON / OFF signal is pulled from high level to low level. The driver circuit 2 outputs a low level to the MOSFET of the current limiting circuit, and the MOSFET turns on. The current flows through the MOSFET and then through the current limiting resistor to the output terminal. When the output voltage rises to a certain voltage, the feedback circuit FB signal controls the driver circuit 2 to turn off the MOSFET in the current limiting circuit. At the same time, the feedback circuit FB signal and the ON / OFF signal jointly control the driver circuit 1 to output a low level to the main switching circuit, so that the MOSFET in the main switching circuit turns on.
[0020] When the ON / OFF signal level goes high, the drive circuit 1 outputs a high level to the MOSFET of the main switch circuit, the main switch circuit is turned off, the drive circuit 2 outputs a high level, the MOSFET in the switch current limiting circuit is turned off, and finally no power is output.
[0021] in,
[0022] The main switching circuit includes MOSFET S1; the switching current limiting circuit includes MOSFET S5 and resistor R6; drive circuit 1 includes resistors R1, R2, R3, R4, and R5, Zener diode V1, and transistors S2, S3, and S4; drive circuit 2 includes resistors R7, R8, R9, R10, and R12, Zener diode V2, and transistors S6, S7, and S8; the feedback circuit includes resistors R11 and R13. Resistors R11 and R13 form a voltage divider circuit, connected between the output terminal and ground, and the FB signal is obtained through voltage division.
[0023] The specific design of the load switching circuit includes: one end of resistor R1 is connected to the input Va, and the other end is connected to the external ON / OFF enable; one end of resistor R2 is connected to the input Va, and the other end is connected to the collector of NPN transistor S2; the negative terminal of Zener diode V1 is connected to Va, and the positive terminal is connected to the gate of MOSFET S1; one end of resistor R3 is connected to Va, and the other end is connected to the gate of MOSFET S1; the source of MOSFET S1 is connected to Va, the gate is connected to one end of resistor R4, the other end of resistor R4 is connected to the collector of NPN transistor S4, and the drain of MOSFET S1 is connected to the output Vb; the base of transistor S4 is connected to one end of resistor R5, which is connected to the collector of PNP transistor S3, and the emitter of transistor S4 is connected to the other end of resistor R5 and also connected to GND; the base of transistor S2 is connected to the feedback signal FB, the emitter is connected to the emitter of transistor S3, and the base of transistor S3 is connected to the external ON / OFF enable.
[0024] One end of resistor R7 is connected to the input Va, and the other end is connected to an external ON / OFF enable. One end of resistor R8 is connected to the input Va, and the other end is connected to the emitter of PNP transistor S6. The cathode of Zener diode V2 is connected to Va, and the anode is connected to the gate of MOSFET S5. One end of resistor R9 is connected to Va, and the other end is connected to the gate of MOSFET S5. The source of MOSFET S5 is connected to Va, and the gate is connected to one end of resistor R10. The other end of resistor R10 is connected to the collector of NPN transistor S7. The drain of MOSFET S5 is connected to one end of resistor R6, and the other end of resistor R6... One end is connected to the output Vb; the base of transistor S7 is connected to one end of R12, to the collector of NPN transistor S8, and to the collector of PNP transistor S6; the emitter of transistor S7 is connected to the other end of resistor R12, to the emitter of transistor S8, and also to GND; the base of transistor S8 serves as the feedback signal FB, and is also connected to one end of resistor R11, the other end of which is connected to the output Vb; the feedback signal FB is connected to one end of resistor R13, the other end of which is connected to GND; the base of transistor S6 is connected to an external ON / OFF enable.
[0025] To achieve the above objectives, the present invention provides a load switching circuit with surge current suppression, such as... Figure 2 The diagram shown is a schematic of a load switch circuit, which mainly consists of a main switch circuit, a switch current limiting circuit, a drive circuit 1, a drive circuit 2, and a feedback circuit.
[0026] The collector of NPN transistor S2 is designated as node M1, and the emitter as node M2. The collector of transistor S3 is designated as node M3. The gate of MOSFET S1 is designated as node M4. The collector of transistor S4 is designated as node M5. The emitter of transistor S6 is designated as node M6. The gate of MOSFET S5 is designated as node M7. The collector of transistor S7 is designated as node M8, and the base is designated as node M9.
[0027] When input Va is powered on, the external enable ON / OFF in drive circuit 2 is pulled from high level to low level. The base level of PNP transistor S6 is low, and the collector and emitter of transistor S6 are turned on. After voltage division by R8 and R12, the level of node M9 becomes high. The collector and emitter of NPN transistor S7 are turned on. After voltage division by R9 and R10, the voltage of node M7 is lower than the voltage of Va. At this time, P-channel MOSFET S5 in the switching current limiting circuit is turned on. The current flows through MOSFET S5 and then through current limiting resistor R6 to output Vb.
[0028] In the feedback circuit, the Vb voltage is divided by R11 and R13 to form the feedback voltage FB, which drives the NPN transistor S8. The collector and emitter of transistor S8 are turned on, the level of node M9 is pulled low, transistor S7 is turned off, the level of node M7 is high, and MOSFET S5 is turned off.
[0029] In drive circuit 1, FB is at a high level, NPN transistor S2 is turned on, node M2 is at a high level, external enable ON / OFF is at a low level, PNP transistor S3 is turned on, after voltage Va is divided by R2 and R5, the level of node M3 becomes high, NPN transistor S4 is turned on, after voltage Va is divided by R3 and R4, the voltage of node M4 is lower than the voltage Va, at this time, P-channel MOSFET S1 in the switching current limiting circuit is turned on, and the current flows to the output Vb after passing through MOSFET S1.
[0030] When the external enable ON / OFF is floating or high, in drive circuit 1, transistor S3 is off, node M3 is low, transistor S4 is off, the level of node M4 is the same as the input Va voltage, and MOSFET S1 is off; in drive circuit 2, S6 is off, node M9 is low, transistor S7 is off, the level of node M7 is the same as the input Va voltage, MOSFET S5 is off, and output Vb is not energized.
[0031] Beneficial effects:
[0032] This invention provides a load switching circuit with surge suppression. It limits the output current at power-on instantaneously through a switching current-limiting circuit, and uses feedback control to turn on the main switching circuit and turn off the switching current-limiting circuit, maintaining a low on-state voltage drop after the circuit is operating normally. This circuit has advantages such as compact size, low power consumption, long service life, strong current carrying capacity, and high safety and reliability, effectively improving the overall operational stability and environmental adaptability of computer products.
[0033] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A load switching circuit with surge current suppression, characterized in that, The load switching circuit includes: a main switching circuit, a switching current limiting circuit, a drive circuit 1, a drive circuit 2, and a feedback circuit; When the input is powered on, the external ON / OFF signal is pulled from high level to low level. The driver circuit 2 outputs a low level to the MOSFET of the current limiting circuit. The MOSFET turns on, and the current flows through the MOSFET and then through the current limiting resistor to the output terminal. When the output voltage rises to a certain voltage, the feedback circuit FB signal controls the driver circuit 2 to turn off the MOSFET in the current limiting circuit. At the same time, the feedback circuit FB signal and the ON / OFF signal jointly control the driver circuit 1 to output a low level to the main switching circuit, so that the MOSFET in the main switching circuit turns on. When the ON / OFF signal level becomes high, the drive circuit 1 outputs a high level to the MOSFET of the main switch circuit, the main switch circuit is turned off, the drive circuit 2 outputs a high level, the MOSFET in the switch current limiting circuit is turned off, and finally no power is output.
2. The load switching circuit with surge current suppression as described in claim 1, characterized in that, The main switching circuit includes: MOSFET S1; the switching current limiting circuit includes: MOSFET S5 and resistor R6; the drive circuit 1 includes: resistors R1, R2, R3, R4, and R5, Zener diode V1, and transistors S2, S3, and S4; the drive circuit 2 includes: resistors R7, R8, R9, R10, and R12, Zener diode V2, and transistors S6, S7, and S8; the feedback circuit includes: resistors R11 and R13.
3. The load switching circuit with surge current suppression as described in claim 2, characterized in that, Resistors R11 and R13 form a voltage divider circuit, which is connected between the output terminal and ground. The FB signal is obtained by voltage division.
4. The load switching circuit with surge current suppression as described in claim 2, characterized in that, One end of resistor R1 is connected to the input Va, and the other end is connected to the external ON / OFF enable. One end of resistor R2 is connected to the input Va, and the other end is connected to the collector of NPN transistor S2. The cathode of Zener diode V1 is connected to Va, and the anode is connected to the gate of MOSFET S1. One end of resistor R3 is connected to Va, and the other end is connected to the gate of MOSFET S1. The source of MOSFET S1 is connected to Va, and the gate is connected to one end of resistor R4. The other end of resistor R4 is connected to the collector of NPN transistor S4, and the drain of MOSFET S1 is connected to the output Vb. The base of transistor S4 is connected to one end of resistor R5, which is connected to the collector of PNP transistor S3. The emitter of transistor S4 is connected to the other end of resistor R5 and is also connected to GND. The base of transistor S2 is connected to the feedback signal FB, and its emitter is connected to the emitter of transistor S3. The base of transistor S3 is connected to the external ON / OFF enable.
5. The load switching circuit with surge current suppression as described in claim 4, characterized in that, One end of resistor R7 is connected to the input Va, and the other end is connected to an external ON / OFF enable. One end of resistor R8 is connected to the input Va, and the other end is connected to the emitter of PNP transistor S6. The cathode of Zener diode V2 is connected to Va, and the anode is connected to the gate of MOSFET S5. One end of resistor R9 is connected to Va, and the other end is connected to the gate of MOSFET S5. The source of MOSFET S5 is connected to Va, and the gate is connected to one end of resistor R10. The other end of resistor R10 is connected to the collector of NPN transistor S7. The drain of MOSFET S5 is connected to one end of resistor R6, and the other end of resistor R6... One end is connected to the output Vb; the base of transistor S7 is connected to one end of R12, to the collector of NPN transistor S8, and to the collector of PNP transistor S6; the emitter of transistor S7 is connected to the other end of resistor R12, to the emitter of transistor S8, and also to GND; the base of transistor S8 serves as the feedback signal FB, and is also connected to one end of resistor R11, the other end of which is connected to the output Vb; the feedback signal FB is connected to one end of resistor R13, the other end of which is connected to GND; the base of transistor S6 is connected to an external ON / OFF enable.
6. The load switching circuit with surge current suppression as described in claim 5, characterized in that, The collector of NPN transistor S2 is designated as node M1, and the emitter as node M2. The collector of transistor S3 is designated as node M3. The gate of MOSFET S1 is designated as node M4. The collector of transistor S4 is designated as node M5. The emitter of transistor S6 is designated as node M6. The gate of MOSFET S5 is designated as node M7. The collector of transistor S7 is designated as node M8, and the base is designated as node M9.
7. The load switching circuit with surge current suppression as described in claim 6, characterized in that, When input Va is powered on, the external enable ON / OFF in drive circuit 2 is pulled from high level to low level. The base level of PNP transistor S6 is low, and the collector and emitter of transistor S6 are turned on. After voltage division by R8 and R12, the level of node M9 becomes high. The collector and emitter of NPN transistor S7 are turned on. After voltage division by R9 and R10, the voltage of node M7 is lower than the voltage of Va. At this time, P-channel MOSFET S5 in the switching current limiting circuit is turned on. The current flows through MOSFET S5 and then through current limiting resistor R6 to output Vb.
8. The load switching circuit with surge current suppression as described in claim 7, characterized in that, In the feedback circuit, the Vb voltage is divided by R11 and R13 to form the feedback voltage FB, which drives the NPN transistor S8. The collector and emitter of transistor S8 are turned on, the level of node M9 is pulled low, transistor S7 is turned off, the level of node M7 is high, and MOSFET S5 is turned off.
9. The load switching circuit with surge current suppression as described in claim 8, characterized in that, In drive circuit 1, FB is at a high level, NPN transistor S2 is turned on, node M2 is at a high level, external enable ON / OFF is at a low level, PNP transistor S3 is turned on, after voltage Va is divided by R2 and R5, the level of node M3 becomes high, NPN transistor S4 is turned on, after voltage Va is divided by R3 and R4, the voltage of node M4 is lower than the voltage Va, at this time, P-channel MOSFET S1 in the switching current limiting circuit is turned on, and the current flows to the output Vb after passing through MOSFET S1.
10. The load switching circuit with surge current suppression as described in claim 6, characterized in that, When the external enable ON / OFF is floating or high, in drive circuit 1, transistor S3 is off, node M3 is low, transistor S4 is off, the level of node M4 is the same as the input Va voltage, and MOSFET S1 is off; in drive circuit 2, S6 is off, node M9 is low, transistor S7 is off, the level of node M7 is the same as the input Va voltage, MOSFET S5 is off, and output Vb is not energized.