Semiconductor device and manufacturing method thereof
By forming a first polysilicon layer and a second polysilicon layer sequentially during the semiconductor device manufacturing process, and selectively etching with a hard mask layer, the problem of polysilicon residue was solved, improving product yield and reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN PENGXIN MICRO INTEGRATED CIRCUIT MFG CO LTD
- Filing Date
- 2024-10-17
- Publication Date
- 2026-04-21
AI Technical Summary
During the semiconductor device manufacturing process, polysilicon residues at the fin and gate structure connections are difficult to remove, affecting product yield and reliability.
By forming a first polysilicon layer and a second polysilicon layer on the substrate sequentially, and using a hard mask layer as a mask, selective etching is performed to form the gate electrode layer. The first polysilicon layer has a higher etching selectivity, preferentially removing polysilicon residue at the connection between the fin and the gate structure.
It effectively reduces polysilicon residue, improving product yield and reliability.
Smart Images
Figure CN121908608A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of semiconductor manufacturing, specifically to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] Currently, the FinFET (Fin Field-Effect Transistor) is a special type of semiconductor device. During device manufacturing, polysilicon is filled and etched multiple times. Due to process or equipment limitations, tiny polysilicon residues often remain in corners. For example, during wet etching, the sidewalls in the fin structure obstruct the polysilicon in corners, making it difficult for the polysilicon to contact the etching solution, resulting in persistent polysilicon residues at the fin-gate connection. These tiny polysilicon residues are typically less than 0.2µm in size and are difficult to remove using conventional cleaning methods. Furthermore, these polysilicon residues are conductive, and if they fall between the gate and source, they can affect product yield and reliability. Summary of the Invention
[0003] This application is made to address the aforementioned problems. According to one aspect of this application, a method for manufacturing a semiconductor device is provided, the method comprising: providing a substrate; forming fins extending along a first direction on the surface of the substrate; forming a first polysilicon layer covering the fins on the substrate, and forming a second polysilicon layer on the surface of the first polysilicon layer; forming a hard mask layer extending along a second direction on the second polysilicon layer, wherein the first direction intersects the second direction, and the etching selectivity ratio of the first polysilicon layer to the hard mask layer is greater than the etching selectivity ratio of the second polysilicon layer to the hard mask layer; and etching the second polysilicon layer and the first polysilicon layer using the hard mask layer as a mask to form a gate electrode layer extending along the second direction.
[0004] For example, after forming a fin extending in a first direction on the substrate surface, the method further includes: forming an isolation layer on the substrate surface at the same height as the fin, and etching away a portion of the isolation layer.
[0005] For example, etching the second polysilicon layer and the first polysilicon layer to form a gate electrode layer extending along the second direction includes: performing a first etching step to stop at the surface exposing the fin; and performing a second etching step to expose the isolation layer on the substrate.
[0006] For example, after forming a fin extending in a first direction on the surface of the substrate and before forming a first polysilicon layer covering the fin on the substrate, the method further includes forming a gate dielectric layer covering the fin on the substrate.
[0007] For example, the first polysilicon layer and the second polysilicon layer are ion-doped polysilicon layers, and the doping concentration of the first polysilicon layer is greater than the doping concentration of the second polysilicon layer.
[0008] For example, the first polycrystalline silicon layer is an ion-doped polycrystalline silicon layer, and the second polycrystalline silicon layer is an undoped polycrystalline silicon layer.
[0009] For example, the density of the first polysilicon layer is lower than that of the second polysilicon layer.
[0010] For example, the first direction is perpendicular to the second direction.
[0011] According to another aspect of this application, a semiconductor device is manufactured by the method described above.
[0012] According to another aspect of this application, an electronic device is provided, the electronic device comprising the semiconductor device described above.
[0013] The semiconductor device manufacturing method in this application forms a first polysilicon layer and a second polysilicon layer after forming the fin. The gate electrode layer is obtained by etching the first and second polysilicon layers. Because the etching selectivity of the first polysilicon layer is higher and it is closer to the corner of the fin, the etching rate of the first polysilicon layer is faster. During etching, the polysilicon at the connection between the fin and the gate structure can be fully removed, thereby effectively reducing the polysilicon residue when the etching is completed and improving product yield and reliability. Attached Figure Description
[0014] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain the application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.
[0015] Figure 1 A flowchart of a semiconductor device manufacturing method according to an embodiment of this application is shown.
[0016] Figures 2(a)-2(d) This diagram illustrates the semiconductor device after fins are formed in the manufacturing method of an embodiment of this application.
[0017] Figures 3(a)-3(d) This diagram illustrates a semiconductor device after the formation of the first polysilicon layer in the manufacturing method of an embodiment of this application.
[0018] Figures 4(a)-4(d)This diagram illustrates a semiconductor device after the formation of a second polysilicon layer in the manufacturing method of an embodiment of this application.
[0019] Figures 5(a)-5(d) This diagram illustrates the semiconductor device after the first etching in the manufacturing method of this application embodiment.
[0020] Figures 6(a)-6(d) This diagram illustrates the semiconductor device after the second etching in the manufacturing method of this application embodiment.
[0021] Reference numerals: 210, substrate; 220, isolation layer; 230, fin; 240, gate dielectric layer; 250, first polysilicon layer; 260, second polysilicon layer; 270, hard mask layer. Detailed Implementation
[0022] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.
[0023] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0024] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0025] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0027] To fully understand this invention, a detailed structure will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.
[0028] like Figure 1 As shown in the figure, this application provides a method for manufacturing a semiconductor device, the method comprising the following steps:
[0029] S110 provides a substrate.
[0030] S120, A fin extending in a first direction is formed on the surface of the substrate.
[0031] S130. A first polysilicon layer covering the fins is formed on the substrate, and a second polysilicon layer is formed on the surface of the first polysilicon layer.
[0032] S140. A hard mask layer extending along a second direction is formed on the second polysilicon layer, wherein the first direction intersects the second direction, and the etching selectivity ratio of the first polysilicon layer to the hard mask layer is greater than that of the second polysilicon layer to the hard mask layer.
[0033] S150, using a hard mask layer as a mask, etch the second polysilicon layer and the first polysilicon layer to form a gate electrode layer extending along the second direction.
[0034] The manufacturing method in this application embodiment forms a first polysilicon layer and a second polysilicon layer sequentially after forming the fin. The gate electrode layer is obtained by etching the first and second polysilicon layers. Because the etching selectivity of the first polysilicon layer is higher and it is closer to the corner of the fin, the etching rate of the first polysilicon layer is faster. During etching, the polysilicon at the connection between the fin and the gate structure can be fully removed, thereby effectively reducing the polysilicon residue when the etching is completed, and improving product yield and reliability.
[0035] For example, the semiconductor device in this application embodiment is a vertical transistor. For example, a soft structure, concentration difference, or ion implantation can be used to make the first polysilicon layer have a greater etch selectivity than the second polysilicon layer.
[0036] Specifically, a lower density polysilicon layer can be used as the first polysilicon layer, meaning the density of the first polysilicon layer is lower than that of the second polysilicon layer. Alternatively, an ion-doped polysilicon layer can be used as the first polysilicon layer, and an undoped polysilicon layer as the second polysilicon layer. Or, both the first and second polysilicon layers can be ion-doped, with the doping concentration of the first polysilicon layer being greater than that of the second polysilicon layer. The ultimate goal is to achieve a higher etching selectivity ratio between the first polysilicon layer and the hard mask layer than between the second polysilicon layer and the hard mask layer. During etching, it is easier to etch the polysilicon at the corners of the fin structure, thereby minimizing polysilicon residue. In some embodiments, the first and second directions are perpendicular. Each fin is covered with at least two gate electrode layers.
[0037] Exemplarily, the method further includes: after forming fins extending along a first direction on the substrate surface, forming an isolation layer of the same height as the fins on the substrate surface, and etching away a portion of the isolation layer. This isolates different circuit regions and reduces leakage current.
[0038] For example, the method of etching the second polysilicon layer and the first polysilicon layer to form a gate electrode layer extending along the second direction specifically includes: performing a first etching step to stop at the surface of the fin; and performing a second etching step to expose the isolation layer on the substrate. In the first etching step, the surface of the fin is exposed, and there are corner portions between the two side surfaces of the fin and the first polysilicon layer. During the second etching step, because the first polysilicon layer is closer to the two sides of the fin and has a larger etching ratio, the etching of the first polysilicon layer is preferentially performed, thereby effectively removing the polysilicon residue at the corners of the two sides of the fin in the second etching step.
[0039] Exemplarily, after forming fins extending along a first direction on the substrate surface and before forming a first polycrystalline silicon layer covering the fins on the substrate, the method further includes forming a gate dielectric layer covering the fins on the substrate. The gate dielectric layer may comprise conventional dielectric materials, such as oxides, nitrides, and oxides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum). Alternatively, the gate dielectric layer may comprise a high-k dielectric layer having a k-value (dielectric constant) typically greater than 3.9, and its constituent materials include hafnium oxide, hafnium silicon oxide, hafnium oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc. The gate dielectric layer may be formed using any of several methods employing materials suitable for the gate dielectric layer composition, including, but not limited to, thermal or plasma oxidation or nitriding methods, chemical vapor deposition methods, and physical vapor deposition methods. In some embodiments, the gate dielectric layer comprises a thermally oxidized silicon dielectric material having a thickness from about 5 to 70 angstroms.
[0040] Figures 2-6 are schematic diagrams illustrating the various steps of the semiconductor device manufacturing method according to embodiments of this application. The method of this application will be further described below with reference to Figures 2-6:
[0041] like Figures 2(a)-2(d) The diagram shows a schematic of the device after fin formation, where Figure 2(a) is a top view of the device, and Figures 2(b), 2(c), and 2(d) are cross-sectional views of Figure 2(a) in the X, Y, and X0 directions, respectively. During fabrication, a substrate 210 is first provided, and a fin 230 extending in a first direction (X(X0) in the figure) is formed on the substrate 210. The first direction is the X (X0) direction, and the second direction is the Y direction, which are perpendicular to each other. As shown in Figure 2(d), the cross-section of the fin 230 has a trapezoidal structure.
[0042] After the fin 230 is formed, an isolation layer 220 is formed on the surface of the substrate 210. A portion of the isolation layer 220 is removed by etching back, ultimately exposing the fin 230. A gate dielectric layer 240 is then formed on the surface of the fin 230, wherein the gate dielectric layer 240 can be an oxide, such as silicon oxide.
[0043] like Figures 3(a)-3(d)The diagram shows a schematic of the device after the formation of the first polysilicon layer. Figure 3(a) is a top view of the device, and Figures 3(b), 3(c), and 3(d) are cross-sectional views of Figure 3(a) in the X, Y, and X0 directions, respectively. After the fin 230 and the gate dielectric layer 240 are formed, a first polysilicon layer 250 is formed on the substrate 210. The first polysilicon layer 250 covers the isolation layer 220, the fin 230, and the gate dielectric layer 240 on the surface of the fin 230. The first polysilicon layer 250 is soft polysilicon, which can be ion-doped polysilicon with a high doping concentration. The first polysilicon layer 250 covers the fin 230 in the device. In the subsequent etching process, the fin 230 can be exposed and excess polysilicon residue on both sides of the fin 230 can be removed by etching the first polysilicon layer 250.
[0044] like Figures 4(a)-4(d) The diagram shows a schematic of the device after the formation of the second polysilicon layer. Figure 4(a) is a top view of the device, and Figures 4(b), 4(c), and 4(d) are cross-sectional views of Figure 4(a) in the X, Y, and X0 directions, respectively. After forming the first polysilicon layer 250, a second polysilicon layer 260 is formed on the surface of the first polysilicon layer 250. The first polysilicon layer has a higher etch selectivity than the second polysilicon layer and can be formed using a soft structure, different concentrations, or ion implantation. Specifically, a lower density polysilicon layer 250 can be used as the first polysilicon layer 250, meaning the density of the first polysilicon layer 250 is lower than that of the second polysilicon layer 260. Alternatively, an ion-doped polysilicon layer can be used as the first polysilicon layer 250, and an undoped polysilicon layer can be used as the second polysilicon layer 260. Or, the doping concentration of the first polysilicon layer 250 is greater than that of the second polysilicon layer 260. In some embodiments, two or more of the above methods can be used simultaneously. The ultimate goal is to ensure that the etching selectivity ratio between the first polysilicon layer 250 and the hard mask layer 270 is greater than that between the second polysilicon layer 260 and the hard mask layer 270. This makes it easier to etch the polysilicon at the corners of the fin 230 structure, thereby minimizing polysilicon residue.
[0045] like Figures 5(a)-5(d)The diagram shows the device after the first etching. Figure 5(a) is a top view of the device, and Figures 5(b), 5(c), and 5(d) are cross-sectional views of Figure 5(a) in the X, Y, and X0 directions, respectively. After forming the first polysilicon layer 250, the method further includes forming a hard mask layer 270 on the surface of the first polysilicon layer 250. The hard mask layer 270 serves as a mask for etching the first polysilicon layer 250 and the second polysilicon layer 260. After forming the mask layer, the second polysilicon layer 260 and the first polysilicon layer 250 are etched using the hard mask layer 270 as a mask to form a gate electrode layer extending along a second direction. Figures 5(a)-5(d) The diagram shows the first etching process, where the first etching step is performed to stop at the surface of the fin 230, which exposes the gate dielectric layer 240 on the surface of the fin 230.
[0046] The etching selectivity ratio is compared with the hard mask layer 270 as a reference. The etching selectivity ratio between the first polysilicon layer 250 and the hard mask layer 270 is greater than that between the second polysilicon layer 260 and the hard mask layer 270. After the first etching, as shown in Figure 5(c), the polysilicon on both sides of the fin 230 is the first polysilicon layer 250. The notch in the figure is the starting point of the next etching step. Because the etching selectivity ratio of the first polysilicon layer 250 is greater than that of the second polysilicon layer 260, the next etching will be performed from top to bottom and from the middle to the sides, thereby ensuring that as much polysilicon residue as possible is removed from both sides of the fin 230.
[0047] like Figures 6(a)-6(d) The diagram shows the device after the second etching step. Figure 6(a) is a top view of the device, and Figures 6(b), 6(c), and 6(d) are cross-sectional views of Figure 6(a) in the X, Y, and X0 directions, respectively. After the first etching step, a second etching step is performed to expose the isolation layer 220 on the substrate 210. As shown in Figure 6(c), during the second etching step, both sides of the fin 230 are covered by the first polysilicon layer 250, which has a higher etching selectivity. During the second etching step, the etching process tends to proceed from top to bottom and from the middle to the sides. Therefore, the polysilicon on both sides of the fin 230 can be effectively removed during etching, and the polysilicon residue at the corners of the fin 230 can be further removed. After the second etching is completed, a gate electrode layer covering the fin 230 is formed, completing the fabrication process.
[0048] For example, after the etching step is completed, the device can also be subjected to processes such as CMP (chemical mechanical polishing) and cleaning to obtain a device with a smoother surface.
[0049] In the manufacturing method of this application embodiment, after forming the fin 230, a first polysilicon layer 250 and a second polysilicon layer 260 are formed successively. The gate electrode layer is obtained by etching the first polysilicon layer 250 and the second polysilicon layer 260. Because the etching selectivity of the first polysilicon layer 250 is higher and closer to the corner of the fin 230, when etching the polysilicon near the corner of the fin 230, the first polysilicon layer 250 at the corner is etched first, and then the second polysilicon layer 260 is etched. This can effectively reduce the polysilicon residue when the etching is completed, and improve the product yield and reliability.
[0050] This application also provides a semiconductor device and an electronic device, wherein the electronic device includes the semiconductor device, and the semiconductor device can be prepared by the method described above.
[0051] As shown in Figure 6(b), a fin is formed on the substrate of the semiconductor device, and a gate electrode layer is covered on the fin. The gate electrode layer includes a first polysilicon layer and a second polysilicon layer, with the first polysilicon layer covering the surface of the fin. The etching selectivity of the first polysilicon layer to the hard mask layer is greater than that of the second polysilicon layer to the hard mask layer. During etching, the first polysilicon layer is located on both sides of the fin. Because the fin has a greater etching selectivity, it is easier to etch and remove the polysilicon at the corners, thereby reducing the amount of polysilicon residue generated during the etching process.
[0052] Based on this, in the semiconductor device of this application embodiment, after forming the fin, a first polysilicon layer and a second polysilicon layer are formed sequentially through the above-described manufacturing method. The gate electrode layer is obtained by etching the first polysilicon layer and the second polysilicon layer. Because the etching selectivity of the first polysilicon layer is higher and it is closer to the corner of the fin, the etching rate of the first polysilicon layer is faster. During etching, the polysilicon at the connection between the fin and the gate structure can be fully removed, thereby effectively reducing the polysilicon residue when the etching is completed, and improving product yield and reliability.
[0053] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.
[0054] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.
[0055] Similarly, it should be understood that, in order to streamline this application and aid in understanding one or more of the various inventive aspects, features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with features fewer than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.
[0056] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.
[0057] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.
[0058] The above description is merely a specific embodiment or illustration of the embodiments of this application. The scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. The scope of protection of this application shall be determined by the scope of the claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, The method includes: Provide substrate; Fins extending in a first direction are formed on the surface of the substrate; A first polysilicon layer covering the fins is formed on the substrate, and a second polysilicon layer is formed on the surface of the first polysilicon layer; A hard mask layer extending in a second direction is formed on the second polysilicon layer, wherein the first direction intersects the second direction, and the etching selectivity ratio of the first polysilicon layer to the hard mask layer is greater than that of the second polysilicon layer to the hard mask layer. The second polysilicon layer and the first polysilicon layer are etched using the hard mask layer as a mask to form a gate electrode layer extending along the second direction.
2. The method according to claim 1, characterized in that, After forming a fin extending in a first direction on the substrate surface, the method further includes: forming an isolation layer on the substrate surface at the same height as the fin, and etching away a portion of the isolation layer.
3. The method according to claim 2, characterized in that, The etching of the second polysilicon layer and the first polysilicon layer to form a gate electrode layer extending along the second direction includes: Perform the first etching step to stop at the surface exposing the fin; A second etching step is performed to expose the isolation layer of the substrate.
4. The method according to claim 1, characterized in that, After forming fins extending in a first direction on the substrate surface and before forming a first polysilicon layer covering the fins on the substrate, the method further includes: A gate dielectric layer covering the fin is formed on the substrate.
5. The method according to claim 1, characterized in that, The first polysilicon layer and the second polysilicon layer are ion-doped polysilicon layers, and the doping concentration of the first polysilicon layer is greater than the doping concentration of the second polysilicon layer.
6. The method according to claim 1, characterized in that, The first polycrystalline silicon layer is an ion-doped polycrystalline silicon layer, and the second polycrystalline silicon layer is an undoped polycrystalline silicon layer.
7. The method according to claim 1, characterized in that, The density of the first polycrystalline silicon layer is lower than that of the second polycrystalline silicon layer.
8. The method according to any one of claims 1-7, characterized in that, The first direction is perpendicular to the second direction.
9. A semiconductor device, characterized in that, The semiconductor device is manufactured by the method described in any one of claims 1-8.
10. An electronic device, characterized in that, The electronic device includes the semiconductor device of claim 9.