Semiconductor device

Abstract

A semiconductor device is provided with: an n-type first semiconductor region (11); and an n-type common contact region (12) that is formed locally at a high impurity concentration on the first semiconductor region and that is connected to a common electrode that also serves as a first main electrode of the switching element and a protection element-side first electrode on the protection element side. The switching element region (R1) is provided with: a p-type second semiconductor region (13) formed in the first semiconductor region at a location spaced apart from the common contact region in the radial direction; and an n-type third semiconductor region (14) formed in the second semiconductor region, the second main electrode is connected to the third semiconductor region (14), and in the protection element region (R2), a p-type fourth semiconductor region (16) formed in the first semiconductor region is provided at a location spaced apart from the common contact region (12) in the radial direction. The protection element-side second electrode is connected to the fourth semiconductor region (16).

Description

Technical Field

[0001] This disclosure relates to a semiconductor device that combines a horizontal switching element with a protection element. Background Technology

[0002] As power semiconductor devices, laterally diffused MOS (LDMOS) transistors (switching elements) with a drift layer through which the conduction current flows in the planar direction of the semiconductor layer are preferred due to their improved breakdown voltage. In this case, the length of the region (high-voltage region) along the electric field direction, which should be ensured to achieve a particularly high electric field strength at the off state, is set in the in-plane direction of the semiconductor layer in a manner that ensures the breakdown voltage.

[0003] Furthermore, as described in Patent Document 1, a protective element (e.g., a diode) is connected between the source and drain of the LDMOS in the LDMOS. When a surge voltage exceeding the withstand voltage is applied to the LDMOS, the protective element breaks down instead of the LDMOS to bypass the current, thereby preventing the LDMOS or the circuit connected to it from being damaged.

[0004] In this case, the breakdown voltage of the protective element (diode) is set to be higher than that of the LDMOS. Therefore, the diode is also horizontal, and a high-voltage region of a certain size is set in the diode, similar to that of the LDMOS. In the technology described in Patent Document 1, the LDMOS is formed in a region on a plane, and the region constituting the diode surrounds the LDMOS.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2006-319072

[0006] As described above, in order to form an LDMOS and a lateral protection element on a common semiconductor substrate and to improve the voltage withstand capability of both, a large area is required in terms of the combined area of ​​the two. Alternatively, with limited area, it is not possible to increase the current flowing through the LDMOS or the protection element, thus reducing the protection function. Therefore, it is difficult to obtain a small semiconductor device with high voltage withstand capability that combines a switching element and a protection element that protects the switching element. Summary of the Invention

[0007] This disclosure was made in view of such problems, and its purpose is to provide a semiconductor device that solves the aforementioned problems.

[0008] To address the aforementioned issues, this disclosure has the following structure.

[0009] The semiconductor device disclosed herein comprises, on a semiconductor substrate, a switching element that is switched on and off between a first main electrode on a high-potential side and a second main electrode on a low-potential side by a control electrode potential; and a protection element that, when the switching element is off, allows current to bypass between the first electrode on the protection element side on the high-potential side and the second electrode on the protection element side on the low-potential side. The semiconductor device is characterized by comprising: a first semiconductor region of a second conductivity type opposite to a first conductivity type, formed on the surface side of the semiconductor substrate of the first conductivity type; a common electrode that serves as both the first main electrode and the first electrode on the protection element side; and a common contact region of the second conductivity type, locally formed with a high impurity concentration on the first semiconductor region and connected to the common electrode. In a top view, one region and another region in the circumferential direction centered on the common contact region are respectively designated as the switching element region where the switching element is formed and the protection element region where the protection element is formed. The protective element region of the component includes: a second semiconductor region of the first conductivity type, which is partially formed in the first semiconductor region radially separated from the common contact region when viewed from above; and a third semiconductor region of the second conductivity type, which is partially formed in the second semiconductor region when viewed from above. A second main electrode is connected to the third semiconductor region. A fourth semiconductor region of the first conductivity type is provided in the protective element region, which is partially formed in the first semiconductor region radially separated from the common contact region when viewed from above. A second electrode on the protective element side is connected to the fourth semiconductor region. The first semiconductor region is integrated throughout the switching element region and the protective element region. When viewed from above, the end of the second semiconductor region on the common contact region side is separated from the end of the fourth semiconductor region on the common contact region side.

[0010] Alternatively, the shortest distance between the common contact area in the protection element area and the fourth semiconductor area may be set to be shorter than the shortest distance between the common contact area in the switching element area and the second semiconductor area.

[0011] Alternatively, the semiconductor device may include a buried semiconductor region of the second conductivity type, which is formed on the common contact area side of the semiconductor substrate at a depth greater than that of the first semiconductor region and is connected to the first semiconductor region. The shortest distance from the common contact area to the second semiconductor region is equal to the shortest distance from the common contact area to the fourth semiconductor region. The shortest distance between the buried semiconductor region and the second semiconductor region in the switching element region is set to be shorter than the shortest distance between the buried semiconductor region and the fourth semiconductor region in the protection element region.

[0012] Alternatively, multiple field plates, made of conductive material and facing the surface of the first semiconductor region through an insulating layer, are formed such that they are capacitively coupled between the common electrode and the control electrode, and between the common electrode and the second electrode on the protection element side, and surround the common electrode when viewed from above.

[0013] Alternatively, the semiconductor device may include a fifth semiconductor region of the second conductivity type partially formed in the fourth semiconductor region, and the second electrode on the protection element side is connected to the fifth semiconductor region.

[0014] Alternatively, the shortest distance between the common contact area in the switching element area and the second semiconductor area, and the shortest distance between the common contact area in the protection element area and the fourth semiconductor area, can be set to be equal.

[0015] Alternatively, one of the second semiconductor region and the fourth semiconductor region may be formed inside the first semiconductor region when viewed from above.

[0016] Alternatively, when viewed from above, one of the second semiconductor region and the fourth semiconductor region may be connected to the semiconductor substrate on the radially outer side.

[0017] Alternatively, the second semiconductor region is formed inside the first semiconductor region when viewed from above, and the distance between the outermost radial periphery of the portion other than the portion of the first semiconductor region that is not directly in contact with the semiconductor substrate and the outermost radial periphery of the first semiconductor region is set as a length less than the distance between the second semiconductor region and the fourth semiconductor region in the circumferential direction.

[0018] Alternatively, when viewed from above, an inter-element field plate made of a conductor is formed on the surface of the first semiconductor region, which is partially separated from the second semiconductor region and the fourth semiconductor region in the circumferential direction, with an insulating layer between the second semiconductor region and the fourth semiconductor region.

[0019] Alternatively, the inter-element field plate may be connected to the second semiconductor region, the fourth semiconductor region, or the control electrode via a conductive material.

[0020] Because this disclosure is configured as described above, it is possible to obtain a small semiconductor device with high voltage resistance that combines a switching element and a protective element for protecting the switching element. Attached Figure Description

[0021] Figure 1 This is a circuit diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0022] Figure 2 This is a cross-sectional view of the switching element region side of a semiconductor device according to an embodiment of the present disclosure.

[0023] Figure 3 This is a cross-sectional view of the protective element region side of a semiconductor device according to an embodiment of the present disclosure.

[0024] Figure 4 This is a top view showing the structure (excluding the field plate) of a semiconductor device according to an embodiment of the present disclosure.

[0025] Figure 5 This is a cross-sectional view of an example in which the depth direction contours of the second semiconductor region and the fourth semiconductor region are different in a semiconductor device according to an embodiment of this disclosure.

[0026] Figure 6 This is a cross-sectional view of an example in which the structure of the first semiconductor region differs in the semiconductor device of the embodiments of this disclosure.

[0027] Figure 7 (a) is a top view showing the configuration of the field plate in a semiconductor device according to an embodiment of the present disclosure. Figure 7 (b) is a magnified view of its part.

[0028] Figure 8 This is a circuit diagram illustrating the structure of a first modified example of a semiconductor device according to an embodiment of the present disclosure.

[0029] Figure 9 This is a cross-sectional view of the protective element region side of a first modified example of a semiconductor device according to an embodiment of the present disclosure.

[0030] Figure 10 This is a top view of a semiconductor device according to an embodiment of the present disclosure, in which the first semiconductor region, the second semiconductor region, and the fourth semiconductor region are arranged in two different positional relationships.

[0031] Figure 11 This is a top view of a first variation of the semiconductor device according to an embodiment of the present disclosure, in which the first semiconductor region, the second semiconductor region, and the fourth semiconductor region are arranged in four different positional relationships.

[0032] Figure 12 This is a diagram showing the arrangement of the distances between layers in a semiconductor device according to an embodiment of the present disclosure when the potentials of the second semiconductor region and the fourth semiconductor region are different.

[0033] Figure 13This is a top view of an example of a structure in a semiconductor device according to an embodiment of the present disclosure that makes the protection element more susceptible to breakdown compared to the switching element.

[0034] Figure 14 This is a top view that partially illustrates the structure of a second variation of a semiconductor device according to an embodiment of the present disclosure.

[0035] Figure 15 This is a partial cross-sectional view of a second variation of a semiconductor device according to an embodiment of the present disclosure.

[0036] Figure 16 This is a plan view of the structure of another example (one of) the inter-element field plate in a second variation of the semiconductor device according to an embodiment of the present disclosure.

[0037] Figure 17 This is a plan view of another example (two) of the structure of the inter-element field plate in a second modification of the semiconductor device according to an embodiment of the present disclosure.

[0038] Figure 18 This is a circuit diagram illustrating the structure of a third variation of a semiconductor device according to an embodiment of the present disclosure.

[0039] Label Explanation

[0040] 1-4: Semiconductor devices;

[0041] 10: p-type substrate (semiconductor substrate);

[0042] 11: n layers (first semiconductor region);

[0043] 11A: n-layer (buried n-type layer: buried semiconductor region);

[0044] 12:n + Floor (public contact area);

[0045] 13: p-layer (second semiconductor region);

[0046] 14:n + Layer (third semiconductor region);

[0047] 15, 17: p + layer;

[0048] 16: p-layer (fourth semiconductor region);

[0049] 18:n + Layer (fifth semiconductor region);

[0050] 20: Interlayer insulation layer;

[0051] 21: Drain electrode (common electrode, first main electrode, first electrode on the protection element side);

[0052] 21A, 26A: Via routing;

[0053] 22: Source electrode (second main electrode);

[0054] 23: Back gate electrode (second control electrode);

[0055] 24: Gate oxide film;

[0056] 25, 35: Gate electrode (first control electrode);

[0057] 26: Anode electrode (second electrode on the protection element side);

[0058] 27: Emitter electrode (second electrode on the protection element side);

[0059] 30, 30A, 30B, 30C: Field plates;

[0060] 40: Inter-component field plate;

[0061] 81: n-layer (first semiconductor region);

[0062] 81A, 81B: n - layer;

[0063] AN: Anode (second electrode on the protection element side);

[0064] B: Base;

[0065] BG: Back gate (second control electrode);

[0066] C: Collector (first electrode on the protection element side);

[0067] CA: Cathode (first electrode on the protection element side);

[0068] D: Drain electrode (first main electrode: high potential side electrode);

[0069] E: Emitter: (Second electrode on the protection element side);

[0070] G: Gate (first control electrode);

[0071] R1: Switching element area;

[0072] R2: Protection element area;

[0073] R3: Connection area;

[0074] S: Source electrode (second main electrode: low potential side electrode);

[0075] T1: Component (switching component);

[0076] T2, T3, T4: Components (protective components). Detailed Implementation

[0077] The semiconductor device according to the embodiments of the present disclosure will be described below. Furthermore, in the following description of the drawings, the same or similar parts are labeled with the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the length ratios of various parts, etc., may differ from reality. Therefore, specific dimensions should be determined by referring to the following description. Additionally, the drawings naturally include parts with different dimensional relationships or ratios. Furthermore, the embodiments shown below exemplify a device for embodying the technical concept of the present disclosure; the technical concept of the present disclosure does not limit the shape, structure, arrangement, etc., of the constituent components to the following content. Various modifications can be made to the embodiments of the present invention in the claims. Furthermore, in this disclosure, terms such as "upper" and "lower" are used for ease of description, and even when disposed on a side surface, as long as they are substantially the same as the constituent elements of the present disclosure, they are still within the scope of the present disclosure. In addition, "upper" includes not only the case formed in contact with the object but also the case formed across other layers. Furthermore, in this disclosure, "connection" is not limited to direct connection. Even when some components such as resistors are connected in between, as long as the connection is substantially the same as the constituent elements of this disclosure, it falls within the scope of this disclosure.

[0078] Figure 1 This is a circuit diagram showing the structure of the semiconductor device 1. Here, an n-channel MOSFET (LDMOS) element (switching element) T1, which serves as a switching element, and a diode (pn diode) element (protection element) T2 are formed on a common semiconductor substrate. Here, an n-type layer (drift layer) connected to the drain (D: high-potential side electrode (first main electrode)) in element T1 and an n-type layer connected to the cathode (CA) in element T2 are shared. The source (S: low-potential side electrode (second main electrode)), gate (G: first control electrode), and their associated structures are the same as those of a conventional MOSFET. When the potential VS of the source (S) is, for example, set to ground potential (GND) and the potential VD of the drain (D) is set to a positive potential, the current between the drain (D) and the source (S) is controlled by the voltage VG of the gate (G).

[0079] At this time, the potential VBG of the body layer (BG) of element T1 (MOSFET) is sometimes equal to that of the source (S), but sometimes it is controlled independently of VS by applying a specified potential to the back gate electrode (second control electrode). Thus, the characteristics of element T1 can be adjusted.

[0080] Furthermore, component T2 is a pn-type diode, and its cathode (CA: the first electrode on the protection element side) is shared with the drain (D: the first main electrode) of component T1, thus the aforementioned VD is applied. Additionally, the potential of its anode (AN: the second electrode on the protection element side) is VAN, which is the same as VBG and close to ground potential. With the aforementioned VD and VAN potential settings, component T2 is normally cut off (reverse biased), but when VD increases, component T2 breaks down, allowing a large current to flow. Moreover, this characteristic can be fine-tuned using VAN, etc.

[0081] When a high voltage surge or other positive voltage is applied to the drain (D) side when component T1 is turned off, component T1 may break down. In this case, if component T2 breaks down first (bypassing current through component T2), the large current caused by the breakdown can be suppressed on the component T1 side, thus preventing damage to component T1 or the circuit connected to it.

[0082] Additionally, there are cases where VBG in component T1 and VAN in component T2 are shared (dashed line in the figure), and there are also cases where they are controlled separately. This can be easily achieved through wiring connections. Furthermore, as described later, it is also possible to achieve... Figure 1 Any element in VBG or VAN automatically becomes part of the GND structure.

[0083] Here, on the T1 side, the region on the plane of the semiconductor layer where the electric field strength increases when semiconductor device 1 is turned off is particularly the region between the gate (G) and drain (D) where the potential difference between their two ends increases. On the T2 side, the region where the electric field strength increases when semiconductor device 1 is turned off is the region between the cathode (CA) and anode (AN). Therefore, to achieve high withstand voltage, these regions need to be expanded along the electric field direction. Figure 1 In this semiconductor device 1, the drain (D) of element T1 and the cathode (CA) of element T2 are connected to a common terminal with a potential of VD. Furthermore, in this semiconductor device 1, a generally circular region in the semiconductor substrate is divided circumferentially into a portion for the operation of element T1 and a portion for the operation of element T2. Therefore, even when the breakdown voltage of elements T1 and T2 is set to a high level, the overall size of the semiconductor device 1 can be minimized.

[0084] Figure 2 This is a cross-sectional view of the region (switching element region) in the semiconductor device 1 where the element T1 is formed. Figure 3 This is a cross-sectional view of the area where component T2 is formed (the area protecting the component). Figure 4 This is a top view of the semiconductor device 1. Figure 2 yes Figure 4 A cross-sectional view along the AA direction. Figure 3This is a sectional view along the BB direction. Figure 2 , Figure 3 In this process, the semiconductor device 1 is formed on a p-type substrate (semiconductor substrate) 10 of p-type (first conductivity type). Figure 4 In this diagram, R1 is the switching element area, R2 is the protection element area, and R3 is the connection area that connects them.

[0085] exist Figure 2 , Figure 3 In the figure, on the surface side of the p-type substrate 10, an n-type (second conductivity type) n-layer (first semiconductor region) 11 is formed more extensively in the shape shown. Figure 1 Components T1 and T2 in the diagram are both formed using this n-layer 11. Figure 2 , Figure 3 In the middle, the right side of layer n11 is the low potential side (the side close to the ground potential), and the left side is the high potential side (e.g., above +600V).

[0086] exist Figure 2 In the (switching element region), a p-type p-layer (second semiconductor region) 13, which forms the body region of the MOSFET, is formed on the low-potential side (right side of the figure), and an n-type n-layer (first semiconductor region) 11 is formed on the higher-potential side. Furthermore, a higher-density and deeper n-type n-layer (buried n-type layer: buried semiconductor region) 11A is formed on the high-potential side of the n-layer 11. Similarly, in... Figure 3 In the (protection element region), on the low-potential side (right side of the figure), a p-layer 16 is also formed corresponding to the aforementioned p-layer 13, but its impurity concentration, depth, etc., do not need to be the same as those of p-layer 13. On the higher-potential side, a p-layer 16 is formed... Figure 2 Similarly, n layers 11 and n layers (buried n-type layers: buried semiconductor regions) 11A are formed. As described later, the switching element region ( Figure 2 In the nth layer 11 and nth layer 11A, respectively, the protection element area side ( Figure 3 The n-layer 11 and n-layer 11A are connected, but their impurity concentration and depth do not need to be consistent on the switching element area side and the protection element area side. They can be adjusted separately according to the characteristics of element T1 and element T2.

[0087] exist Figure 4 In this configuration, the overall shape of the n-layer 11A is circular (i.e., the same sector shape on both the switching element R1 side and the protection element region R2 side), but this shape does not need to be circular (the shapes on the switching element R1 side and the protection element region R2 side do not need to be the same). That is, the shape can be appropriately set according to the characteristics of the LDMOS and the specifications of the diodes. Not only the shape, but also the impurity concentration is the same. Furthermore, the impurity concentration of the n-layer 11 is also the same.

[0088] In addition, Figure 2 , Figure 3 In the middle, a high concentration of n-type layers, i.e., n, is formed on the surface of the left side (high potential side) of the n-layer 11. + Floor (public contact area) 12. (e.g.) Figure 4 As shown in the figures, n in these figures + Layer 12 is actually the same, in Figure 2 , Figure 3 The image shows cross-sections in different directions.

[0089] exist Figure 2 In the middle, n on layer 11 + Layer 12 as Figure 1 The contact layer at the drain (D) region of element T1 functions. On the other hand, a high concentration of n-type n-type electrons is present on the surface of p-layer 13. + Layer (third semiconductor region) 14, high concentration of p-type p + Layer 15 is formed on the left and right sides respectively. + Layer 15 is formed as a contact layer in contact with p-layer 13 (the second semiconductor region), thereby setting the potential of p-layer 13 to [value missing]. Figure 1 VBG in Chinese. + Layer 14 functions as the source (S) region of element T1, and its potential is set to... Figure 1 VS.

[0090] exist Figure 3 In the middle, n on layer 11 + Layer 12 as Figure 1 The contact layer at the cathode (CA) region of element T2 functions. That is, n + Layer 12 becomes used for... Figure 1 The common contact area connecting the drain (D) and cathode (CA) in the process. Figure 3 In the middle, on the surface of the p-type substrate 10 on the right side (low potential side), with Figure 2 The p-layer 13 in the middle is correspondingly formed with a p-type p-layer (fourth semiconductor region) 16 that contacts the n-layer 11. As will be described later, the p-layer 13 and p-layer 16 are actually separated in terms of device operation, but... Figure 2 , Figure 3 In this context, their potentials are all directly connected to the p-type substrate 10, therefore in Figure 1 In this context, VBG = VAN (=VS). Here, the potential of the p-type substrate 10 can be set to GND, for example.

[0091] A high concentration of p-type ... + Layer 17. Layer 16 functions as the anode layer of element T2, and its potential is set to... Figure 1The VAN. The p+ layer 17 is formed to contact the p layer 16, which serves as the anode layer.

[0092] exist Figure 2 , Figure 3 In this process, an interlayer insulating layer 20 composed of a silicon oxide film is formed on the semiconductor substrate having the above-described structure. Each wiring is connected to the above-described layers through an opening formed in the interlayer insulating layer 20, thereby realizing... Figure 1 The circuit structure. First, in n + Layer 12 connects to the drain electrode (common electrode) 21 of element T1. As mentioned above, the drain electrode 21 with potential VD in the figure also serves as the collector electrode of element T2. Figure 2 In n + Layer 14 is connected to a source electrode (second main electrode) 22 with a potential of VS, located to its right in the figure, at p + Layer 15 is connected to a back gate electrode (second control electrode) 23 with a potential of VBG. As described above, in this semiconductor device 1, independent control is achieved. Figure 1 VS, VBG, and VAN in the context of VAN.

[0093] Additionally, in n + Layer 14 and the surface of layer p 13 up to the portion where layer n 11 is exposed on its left side are grounded with a potential of [potential value missing]. Figure 1 The gate electrode (first control electrode) 25 of VG is formed. This structure creates a MOSFET, or device T1, that operates using the drain electrode 21, source electrode 22, and gate electrode 25 (and consequently, back gate electrode 23). In this MOSFET, when turned on, the p-layer 13 and the n-layer... + When a conducting current flows through the n layers 11 up to layer 12 and a high voltage is applied to the drain electrode 21 during the off state, at least a portion of the n layers 11 in this region is depleted.

[0094] In addition, Figure 2 In this process, a silicon oxide film thicker than the gate oxide film 24 is formed directly below the portion to the left of the gate electrode 25. This portion functions as the field plate 30, which will be described later.

[0095] On the other hand, Figure 3 In p + Layer 17 is connected to an anode electrode (second electrode on the protection element side) 26 with a potential of VAN. This forms... Figure 1 In normal use, in element T2, VAN becomes close to the ground potential, while the drain electrode 21, which serves as the cathode electrode, becomes a high potential, VD, as described above. Therefore, element T2 is in the off state. Consequently, element T2 has a relatively small impact on the operation of element T1.

[0096] In addition, the anode electrode 26 is connected to the field plate (field plate 30, described later) opposite the n-layer 11A on its left side through a silicon oxide film that is thicker than the gate oxide film 24.

[0097] exist Figure 2 In the middle, regarding the p layer 13 and n on the surface side + The n-layer 11 between layers 12 becomes a region where withstand voltage must be ensured (withstand voltage assurance region) due to the increased electric field strength in the depletion layer formed when component T1 is turned off. Here, to ensure withstand voltage, in the p-layer 13 and n-layer... + The surfaces of n-layers 11 and n-layers 11A between layers 12 are separated by a silicon oxide film thicker than the gate oxide film 24 described above, and multiple field plates 30 are arranged along the left-right direction in the figure (the direction in which the electric field distribution is generated during use). Figure 2 The cross-section is shown, but as described later, each field plate 30 concentrically surrounds n. + The layers are formed in the manner of layer 12 or drain electrode 21, thereby making the surface potential of the n layers 11 directly below each field plate 30 the same, and, regarding this surface potential, from Figure 2 The field plate 30 is capacitively coupled from the highest potential side (left side in the figure) to the lowest potential side (right side in the figure). This allows the field plates 30 to be appropriately distributed to avoid forming regions with locally high electric field strength. The function of such field plates 30 is as described, for example, in Japanese Patent No. 3275964. That is, this structure improves the withstand voltage in the withstand voltage assurance zone.

[0098] exist Figure 3 In the middle, the p layer 16 on the surface side and n + The n layers 11 between layers 12 also form a region where withstand voltage is ensured (withstand voltage assurance region) so as to increase the electric field strength formed in the depletion layer of element T2 when element T1 is turned off. Here, field plates 30 are also arranged in the same manner as described above, and their function is also the same. This will be described later. Figure 2 and Figure 3 The planar structure of the field plate 30 and its electrical connections.

[0099] Furthermore, the thicker silicon oxide film in the region forming the field plate 30 is actually formed as a LOCOS oxide film, for example. Therefore, the surface of the semiconductor layer (n-layer 11, etc.) in this region is actually located lower than the surface of the p-layer 13 directly below the gate electrode 25, and these surfaces are not on the same plane. Figure 2 In simplified terms, this is described as the surfaces of the semiconductor layers forming a single plane. The same applies to the sectional views described later.

[0100] exist Figure 4 The top view only records Figure 2 , Figure 3 The components shown include the p-type substrate 10, n-layer 11, n-layer 11A, and n-layer 11A, which are structures within the semiconductor layer. + Layer 12, p-layer 13, p-layer 16, n + Layer 14 and gate electrode 25. Alternatively, only layer n can be selected. + Layer 12 is a circular region centered on a semiconductor device 1, and different semiconductor devices are disposed on a p-type substrate 10 on its outer side. Layers 13 and 14 constitute element T1. + Layer 14 and gate electrode 25 are formed only in the lower switching element region R1 in the figure, and p-layer 16 constituting element T2 is formed only in the upper protection element region R2 in the figure. At this time, n-layer 11 is formed continuously from the lower half (switching element region R1) to the connection region R3 and the upper half (protection element region R2), but p-layer 13 is formed separately in the lower half (switching element region R1) and p-layer 16 is formed separately in the upper half (protection element region R2) of the figure, with the connection region R3 as the boundary. n-layer 11A is a circle centered on n+ layer 12, that is, n-layer 11A has the same planar shape and size on the switching element region R1 and protection element region R2 sides. However, as mentioned above, n-layer 11A can actually be set separately on the switching element region R1 side and the protection element region R2 side, and the planar shape of n-layer 11A does not need to be circular.

[0101] Furthermore, the current flowing in the nth layer 11 of component T1 is Figure 4 From n + The current flows from layer 12 in the region R1 below it, while the current flowing in layer 11 in element T2 is... Figure 4 From n + Layer 12 flows in the upper region R2. Therefore, it is possible to... Figure 1 The drain (D) of element T1 and the cathode (CA) of element T2 are jointly subjected to n. + Layer 12, and enables components T1 and T2 to operate independently, thereby achieving Figure 1 The circuit. At this time, Figure 4 The center side of the circle is the high potential side, and the outer periphery side is the low potential side.

[0102] Here, in the case where surge voltage is mixed into VD and becomes excessive at the cutoff time, in order to... Figure 1 In the process of protecting element T1 through element T2, it is necessary for element T2 to break down before element T1 breaks down in layer 11. Therefore, in the process of... Figure 2 , Figure 4 n on the T1 side of the component +Let the shortest distance between layer 12 and layer p13 be D11. Figure 3 , Figure 4 n on the T2 side of the component + When the shortest distance between layer 12 and p layer 16 is set to D21, setting D11 > D21 is valid.

[0103] Or, in the case of Figure 2 , Figure 4 The shortest distance between layer n 11A and layer p 13 on the component T1 side is set as D12. Figure 3 , Figure 4 In the component T2 side, the shortest distance between layer n 11A and layer p 16 is set to D22. When D11≈D21, setting D12<D22 is valid. Additionally, when D11-D12≈D21-D22, setting D12>D22 is valid. Alternatively, by making... Figure 2 The impurity concentration ratio of the n-layer 11A in the (switching element region) is... Figure 3 The n-layer 11A low voltage in the (protected component area) also allows component T2 to break down at a lower voltage than component T1. That is, through these settings, the breakdown voltages of components T1 and T2 can be fine-tuned. Furthermore, in Figure 3 For example, when D21 is kept constant, increasing D21-D22 will increase the withstand voltage of component T2, while decreasing D21-D22 will decrease the withstand voltage. When D21-D22 is kept constant and D22 is decreased (in... Figure 3 When the p-layer 16 is extended to the left, the breakdown voltage decreases. Furthermore, if the impurity concentration of the n-layer 11A is increased, the breakdown voltage of component T2 decreases. Thus, the breakdown voltage of component T2 can be appropriately adjusted.

[0104] Regarding the setting of the aforementioned distances (D11, etc.), when there are depths (distances from the surface) in components T1 and T2 where breakdown is particularly easy, these distances can be set accordingly. In particular, depending on the formation method of p-layers 13 and 16 (a combination of impurity diffusion and ion implantation), the depth direction profile of p-layers 13 and 16 may not always be... Figure 2 , 3 A simple shape like that, in this case, will produce such a situation. Figure 5 The depth direction profiles of layers 13 and 16 are... Figure 2 , 3 Cross-sectional views of structures formed by combining component T1 and component T2 under different conditions. Figure 5 In, n + Layer 12 is located in the center, with the right half connected to... Figure 2 The cross-section of the switching element region R1 corresponds to the left half of the cross-section. Figure 3 The cross-section of the protective element region R2 corresponds to, Figure 5With Pass Figure 4 The longitudinal section at the center corresponds to that.

[0105] In this structure, the p-layer 16 on the left is shaped to extend towards the n-layer 11A from the lower side of the surface. The p-layer 13 on the right is formed by adding a shallower p-layer on the surface side relative to the same shape (the dashed line in the p-layer 13 in the figure), thus making the surface side of this structure locally extend towards the center (n). + The shape and depth profile of the material extending from layer 12 are significantly different in layers 16 and 13. Specifically, in the left side of layer 16, the end point (most oriented towards n) that becomes the interior is different from the point PA that becomes the end point on its surface. + Point PB (the protruding end of layer 12) separates in the horizontal direction. On the other hand, in layer 13 on the right, point PC, which becomes the end on its surface, separates from the end (the part facing n) that becomes the interior. + The horizontal distance between points PD (the protruding ends of layer 12) is less than the distance between PA and PB.

[0106] exist Figure 4 The diagram shows the intervals D11, D21, D12, and D22 in the planar shape, but specifically... Figure 5 In the case of the structure shown in the figure, it is preferable to set D12 and D22 based on internal points PB and PD rather than surface points. That is, the shortest distance from point PD in layer p 13 to layer n 11A is set as D12, and the shortest distance from point PB in layer p 16 to layer n 11A is set as D22. Similarly, when D11≈D21, it is set as D12<D22, and when D11-D12≈D21-D22, it is set as D12>D22, etc., which is effective.

[0107] in addition, Figure 6 The structure of the n-layer (first semiconductor region) is shown. Figure 2 , Figure 3 In different situations, and Figure 5 The corresponding diagram. In this case, layer n (first semiconductor region) 81 is formed on n + On the p-layer 12 side, on the p-layer 13 and 16 sides, there are n layers with a lower impurity concentration than the n-layer 81. - Layers 81A and 81B. Furthermore, in this case, n - Layer 81A is formed to the outside of p layers 13 and 16, therefore p layers 13 and 16 are not directly connected to the p-type substrate 10. Therefore, in Figure 1 The VBG and VAN can be set independently. In this case, D11, D21, D15, and D25 can be obtained as shown in the diagram. Here, D15 is n +The shortest distance between layer 12 and layer n 81A on the component T1 side, D25 is n + The shortest distance between layer 12 and layer n 81B on the component T2 side.

[0108] In this case, when D11≈D21, by setting D15>D25, it is possible to make element T2 break down before element T1 in the same way as described above.

[0109] Next, a detailed description will be provided. Figure 2 and Figure 3 The planar structure of the field plate 30 in the middle. Figure 7 (a) is in relation to Figure 4 The planar structure of each field plate 30 was added to the same top view, and n was replaced. + The diagram shows layer 12 with an additional drain electrode 21. Figure 7 (b) is an enlarged view showing only the portion related to the three innermost field plates 30. As described above, the basic structure of the field plates 30 is the same as that described, for example, in Japanese Patent No. 3275964. Therefore, the multiple field plates 30 arranged in a concentric ring around the drain electrode (common electrode) 21 are configured to be radially separated from each other.

[0110] As described above, in the withstand voltage assurance region (the region where multiple field plates 30 are configured), the potential on the high-potential side (inner side) and the potential on the low-potential side (outer side) are radially distributed by capacitive coupling between adjacent field plates 30. At this time, the innermost field plate 30 is given the potential of the high-potential side (the potential of the drain electrode 21). Therefore, in Figure 2 , Figure 3 In the middle, the innermost (leftmost) field plate 30, when viewed from above, partially overlaps with the upper side of the interlayer insulating layer 20 of the drain electrode 21, and is connected to the drain electrode 21 through a via wiring 21A penetrating the interlayer insulating layer 20. This field plate 30 is capacitively coupled by being close to the field plate 20 adjacent to it on its right in the horizontal direction. Furthermore, all the field plates 30 on its right (low potential side) are identical.

[0111] However, even without via wiring 21A and with the drain electrode 21 insulated from the innermost field plate 30 by the interlayer insulating layer 20, and even with capacitive coupling between them and the field plate 30, the potential of the innermost field plate 30 can be determined in the same way. Figure 2 , Figure 3 , Figure 7In the original view, the drain electrode 21 overlaps with the innermost field plate 30 when viewed from above. However, in this case, they do not need to overlap when viewed from above. For example, the innermost field plate 30 can be formed close to the outer side of the drain electrode 21 to allow for capacitive coupling. That is, the positional relationship and connection between the innermost field plate and the drain electrode can be appropriately set according to the structure of the electrode or field plate. Furthermore, in Figure 2 (Switching element area R1) Figure 3 In the protection element area R2, the leftmost field plate 30 and drain electrode 21 are connected, but obviously this connection can also be made only in the switching area R1 and the element area R2.

[0112] like Figure 7 As shown in (b), the three outermost field plates 30 (low potential side) are concentric rings and are continuously formed to the switching element region R1, the protection element region R2 and the connection region R3 between them.

[0113] Regarding the potential assignment to the outermost (low-potential side) field plate 30, it can also be done as follows: Figure 3 As shown, it is the same as the high-potential side. Here, the outermost (rightmost) field plate 30 is connected to the cathode electrode 26, which overlaps when viewed from above, via via wiring 26A. On the other hand, in Figure 2 In this configuration, the gate electrode 25 extends towards the high-potential side (left side) and is positioned opposite the n-layer 11 across an oxide film thicker than the gate oxide film 24; this portion essentially forms the field plate 30. These structures can also be appropriately configured in the same way as the high-potential side.

[0114] However, in Figure 2 The potential of the rightmost field plate 30 in (switching element area R1) is VG. Figure 3 The potential of the rightmost field plate 30 in the (protection element area R2) is VAN. Although both are low potentials, VG ≠ VAN.

[0115] therefore, Figure 7 In (a), the three outermost field plates 30 are split into field plates 30A in the switching element region R1 and into field plates 30B in the protection element region R2. Thus, in the switching element region R1, VD and VG are appropriately distributed radially using field plates 30A and their innermost field plates 30 to adjust the surface potential of the n-layer 11; in the protection element region R2, VD and VAN are appropriately distributed radially using field plates 30B and their innermost field plates 30 to adjust the surface potential of the n-layer 11. In the connection region R3, field plates 30A and 30B are separated from each other, so the influence of the circumferential potential difference in this part is also small. Furthermore, the split field plates 30 become the outermost periphery, but their number may not be three. Additionally, in... Figure 7In this case, the field plate 30 is not configured on the connection area R3, but it is also possible to configure the field plate 30 on the connection area R3.

[0116] With the above structure, the field plate 30 can function in the same way as the field plate described in, for example, Japanese Patent No. 3275964, and the withstand voltage in the withstand voltage protection area of ​​the semiconductor device 1 can be improved.

[0117] In addition, Figure 4 In this process, p-layers 13 and 16 are completely separated. That is, they are separated radially inward (high potential side) to radially outward (low potential side) within the connection region R3. However, the operation of components T1 and T2 primarily occurs in… Figure 4 The process is performed radially inward compared to p-layers 13 and 16. Therefore, p-layers 13 and 16 can be separated only on the radially inward side (the side of the common contact area), or they can be connected on the radially outward side.

[0118] A variation of the semiconductor device 1 described above will be explained. Figure 8 This illustrates the structure of the semiconductor device 2. Figure 1 The corresponding circuit diagram. In this semiconductor device 2, instead of the aforementioned element T2 which is a diode, element T3, which is an npn transistor (bipolar transistor), is used as a protection element. Here, the collector (C: first electrode on the protection element side) of element T3 is shared with the drain (D) of element T1 instead of the cathode (CA) (potential VD), and the potential of the emitter (E: second electrode on the protection element side) is set to VISO instead of the anode (AN). VISO can be used as the potential of the outer periphery of the element, for example, as described later. However, the p-type layer that becomes its base (B) and the n-type layer that becomes its emitter (E) are actually short-circuited by wiring, so element T3 actually operates with two terminals. In semiconductor device 2, element T3 is normally in the off state, but if large external noise such as a surge is mixed into VD, element T3 conducts, which can suppress the surge applied to element T1. This operation is the same as the breakdown in the operation of a parasitic transistor. The characteristics such as the on-state voltage of element T3 can be described later by n + Fine adjustments can be made to the spacing between layer 18 and n layer 11, the impurity concentration of p layer 16 or n layer 11, or VISO, etc.

[0119] Figure 9 This is a cross-sectional view of component T3 in this case, compared with... Figure 3 Correspondingly, in this case, p layers 16 and p are also formed. + Layer 17. Here, layer 16 functions as the base (B) layer of component T3. + Layer 17 is its contact layer.

[0120] Here, an n-type anode with a potential of VISO is formed in p-layer 16. + Layer (fifth semiconductor region) 18, and the n + The emitter electrode 27 connected to layer 18 is also connected to p + Layer 17 connection, thus achieving Figure 8 The circuit structure.

[0121] To protect element T1 using element T3, it is preferable that element T3 conducts before element T1 or its connected circuitry is damaged. Such characteristics, such as the on-state voltage, can be adjusted by setting the impurity concentration of p-layer 16. At this time, by setting the distances (D11, D21) between n-layer 11 and p-layers 13, 16, and the distances (D12, D22) between n-layer 11A and p-layers 13, 16, it is effective to maintain a high withstand voltage while making breakdown in n-layer 11 more likely to occur on the element T3 side than on the element T1 side, similar to the case of semiconductor device 1 described above. At this time, it is also obviously possible to set n-layer 11 to be... Figure 5 , Figure 6 Same shape.

[0122] Figure 10 It is shown in having Figure 1 The diagram shows two planar shapes of the semiconductor device 1 with the circuit structure shown, where the positional relationship between the p-layer 13 and the p-type substrate 10 is changed. Figure 10 (a) is with Figure 4 In the same diagram, p-layer 13 (potential VBG) and p-layer 16 (potential VAN) are both connected to the p-type substrate 10 (VBG = VAN). Figure 10 In (b), the p layer 16 (VAN) is connected to the p-type substrate 10. Alternatively, the n layer 11 can be located between and separated from the p layer 13 (VBG) and the p-type substrate 10.

[0123] Figure 11 It is shown in having Figure 8 The diagram shows the planar shape of the semiconductor device 2 with the circuit structure shown, where the positional relationship between the p-layer 13 and the p-type substrate 10 is similarly changed. Figure 11 In (a), p-layer 13 (potential VBG) and p-layer 16 (potential VISO) are both connected to the p-type substrate 10 (VBG = VISO). Figure 11 In (b), p-layer 16 (potential VISO) is connected to p-type substrate 10, and p-layer 13 (potential VBG) is connected to p-type substrate 10. Figure 10 (b) is similarly separated. In Figure 11 In (c), p-layer 13 (potential VBG) is connected to p-type substrate 10, while p-layer 16 (potential VISO) is separable from p-type substrate 10. Figure 11 In (d), both p-layer 13 (VBG) and p-layer 16 (VISO) can be separated from the p-type substrate 10.

[0124] exist Figure 10 , Figure 11 In Figure 10 (a) and Figure 11 In addition to (a), the potential difference (the difference between VBG and VISO) between p-layer 13 and p-layer 16 varies depending on the setting, thus requiring a withstand voltage between p-layer 13 and p-layer 16. Figure 12 Based on this viewpoint Figure 11 A top view of the structure of (d). Here, the spacing between the p-type substrate 10 and the p-layer 13 is set to DA, the spacing between the p-type substrate 10 and the p-layer 16 is set to DB, and the spacing between the p-layer 13 and the p-layer 16 is set to DC. In the operation of this semiconductor device, since the potential of the p-type substrate 10 is, for example, GND, and the potentials of the p-layer 13 (VBG) and the p-layer 16 (VISO) are not limited to either positive or negative, it is preferable to set the spacing DC between the p-layer 13 and the p-layer 16 to: spacing DC ≥ spacing DA, spacing DC ≥ spacing DB. Such a requirement is... Figure 1 Semiconductor device 1 ( Figure 10 The same principle can be applied in this context as well.

[0125] To balance improving the withstand voltage related to the switching element region R1 and the protection element region R2, and to ensure that the breakdown or switching on the T2 and T3 sides of the protection element region R2 occurs earlier than the T1 side of the switching element region R1 as described above, it is preferable to set it to... Figure 13 The structure shown is a planar shape. Figure 13 In this diagram, the semiconductor device 2 is racetrack-shaped (a semi-circular portion separated vertically and connected by a straight line). Here, a diagram is shown... Figure 11 The structure corresponding to (a). In this structure, by ensuring that the connection area R3 sandwiched between the switching element area R1 and the protection element area R2 is more than... Figure 11 The length of the semiconductor device 2 in (a) results in a greater separation between the switching element region R1 and the protection element region R2. In this case, it is easier to make the p layer 13 and n + The distance D11 between layers 12 is greater than that between layers 16 and n. + The distance between layers 12 is D21. The same structure is found in semiconductor device 1 ( Figure 10 It can also be applied in ).

[0126] The foregoing has shown various planar structures that the constituent elements of semiconductor devices 1 and 2 can adopt. In contrast, in the semiconductor device 3 of the second variation described below, a new structure is added particularly to the surface. This semiconductor device 3 will now be described.

[0127] exist Figure 7 In region F (the portion corresponding to the connection region R3 sandwiched between p-layers 13 and 16 and adjacent to each other), when the semiconductor device 3 is turned off, the depletion layer extends from the interface between p-layer 13 and n-layer 11, and then from the interface between p-layer 16 and n-layer 11. When the depletion layers extending from both sides come into contact, conduction (through) occurs between p-layers 13 and 16.

[0128] Therefore, as Figure 13 Increasing the spacing between p-layer 13 and p-layer 16 (the length of the connection portion R3) in the same structure is effective, but the size of the semiconductor device will increase.

[0129] To suppress such penetration, in Figure 7 In region F, an inter-element field plate 40 is preferably disposed between p-layer 13 and p-layer 16, extending circumferentially. Figure 14 This is a top view showing the structure of such a semiconductor device 3; only the structure shown here is related to... Figure 7 Region F and its surrounding area.

[0130] exist Figure 14 The image shows a p-type substrate 10. Figure 7 The field plate 30, p-layer 13, p-layer 16, and inter-component field plate 40 are included. Additionally, Figure 15 It shows Figure 14 The cross-section along the HH direction. Figure 15 In the middle, the inter-element field plate 40 is similar to the above-mentioned field plate 30, and is opposite to the n layer 11 between the p layer 13 and the p layer 16, separated by an interlayer insulating layer 20 composed of a thick silicon oxide film.

[0131] like Figure 14 As shown, the inter-component field plate 40 is formed such that, when viewed from above, one end extends overlapping with p-layer 13, and the other end extends overlapping with p-layer 16. Furthermore, the inter-component field plate 40 is connected to either p-layer 13 (potential VBG) or p-layer 16 (potential VISO). Consequently, in the n-layer 11 between p-layer 13 and p-layer 16 directly below the inter-component field plate 40, the extension of the depletion layer is suppressed, thereby suppressing punch-through.

[0132] Alternatively, the inter-element field plate 40 can be connected to the gate electrode 25 (potential VG). In this case, it can also be configured to... Figure 4The circumferential end of the gate electrode 25 extends circumferentially and is connected to the inter-element field plate 40.

[0133] In addition, such as Figure 7 As shown, the outer field plate 30 is divided into field plate 30A in the switching element region R1 and field plate 30B in the protection element region R2. However, when an inter-element field plate 40 is provided, as... Figure 14 As shown, a field plate 30C, separated from the field plates 30A and 30B, can also be provided on the same circumference between the field plates 30A and 30B. The field plate 30C can also be capacitively coupled between the field plate 30 on its radially inner side and the inter-element field plate 40 on its radially outer side.

[0134] The planar shape of the inter-component field plate 40 only needs to contain a minimum of Figure 14 The shape of the inter-component field plate 40 shown can be appropriately set without affecting other electrodes (wiring), etc.

[0135] Figure 16 The overall planar shape of an example of a case where the inter-component field plate 40 is connected to the p-layer 13 side as described above is shown. A field plate is also formed on the p-layer 13 in the circumferential direction connecting the inter-component field plate 40. In this case, the electrical connection between the inter-component field plate 40 and the p-layer 13 can be made on the p-layer 13.

[0136] Figure 17 The diagram shows an example of an overall planar shape in which the inter-node field plate 40 and the gate electrode 35, which is also arranged circumferentially, are integrated as described above. In this case, if the silicon oxide film directly below the portion that will become the inter-node field plate 40 is a LOCOS oxide film and is formed to be thicker than the gate oxide film 24, this structure can be obtained simply by changing the pattern of the gate electrode 25. Furthermore, in Figure 16 , Figure 17 The description of the field plate 30 is omitted.

[0137] Furthermore, in the semiconductor device described above, the portions constituting the switching element region R1 and the protection element region R2 are shaped along an arc. However, they do not necessarily have to be shaped along an arc; they only need to be circumferentially oriented along the center (common contact area). Additionally, in the example above, the angles from the center for observing the switching element region and the angles for observing the protection element region (circumferential extension) are the same, but they do not need to be identical.

[0138] Furthermore, in the example above, multiple field plates 30 were used in the breakdown voltage assurance region. However, if breakdown voltage can be ensured even without such field plates, then field plates are not necessary in the breakdown voltage assurance region. In this case, the structure of the semiconductor device becomes simpler and cheaper. Alternatively, in the breakdown voltage assurance region, known resistive field plates or shallow trench isolation structures can be used instead of multiple field plates 30. This also applies to the inter-component field plates 40.

[0139] Alternatively, as a protection element, the same n-channel MOSFET (LDMOS) as element T1 can be used instead of the npn transistor. Figure 18 The structure of semiconductor device 4 as such a variation (third variation) is shown. The element (protection element) T4 used here is the same MOSFET as element T1, and as shown, its source (S), gate (G), and back gate (BG) are connected. For example, if... Figure 9 In the diagram where the field plate 30 on the far right is connected to the emitter electrode 27, the interlayer insulating layer 20 directly below it is a thinner gate oxide film 24. Figure 2 Then, by setting the field plate 30 as... Figure 18 The gate (G) of element T4 in the middle, and make it pass through the emitter electrode 27 and p + Layer 17, n + Layer 18 is connected, which makes this structure easy to achieve. In other structures, the protective element T4 can also be achieved by deforming the structure near the field plate.

[0140] In addition, in Figure 4 In the top view, the portions that form element T1 and elements T2 (to T4) are both semicircles (they are arc-shaped and occupy an angle of 180° when viewed from the center) and have the same area. However, their areas do not need to be the same; their areas are appropriately set according to the required element characteristics. For example, the area of ​​element T1 can be larger than the area of ​​element T2 (to T4). In this case, their areas can be changed, for example, by changing the aforementioned angle on the element T1 side and the element T2 side. Furthermore, in... Figure 4 In some cases, the parts that become element T1 and the parts that become element T2 are combined one by one in a single chip. However, in these planar structures, if the angle between the parts that become element T1 and the parts that become element T2 is less than 180°, it is also possible to arrange multiple combinations of them in the circumferential direction. In this case, it is also possible to alternately arrange the parts that become element T1 and the parts that become element T2 in the circumferential direction.

[0141] Furthermore, other layers can be added or removed appropriately within the semiconductor layer. Additionally, in the example above, the same structure can obviously be applied even if the p-type and n-type phases in the semiconductor are completely reversed.

Claims

1. A semiconductor device comprising: a switching element formed on a semiconductor substrate, wherein a switching element is switched on and off between a first main electrode on a high potential side and a second main electrode on a low potential side by a control electrode potential; and a protection element, wherein when the switching element is off, a current bypasses between the first electrode on the protection element side on the high potential side and the second electrode on the protection element side on the low potential side, characterized in that, The semiconductor device includes: A first semiconductor region of a second conductivity type opposite to the first conductivity type is formed on the surface side of the semiconductor substrate of the first conductivity type; The common electrode serves as both the first main electrode and the first electrode on the protection element side. as well as The second conductivity type common contact region is locally formed with a high impurity concentration on top of the first semiconductor region and is connected to the common electrode. Viewed from above, one region and another region in the circumferential direction centered on the common contact area are respectively designated as the switching element region where the switching element is formed and the protective element region where the protective element is formed. The following are provided in the switching element area: The second semiconductor region of the first conductivity type is locally formed at a portion that is radially separated from the common contact region in the first semiconductor region when viewed from above; and The third semiconductor region of the second conductivity type is locally formed within the second semiconductor region when viewed from above. The second main electrode is connected to the third semiconductor region. A fourth semiconductor region of the first conductivity type is disposed in the protective element region, and the fourth semiconductor region is locally formed at a portion radially separated from the common contact region in the first semiconductor region when viewed from above. The second electrode on the protection element side is connected to the fourth semiconductor region. The first semiconductor region is integrated across the switching element region and the protection element region. When viewed from above, the end of the second semiconductor region on the common contact area side is separated from the end of the fourth semiconductor region on the common contact area side.

2. The semiconductor device according to claim 1, characterized in that, The shortest distance between the common contact area in the protection element region and the fourth semiconductor region is set to be shorter than the shortest distance between the common contact area in the switching element region and the second semiconductor region.

3. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a buried semiconductor region of the second conductivity type, the buried semiconductor region being formed at a greater depth than the first semiconductor region on the common contact region side of the semiconductor substrate and connected to the first semiconductor region. The shortest distance from the common contact area to the second semiconductor area is equal to the shortest distance from the common contact area to the fourth semiconductor area, and the shortest distance between the embedded semiconductor area in the switching element area and the second semiconductor area is set to be shorter than the shortest distance between the embedded semiconductor area in the protection element area and the fourth semiconductor area.

4. The semiconductor device according to claim 1 or 2, characterized in that, A plurality of field plates, made of conductive material and facing the surface of the first semiconductor region through an insulating layer, are formed such that they are capacitively coupled between the common electrode and the control electrode, and between the common electrode and the second electrode on the protection element side, and are arranged to surround the common electrode when viewed from above.

5. The semiconductor device according to claim 1 or 2, characterized in that, The semiconductor device includes a fifth semiconductor region of the second conductivity type, which is partially formed in the fourth semiconductor region. The second electrode on the protective element side is connected to the fifth semiconductor region.

6. The semiconductor device according to claim 5, characterized in that, The shortest distance between the common contact area in the switching element area and the second semiconductor area, and the shortest distance between the common contact area in the protection element area and the fourth semiconductor area are set to be equal.

7. The semiconductor device according to claim 1 or 2, characterized in that, One of the second semiconductor region and the fourth semiconductor region is formed inside the first semiconductor region when viewed from above.

8. The semiconductor device according to claim 1 or 2, characterized in that, When viewed from above, one of the second semiconductor region and the fourth semiconductor region is connected to the semiconductor substrate on the radially outer side.

9. The semiconductor device according to claim 7, characterized in that, The second semiconductor region is formed inside the first semiconductor region when viewed from above. The distance between the outermost radial periphery of the portion other than the first semiconductor region that is not directly in contact with the semiconductor substrate and the outermost radial periphery of the first semiconductor region is set as a length less than the distance between the second semiconductor region and the fourth semiconductor region in the circumferential direction.

10. The semiconductor device according to claim 1 or 2, characterized in that, When viewed from above, on the surface of the first semiconductor region, which is partially separated in the circumferential direction from the second semiconductor region and the fourth semiconductor region, an inter-element field plate made of a conductor is formed on the surface of the first semiconductor region through an insulating layer.

11. The semiconductor device according to claim 10, characterized in that, The inter-element field plate is connected to the second semiconductor region, the fourth semiconductor region, or the control electrode via a conductive material.

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