Storage array and preparation method thereof, memory and electronic equipment

Abstract

The embodiment of the invention provides a storage array and a preparation method thereof, a memory and electronic equipment, and relates to the technical field of electronic equipment. The memory array includes a stacked structure, a plurality of channel layers, a spacer portion, and a support portion. The stacked structure comprises a plurality of stacked first electrode layers; the stacked structure is provided with an open groove, the open groove comprises an open hole and a plurality of sub-grooves, the open hole penetrates through the multiple first electrode layers, the sub-grooves are formed in the side wall of the open hole, and the sub-grooves and the first electrode layers are arranged on the same layer. And the channel layer is arranged on the inner wall of the sub-groove and is in contact with the first electrode layer. The spacing part is arranged in the sub-groove and at least arranged on the surface, away from the first electrode layer, of the channel layer. The supporting part is at least filled in the open hole, and the interval part is arranged between the supporting part and the channel layer. The material of the spacing part is different from that of the supporting part, and the hydrogen content of the spacing part is smaller than that of the supporting part. According to the embodiment of the invention, the damage to the channel layer in the storage array is reduced, and the electrical performance of the storage array is optimized.

Description

Storage arrays and their fabrication methods, memory, electronic devices Technical Field

[0001] This application relates to the field of electronic device technology, and in particular to a storage array and its fabrication method, a memory, and an electronic device. Background Technology

[0002] Memory, such as dynamic random access memory (DRAM), enables the storage and retrieval of data. To meet the demands for high-density storage, memory with a three-dimensional stacked structure (such as 3DDRAM) has been rapidly developed.

[0003] In some three-dimensional stacked memories, it is usually necessary to form multiple stacked channel layers and disconnect each channel layer from the others, thereby forming multiple stacked transistors.

[0004] However, if the channel layers are formed layer by layer, the fabrication cost of the memory will be high and the fabrication difficulty will be high. If multiple channel layers are formed at once and then the channel layers are disconnected from each other, it will cause great damage to the channel layers and affect the electrical performance of the memory. Summary of the Invention

[0005] This application provides a memory array and its fabrication method, a memory, and an electronic device. The purpose is to control the fabrication cost while reducing the damage to the channel layer in the memory array during the fabrication process, thereby improving the reliability of the transistor and optimizing the electrical performance of the memory array.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, a storage array is provided, which includes a stacked structure, multiple channel layers, spacers, and support sections.

[0008] The stacked structure includes multiple layers of first electrode layers stacked and spaced apart. The stacked structure has a slot, which includes an opening and multiple sub-slots. The opening penetrates through the multiple first electrode layers, and the sub-slots are disposed on the sidewalls of the opening, and are arranged in the same layer as the first electrode layers. A channel layer is disposed on the inner wall of the sub-slot and is in contact with the first electrode layers. A spacer portion is disposed in the sub-slot and is located on the side of the channel layer away from the inner wall of the sub-slot. A support portion at least fills the opening, and the spacer portion is disposed between the support portion and the channel layer. The spacer portion is made of a different material than the support portion, and the hydrogen content of the spacer portion is less than the hydrogen content of the support portion.

[0009] In the memory array provided in this application embodiment, by providing a spacer between the support and the channel layer, the easily damaged channel layer can be protected after the channel film is broken into multiple channel layers. This avoids the problem of the channel layer's electrical performance degrading due to direct contact between the support, which has a lower manufacturing cost but a higher hydrogen content, and the channel layer. For example, it avoids the problem of hydrogen atoms being injected into the channel layer after the support with a high hydrogen content comes into contact with the channel layer, leading to an increase in the carrier concentration of the channel layer and a degradation in electrical performance. In other words, this application embodiment can improve the electrical performance of the memory array while avoiding the use of a costly process of forming the channel layer layer by layer. It ensures that the memory array prepared by the low-cost process of forming a whole channel film in one step and then breaking it into multiple channel layers can still have relatively good electrical performance. That is, this application embodiment can balance the manufacturing cost and electrical performance of the memory array.

[0010] In one possible implementation of the first aspect, the spacer and the support are electrically insulating, and the material of the spacer includes one or more of GaO, GaZnO, ZnSiO, and ZnAlO.

[0011] These materials can have a low hydrogen content, and their precursors also have a low hydrogen content and weak reducibility, so that the spacer will not damage the channel layer during the preparation process while separating the channel layer and the support.

[0012] In one possible implementation of the first aspect, the material of the channel layer includes a metal oxide semiconductor material.

[0013] In one possible implementation of the first aspect, the material of the channel layer includes one or more of InGaZnO, InSnZnO, InSnGaZnO, InSnO, InGaO, InMgO, InWO and InAlZnO.

[0014] The channel layer material in the memory array provided in this application embodiment can be one of the aforementioned materials with excellent carrier mobility, thereby achieving excellent electrical performance of the memory array.

[0015] Metal oxide semiconductor materials such as indium gallium zinc oxide (IGaZn) have high carrier mobility, but these materials are sensitive to the external environment and are easily damaged during the fabrication process, leading to a decrease in the electrical performance of the channel layer and making it impossible to achieve high-quality mass production in industrial applications. In the memory array provided in this application, by setting a spacer, the channel layer and the support are separated, avoiding direct contact between the support and the channel layer, which would cause damage to the sensitive channel layer. This effectively improves the product yield of the memory array when high-performance materials such as IGaZn are used as the channel layer, and optimizes its mass production capability.

[0016] In one possible implementation of the first aspect, at least one metallic element in the material of the spacer is the same as the element in the material of the channel layer.

[0017] By setting at least one metal element in the material of the spacer to be the same as the element in the material of the channel layer, the probability of chemical reaction (e.g., displacement reaction) between the channel layer and the spacer can be further reduced, thereby further reducing damage to the channel layer and improving the electrical performance of the memory array.

[0018] In one possible implementation of the first aspect, the spacer covers at least the sidewall of the portion of the channel layer that contacts the first electrode layer, thereby ensuring that the portion of the channel layer that contacts the first electrode layer can be protected by the spacer, and at least ensuring that the critical portion of the channel layer that carries charge (the portion that contacts the first electrode layer) is not damaged.

[0019] In one possible implementation of the first aspect, the stacked structure further includes multiple dielectric layers, which are alternately stacked with multiple first electrode layers; an opening penetrates the multiple dielectric layers, and at least a portion of the dielectric layer is disposed between two adjacent sub-slots. The surface of the spacer portion facing the opening is recessed relative to the surface of the dielectric layer facing the opening; the support portion fills the opening and the portion of the sub-slot.

[0020] The recessed spacer can ensure that the effective part of the channel layer is separated from the support part, thus preventing damage to the channel layer. It can also prevent the part of the channel layer located on the medium layer from being blocked, thereby avoiding affecting the disconnection process between adjacent channel layers and ensuring that the adjacent channel layers are fully disconnected.

[0021] In one possible implementation of the first aspect, the stacked structure further includes multiple second electrode layers, which are alternately stacked with multiple first electrode layers, and the second electrode layers are electrically connected to the first electrode layers; an opening penetrates through the multiple second electrode layers, and at least a portion of the second electrode layer is disposed between two adjacent sub-slots. The surface of the spacer portion facing the opening is flush with or protrudes from the surface of the second electrode layer facing the opening; the support portion only fills the opening.

[0022] The support portion only fills the opening, that is, the spacer portion completely fills the sub-slot, which can protect all surfaces (i.e. the effective portion) of the channel layer and avoid the problem of reduced electrical performance of the channel layer due to contact between the support portion and the effective portion of the channel layer. In addition, the spacer portion completely fills the sub-slot, which can protect the channel layer from covering the inner wall of the sub-slot, thereby ensuring that the channel layer has sufficient area to face the gate and increase the channel transmission area.

[0023] Secondly, a method for fabricating a storage array is provided, the method comprising:

[0024] A stacked structure is formed, comprising multiple layers of first electrode layers stacked and spaced apart. A slot is formed in the stacked structure; the slot includes an opening and multiple sub-slots, the opening penetrating the multiple layers of first electrode layers, and the multiple sub-slots disposed on the sidewalls of the opening, and disposed in the same layer as the first electrode layers. Multiple channel layers and spacers are formed; the channel layers are disposed on the inner walls of the sub-slots and in contact with the first electrode layers; the spacers are disposed in the sub-slots and are at least disposed on the surface of the channel layers away from the first electrode layers. A support portion is formed, the support portion at least filling the opening, and the spacers are disposed between the support portion and the channel layers; wherein the material of the spacers is different from the material of the support portion, and the hydrogen content of the spacers is less than the hydrogen content of the support portion.

[0025] In the memory array prepared according to the embodiments of this application, the spacer is disposed between the channel layer and the support. The spacer protects the easily damaged channel layer, avoids physical damage to the channel layer during the preparation process, and avoids the problem of the channel layer's electrical performance degrading due to direct contact between the support with a large hydrogen content and the channel layer, thereby improving the electrical performance of the memory array.

[0026] In a possible implementation of the second aspect, forming multiple channel layers and spacers includes:

[0027] A semiconductor thin film is formed on the inner wall of a groove. A first insulating material is formed in the groove; the first insulating material covers the semiconductor thin film and fills at least a plurality of sub-grooves. The portions of the semiconductor thin film and the first insulating material located in the openings are removed to form a plurality of channel layers and spacers; the portions of the semiconductor thin film located in the sub-grooves serve as channel layers, and the portions of the first insulating material located in the sub-grooves serve as spacers.

[0028] In the method for fabricating a memory array provided in this application embodiment, by setting the spacer portion on the channel layer before fabricating the support portion, the channel layer is protected. This avoids damage to the channel layer caused by the use of a precursor with a high hydrogen content or a precursor with high reducibility in the fabrication process due to the aspect ratio of the aperture during the formation of the support portion. This improves the electrical performance of the fabricated memory array.

[0029] In a possible implementation of the second aspect, the reducibility of the precursor of the spacer portion is less than that of the precursor of the support portion, and the hydrogen content of the precursor of the spacer portion is less than that of the precursor of the support portion.

[0030] This application embodiment provides a spacer between the support and the channel layer, and the material of the spacer is a material with weak precursor reducing properties and low hydrogen content. This separates the channel layer from the support without affecting the electrical performance of the channel layer itself, thus preventing the precursor of the support from contacting the channel layer and causing damage to the channel layer during the fabrication of the support.

[0031] Thirdly, a memory is provided, comprising peripheral circuitry and a memory array provided in the embodiments of the first aspect. The memory array is electrically connected to the peripheral circuitry.

[0032] Fourthly, an electronic device is provided, comprising a bus and a memory provided in the embodiments of the third aspect. The memory is electrically connected to the bus.

[0033] The technical effects of the memory in the third aspect and the electronic devices in the fourth aspect can be seen in the technical effects of the memory array design in the first aspect, and will not be repeated here. Attached Figure Description

[0034] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0035] Figure 2 is a schematic diagram of a memory structure provided in an embodiment of this application;

[0036] Figure 3 is a schematic diagram of a storage array provided in an embodiment of this application;

[0037] Figure 4 is a cross-sectional view along section line A-A' in Figure 3;

[0038] Figure 5 shows another cross-sectional view along section line A-A' in Figure 3;

[0039] Figure 6 is a cross-sectional view along section line B-B' in Figure 3;

[0040] Figure 7 is an enlarged view of one of the structures corresponding to the dashed box D in Figure 4;

[0041] Figure 8 is an enlarged view of one of the structures corresponding to the dashed box E in Figure 6;

[0042] Figure 9 shows enlarged views of some other structures corresponding to the dashed box E in Figure 6;

[0043] Figures 10 and 11 are flowcharts illustrating the fabrication process of the storage array provided in the embodiments of this application;

[0044] Figures 12 to 26 are schematic diagrams of the structure of the storage array in each fabrication step. Detailed Implementation

[0045] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0046] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0047] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0048] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0049] Connection / linking: can refer to a mechanical or physical connection relationship, that is, A and B are connected or linked. It can mean that there are fastened components (such as screws, bolts, rivets, etc.) between A and B, or that A and B are in contact with each other and are difficult to separate. A and B can be fixed, detachable, or integrated; they can be directly connected or indirectly connected through an intermediate medium.

[0050] Coupling can be understood as direct coupling and / or indirect coupling. "Coupled connection" can be understood as a direct coupling connection and / or indirect coupling connection. Direct coupling, also known as "electrical connection," refers to components being in direct or indirect physical contact and electrically conductive. For example, in circuit construction, different components are connected through physical lines that can transmit electrical signals, such as copper foil or wires on a printed circuit board (PCB). "Indirect coupling" can be understood as two conductors conducting electricity through a gap or without contact. In one embodiment, indirect coupling can also be called capacitive coupling, for example, using the coupling between two conductive parts to form an equivalent capacitance to achieve signal transmission.

[0051] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0052] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0053] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0054] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0055] Furthermore, the scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0056] This application provides an electronic device, which can be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, radar, aerospace equipment, in-vehicle equipment, vehicles, and other different types of user equipment or terminal devices; the electronic device can also be a network device such as a base station. This application does not impose any special limitations on the specific form of the electronic device.

[0057] Figure 1 is a schematic diagram of the structure of an electronic device provided by an exemplary embodiment of this application.

[0058] For example, as shown in FIG1, the electronic device 1000 may include a bus 205 and a system on chip (SoC) 210 connected to the bus 205.

[0059] The system-on-chip 210 can be used to process data, such as processing application data, processing image data, and caching temporary data.

[0060] For example, the system-on-chip 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and on-chip memory 213 for caching high-speed data.

[0061] For example, the on-chip memory 213 may be static random access memory (SRAM) or embedded flash (eflash), etc.

[0062] For example, the application processor 211, the image processing unit 212 and the on-chip memory 213 described above can be integrated into a single die, or they can be disposed in multiple dies respectively.

[0063] For example, as shown in FIG1, the electronic device 1000 may also include an off-chip memory 220 connected to the system-on-chip 210 via a bus 205.

[0064] For example, the off-chip memory 220 may be dynamic random access memory (DRAM). The off-chip memory 220 may be used to store volatile data, such as temporary data generated by the on-chip system 210. The storage capacity of the off-chip memory 220 is typically larger than that of the on-chip memory 213, but its read speed is typically slower than that of the on-chip memory 213.

[0065] For example, the system-on-chip 210 and the off-chip memory 220 can be packaged in a single package structure, such as 2.5D or 3D packaging, to achieve faster inter-chip data transfer rates.

[0066] For example, as shown in FIG1, the electronic device 1000 may also include a communication chip 230 and a power management chip 240 connected to the system-on-a-chip 210 via a bus 205.

[0067] The communication chip 230 can be used for protocol stack processing, or for amplifying and filtering analog radio frequency signals, or simultaneously perform the above functions. The power management chip 240 can be used to supply power to other chips.

[0068] It is understood that the structure of the electronic device 1000 shown in FIG1 does not constitute a specific limitation on the electronic device 1000. The electronic device 1000 may include more or fewer components than those shown in FIG1, or may combine some of the components shown in FIG1, or may have a different arrangement of components than those shown in FIG1.

[0069] This application also provides a memory 100, which can be applied in the aforementioned electronic device 1000. For example, the memory 100 can be an on-chip memory 213 as shown in FIG1, or it can be an off-chip memory 220 as shown in FIG1. ​​This application does not limit the specific application scenario of the memory 100.

[0070] Figure 2 is a schematic diagram of the structure of the memory 100 provided in an embodiment of this application. As shown in Figure 2, the memory 100 includes a memory array 10 and peripheral circuitry 20.

[0071] The storage array 10 is connected to the peripheral circuit 20, which is used to control access to the storage array 10. For example, the peripheral circuit 20 can control the writing of data to the storage array 10 or control the reading of data from the storage array 10.

[0072] For example, the peripheral circuit 20 may include a word line selection circuit, a bit line selection circuit, a control circuit, and a read / write circuit, etc.

[0073] Referring to Figure 2, for example, the storage array 10 may include a plurality of array-distributed storage units G.

[0074] For example, when performing read and write operations on the memory array 10, the read and write circuit transmits control signals to the word line selection circuit and the bit line selection circuit through the control circuit. The word line selection circuit selects a column in the memory array 10, and the bit line selection circuit selects a row in the memory array 10. The word line selection circuit and the bit line selection circuit jointly determine the address of the memory cell G to be accessed.

[0075] For example, peripheral circuitry 20 may be disposed around memory array 10, for example, referring to FIG2, peripheral circuitry 20 is disposed on at least one side of memory array 10.

[0076] For example, the peripheral circuitry 20 may be stacked with the memory array 10, for instance, the memory array 10 may be stacked on top of the peripheral circuitry 20 (not shown in the figure).

[0077] This application also provides a storage array 10.

[0078] Figure 3 is a schematic diagram of a storage array 10 provided in an embodiment of this application. Figure 4 is a cross-sectional view along section line A-A' in Figure 3. Figure 5 is another cross-sectional view along section line A-A' in Figure 3. Figure 6 is a cross-sectional view along section line B-B' in Figure 3.

[0079] For example, the memory array 10 may include multiple transistors stacked in three dimensions. For instance, the memory array 10 may be a 3D DRAM with a vertical word line (VWL) architecture (see FIG3), or a 3D DRAM with a vertical bit line (VBL) architecture, or the memory array 10 may be a 1T1C structure (see FIG3, each memory cell G in the memory array 10 includes a transistor and a capacitor), or a 1TnC structure, or the memory array 10 may also be a resistive random access memory (RRAM or ReRAM). It is understood that any structure capable of constructing multiple transistors in vertical space is within the protection scope of the memory array 10 referred to in the embodiments of this application, and the embodiments of this application do not limit it.

[0080] In some embodiments, as shown in Figures 3, 4, 5 and 6, the storage array 10 includes a stacked structure 1, a plurality of channel layers 2, spacers 3 and support portions 4.

[0081] For example, referring to Figures 4, 5 and 6, the stacked structure 1, multiple channel layers 2, spacer portion 3 and support portion 4 can be disposed on the substrate N, which serves as a carrier structure for the fabrication of the aforementioned structures.

[0082] Referring to Figures 3, 4, 5 and 6, the stacked structure 1 includes multiple layers of first electrode layers 11 that are stacked and spaced apart.

[0083] Referring to Figures 3, 4, 5 and 6, the multilayer first electrode layer 11 is stacked along the third direction Z layer.

[0084] The first electrode layer 11 is used to form the electrodes of a transistor, for example, it can be used to form the source, drain or gate structure of a transistor.

[0085] Referring to Figures 3, 4, 5 and 6, the multilayer first electrode layer 11 is stacked so that the corresponding multiple transistors can be stacked in three dimensions, thereby increasing the storage capacity of the storage array 10.

[0086] Referring to Figures 3, 4, 5 and 6, the plurality of first electrode layers 11 are arranged at intervals. On the one hand, this facilitates the division between the plurality of transistors corresponding to the plurality of first electrode layers 11. On the other hand, the arrangement of the plurality of first electrode layers 11 at intervals facilitates the formation of sub-grooves K2 in the film layer where the first electrode layers 11 are located (refer to Figures 4, 5 and 6), thereby facilitating the formation of a plurality of independent channel layers 2 in the sub-grooves K2.

[0087] For example, the first electrode layer 11 is used to form at least one electrode of a transistor.

[0088] For example, referring to Figures 4 and 5, the first electrode layer 11 may include a first electrode 111 and a second electrode 112.

[0089] The first electrode 111 and the second electrode 112 are disposed at different positions in the same channel layer 2 so that when no channel is formed in the channel layer 2, the first electrode 111 and the second electrode 112 are insulated from each other through the channel layer 2, and when a channel is formed in the channel layer 2, the first electrode 111 and the second electrode 112 are connected to each other through the channel in the channel layer 2. That is, the first electrode 111 and the second electrode 112 can serve as the source and drain of a transistor, respectively.

[0090] For example, referring to FIG4, the multiple second electrodes 112 can be electrically connected, so that the same source signal or drain signal can be transmitted to multiple transistors simultaneously.

[0091] Alternatively, referring to FIG5, in the case where the memory array 10 includes transistors and capacitors C, the transistors and capacitors C can share the second electrode 112, that is, the second electrode 112 can be used as the source or drain of the transistor, or as an electrode plate of the capacitor C (e.g., as a memory node SN), and the different second electrodes 112 are disconnected from each other.

[0092] For example, referring to Figure 5, the first electrode layer 11 may also include a common electrode C1, which is used as another electrode plate of the capacitor C. The common electrodes C1 of multiple capacitors C can be electrically connected (e.g., they can be integrally formed). A dielectric layer C2 may be provided between the common electrode C1 and the second electrode 112.

[0093] For example, referring to Figure 6, the first electrode layer 11 may also include a third electrode 113.

[0094] The third electrode 113 is in contact with the channel layer 2 and is disposed between the first electrode 111 and the second electrode 112 (see Figure 3). The third electrode 113 can control the channel in the channel layer 2, thereby controlling the conduction or cutoff between the first electrode 111 and the second electrode 112. That is, the third electrode 113 is used as the gate structure of a transistor.

[0095] Referring to Figure 6, the third electrode 113 may include a gate 1A and a gate oxide layer 1B. The gate 1A is used to transmit gate control signals, and the gate oxide layer 1B is disposed between the gate 1A and the channel layer 2 to prevent the gate 1A and the channel layer 2 from being directly electrically connected.

[0096] For example, referring to Figures 4 and 5, the stacked structure 1 may further include multiple dielectric layers 121, which are stacked alternately with multiple first electrode layers 11 in sequence, so that adjacent first electrode layers 11 that need to be disconnected from each other can be electrically insulated by dielectric layers 121. For example, referring to Figures 4 and 5, dielectric layers 121 may be sandwiched between adjacent first electrodes 111, or referring to Figure 5, dielectric layers 121 may be sandwiched between adjacent second electrodes 112.

[0097] For example, referring to FIG6, the stacked structure 1 may further include multiple layers of second electrode layers 122, which may be stacked alternately with multiple layers of first electrode layers 11 in sequence, and the second electrode layers 122 are electrically connected to the first electrode layers 11. That is, two adjacent first electrode layers 11 that need to be electrically connected to each other can be electrically connected through the second electrode layers 122. For example, referring to FIG6, a second electrode layer 122 is sandwiched between adjacent third electrodes 113, so that the third electrodes 113 of multiple transistors can transmit the same gate signal at the same time.

[0098] For example, the third electrode 113 and the second electrode layer 122 can be integrally formed, and there may be no obvious boundary between them. The distinction between the two is merely for ease of description and in terms of their stacked positional relationship.

[0099] For example, the aforementioned dielectric layer 121 and the second electrode layer 122 can coexist and be located in the same film layer. For instance, the dielectric layer 121 can be sandwiched at a location where electrical insulation is required between adjacent first electrode layers 11, and the second electrode layer 122 can be sandwiched at a location where electrical connection is required. The second electrode layer 122 can be embedded in the dielectric layer 121.

[0100] Referring to Figures 4, 5 and 6, the stacked structure 1 is provided with a slot K, which includes an opening K1 and a plurality of sub-slots K2.

[0101] The slot K is used to penetrate the stacked structure 1 so that multiple channel layers 2 can be formed in the stacked structure 1 through the slot K, thereby forming multiple stacked transistors.

[0102] Referring to Figures 4, 5 and 6, the opening K1 is used to penetrate the multilayer first electrode layer 11, and multiple sub-slots K2 are disposed on the side wall of the opening K1. The sub-slots K2 are used to provide the channel layer 2.

[0103] Referring to Figures 4, 5 and 6, similar to the first electrode layer 11, two stacked and adjacent sub-slots K2 are spaced apart, so that the two channel layers 2 disposed in the two adjacent sub-slots K2 are spaced apart from each other, so as to realize independent control between the two adjacent transistors.

[0104] Referring to Figures 4, 5 and 6, the sub-slot K2 is disposed in the same layer as the first electrode layer 11. For example, at least a portion of the first electrode layer 11 is used as part of the inner wall of the sub-slot K2, thereby facilitating the contact between the channel layer 2 disposed in the sub-slot K2 and the first electrode layer 11.

[0105] For example, the slot K can be circular, square, elliptical, etc. This application embodiment does not limit this, and any slot K can penetrate through the multilayer first electrode layer 11, so that the shape of the slot K for setting multiple channel layers 2 is within the protection scope of this application embodiment.

[0106] Referring to Figures 4, 5 and 6, the channel layer 2 is disposed on the inner wall of the sub-slot K2 and is in contact with the first electrode layer 11.

[0107] For example, referring to Figures 4, 5 and 6, each sub-slot K2 is provided with a corresponding channel layer 2, which is provided at least on the inner wall of the sub-slot K2 away from the hole K1, so that the channel layer 2 is in contact with the first electrode layer 11.

[0108] The channel layer 2 is made of semiconductor material. It is used to achieve electrical insulation between the source and drain of the transistor when no channel is formed, that is, to turn off the transistor. The channel layer 2 is also used to form a channel under the control of the gate 1A, thereby achieving electrical conduction between the source and drain of the transistor, that is, to turn on the transistor.

[0109] For example, referring to Figure 3, when the first electrode layer 11 includes a first electrode 111, a second electrode 112, and a third electrode 113, a channel layer 2 can simultaneously contact the first electrode 111, the second electrode 112, and the third electrode 113, respectively. Under the control of the third electrode 113, a channel can be formed in the channel layer 2, thereby enabling conduction between the first electrode 111 and the second electrode 112, i.e., turning on the transistor.

[0110] For example, the material of the channel layer 2 may include at least one of the following: single-crystal silicon (Si), polycrystalline silicon (poly-Si), amorphous silicon (amorphous-Si), indium gallium zinc oxide (In-Ga-Zn-O, abbreviated as IGZO), single-crystal germanium (Ge), zinc oxide (ZnO), indium tin oxide (ITO), titanium dioxide (TiO2), molybdenum disulfide (MoS2), gallium arsenide (GaAs), indium phosphide (InP), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0111] For example, referring to Figures 3, 4, 5 and 6, the channel layer 2 can be a thin film, for example, the channel layer 2 is attached to the inner wall of the sub-slot K2. The thin film channel layer 2 is conducive to realizing the miniaturization design of the storage array 10.

[0112] For example, referring to Figures 4, 5 and 6, the multiple channel layers 2 are disconnected from each other and spaced apart so that multiple independent transistors can be formed accordingly.

[0113] For example, referring to Figures 4, 5 and 6, multiple sub-slots K2 are spaced apart on the sidewall of the opening K1, while the channel layer 2 is only set in the inner wall of the sub-slots K2 and not on the sidewall of the opening K1, so that adjacent channel layers 2 can be spaced apart and independent of each other.

[0114] For example, referring to FIG3, the channel layer 2 can be annular, such as a square annular as shown in FIG3, or it can also be a circular annular, elliptical annular or other annular.

[0115] The annular channel layer 2 facilitates simultaneous contact between the channel layer 2 and the first electrode 111, the second electrode 112, and the third electrode 113, and achieves mutual spacing between the first electrode 111, the second electrode 112, and the third electrode 113. For example, referring to Figure 3, the first electrode 111, the second electrode 112, and the third electrode 113 can be respectively disposed on different sides of the annular channel layer 2 (for example, in Figure 3, the first electrode 111 is disposed on the left side of the channel layer 2), thereby achieving mutual spacing between the three. In addition, the annular channel layer 2 can also reduce the fabrication difficulty of the memory array 10. For example, by opening the slot K, a multilayer channel layer 2 that is separated from each other can be fabricated.

[0116] It is understood that in other embodiments, the channel layer 2 may be of other shapes, and the relative positions between the channel layer 2 and the first electrode 111, the second electrode 112 and the third electrode 113 may be other arrangements. For example, the channel layer 2 may be "U" shaped, and the third electrode 113 may be disposed on the inner or outer side of the channel layer 2. The embodiments of this application do not limit these features.

[0117] Referring to Figures 4, 5 and 6, the support portion 4 is at least filled in the opening K1.

[0118] After the multilayer channel layer 2 in the form of a thin film is formed by the slot K, the slot K is still in the open state. The support part 4 is used to fill the slot K so as to support the storage array 10 and improve the structural stability of the storage array 10.

[0119] For example, the material of the support portion 4 is electrically insulating. For instance, the material of the support portion 4 may include one or more of SiO, SiN, SiOC, Al2O3, HfO2, and HfAlO.

[0120] For example, the material of the support portion 4 can be an amorphous structure.

[0121] Referring to Figures 4, 5 and 6, the spacer 3 is disposed in the sub-slot K2 and is disposed at least on the surface of the channel layer 2 away from the first electrode layer 11, such that the spacer 3 is disposed between the support 4 and the channel layer 2, thereby avoiding direct contact between the channel layer 2 (especially the surface of the channel layer 2 away from the first electrode layer 11) and the support 4.

[0122] For example, referring to FIG3, when the channel layer 2 is arranged in a ring, the spacer 3 can also be arranged in a ring inside the ring of the channel layer 2, and the support 4 fills the side of the spacer 3 away from the channel layer 2, thereby ensuring that the spacer 3 can completely separate the channel layer 2 and the support 4.

[0123] For example, referring to Figures 4, 5 and 6, the channel layer 2 is disposed on the inner wall of the sub-slot K2, and the spacer 3 can be filled in the sub-slot K2, so that the spacer 3 can cover the surface of the channel layer 2 and form protection for the channel layer 2.

[0124] Referring to Figure 4, it can be understood that each sub-slot K2 has a corresponding spacer 3, so that the channel layer 2 in each sub-slot K2 can be covered by the spacer 3.

[0125] For example, the spacer 3 also has electrical insulation properties, so that it can protect the channel layer 2 while avoiding affecting the channel transmission in the channel layer 2.

[0126] The material of the spacer 3 is different from that of the support 4, and the hydrogen content of the spacer 3 is less than that of the support 4.

[0127] For example, the material of the spacer 3 may include one or more of GaO, GaZnO, ZnSiO, and ZnAlO.

[0128] For example, the material of the spacer 3 can be an amorphous structure.

[0129] In some other embodiments, in order to achieve the three-dimensional stacking of multiple transistors, a Si and GeSi layer stacking method is used to prepare and form channel layers layer by layer. However, although the method of preparing channel layers layer by layer can achieve the mutual disconnection between multiple channel layers, the process is complex and the preparation cost is high.

[0130] To reduce manufacturing costs, in some embodiments, a low-cost stacked structure is used, and holes are made in the stacked structure. Then, a whole layer of channel film is formed in the holes at once, and then the whole layer of channel film is broken into multiple channel layers to achieve three-dimensional stacking of multiple transistors. However, the electrical performance of the memory array obtained by this manufacturing process is poor, such as leading to increased leakage current and reduced reliability of the memory array.

[0131] In the three-dimensional stacked memory array 10, the depth-to-width ratio of the opening K1 is high. In order to ensure that the support 4 can be fully filled in the opening K1 with a high depth-to-width ratio, the process of forming the support 4 is more limited compared to the process in the planar memory array. As a result, the hydrogen content in the support 4 used to fill the slot K (e.g., opening K1) is high. In addition, since the memory array 10 is three-dimensionally stacked, even if processes such as annealing are used, the hydrogen in the support 4 cannot be completely removed, which also results in a high hydrogen content in the support 4.

[0132] In the memory array 10 provided in this application embodiment, by providing a spacer 3 between the support portion 4 and the channel layer 2, the easily damaged channel layer 2 can be protected by the spacer 3 after the channel film is broken into multiple channel layers 2. This avoids the problem of the channel layer 2's electrical performance degrading due to direct contact between the support portion 4, which has a lower manufacturing cost but a higher hydrogen content, and the channel layer 2. For example, it avoids the problem of hydrogen atoms being injected into the channel layer 2 after the support portion 4 with a higher hydrogen content comes into contact with the channel layer 2, which would lead to the degradation of the carrier transport performance of the channel layer 2. In other words, this application embodiment can improve the electrical performance of the memory array 10 while avoiding a significant increase in manufacturing cost. It ensures that the memory array 10 prepared by the low-cost manufacturing process of forming a whole channel film in one step and then breaking it into multiple channel layers 2 can still have relatively good reliability. That is, this application embodiment can balance the manufacturing cost and electrical performance of the memory array 10.

[0133] In some embodiments, the reducibility of the precursor of the spacer portion 3 is less than that of the precursor of the support portion 4, and the hydrogen content of the precursor of the spacer portion 3 is less than that of the precursor of the support portion 4.

[0134] That is, the material of the spacer 3 provided in the embodiments of this application has the following characteristics: the precursor has weak reducing properties and low hydrogen content (compared to the support 4).

[0135] For example, the material of the spacer 3 can be gallium oxide. The precursor of gallium oxide must contain gallium atoms. Gallium atoms have relatively stable properties, so the reducibility of its precursor can be low. Therefore, when the spacer 3 is fabricated on the channel layer 2, the precursor of the spacer 3 will not react chemically with the channel layer 2 and will not cause damage to the channel layer 2.

[0136] It is understood that the embodiments of this application only use gallium oxide as an example to illustrate the material of the spacer 3, and are not intended to limit its formation. Any other material with low reducibility and low hydrogen content in the precursor (relative to the support 4) is within the protection scope of the embodiments of this application.

[0137] The material used for the support portion 4 used to fill the slot K has poor stability (e.g., silicon oxide). Due to the limited stability of the elements required for the support portion 4 material, the reducing power of the precursor of the support portion 4 cannot be minimized. When the support portion 4 and the channel layer 2 are in direct contact, the precursor of the support portion 4 with high reducing power is prone to chemical reaction with the channel layer 2 during the fabrication of the support portion 4 on the channel layer 2, such as a displacement reaction, which seriously affects the electrical performance of the channel layer 2. In this embodiment, by setting a spacer portion 3 between the support portion 4 and the channel layer 2, and the material of the spacer portion 3 is a material with weak reducing power and low hydrogen content, the spacer portion 3 itself does not affect the electrical performance of the channel layer 2, while separating the channel layer 2 from the support portion 4, thus avoiding damage to the channel layer 2 caused by the precursor of the support portion 4 contacting the channel layer 2 during the fabrication of the support portion 4.

[0138] Similarly, the precursor of the spacer 3 has a low hydrogen content. During the preparation of the spacer 3, the precursor of the spacer 3 will not damage the channel layer 2. During the preparation of the support 4, the spacer 3 protects the channel layer 2, which can prevent the precursor of the support 4, whose hydrogen content cannot be reduced, from directly contacting the channel layer 2 and causing damage to the channel layer 2.

[0139] In some embodiments, the material of the channel layer 2 includes a metal oxide semiconductor material.

[0140] For example, the material of the channel layer 2 includes one or more of In2O3, GaO, ZnO, InGaZnO, InSnZnO, InSnGaZnO, InSnO, InGaO, InMgO, InWO and InAlZnO.

[0141] That is, the material of the channel layer 2 in the memory array 10 provided in this application embodiment can be a material with excellent carrier mobility, such as indium gallium zinc oxide, thereby effectively improving the electrical performance of the memory array 10.

[0142] Materials such as indium gallium zinc oxide (IGNOO) have high carrier mobility, but they are sensitive to the external environment and are easily damaged during fabrication, leading to a decrease in the electrical performance of the channel layer 2 and resulting in yield problems, making it impossible to achieve high-quality mass production in industrial applications. In the memory array 10 provided in this application embodiment, the channel layer 2 and the support portion 4 are separated by the spacer portion 3, avoiding direct contact between the support portion 4 and the channel layer 2, which could damage the sensitive channel layer 2. For example, it prevents the hydrogen-rich precursor of the support portion 4 from being injected into the channel layer 2 during the fabrication of the support portion 4, or the strong reducing properties of the support portion 4 from reacting chemically with the channel layer 2, or the residual hydrogen in the support portion 4 from invading the channel layer 2 after fabrication. This provides a high-quality fabrication space for the channel layer 2, thereby effectively improving the product yield of the memory array 10 when using high-performance materials such as IGNOO as the channel layer 2 and optimizing its mass production capability.

[0143] For example, the material of the channel layer 2 can be an amorphous structure.

[0144] In some embodiments, the metal element in the material of the spacer 3 may be different from the metal element in the material of the channel layer 2. For example, the channel layer 2 may be In2O3, and the spacer 3 may be insulating GaO.

[0145] Alternatively, in some embodiments, at least one metal element in the material of the spacer 3 is the same as the element in the material of the channel layer 2.

[0146] For example, if the material of the channel layer 2 is InGaZnO, the material of the spacer 3 can be GaO or GaZnO.

[0147] By setting at least one metal element in the material of the spacer 3 to be the same as the element in the material of the channel layer 2, the probability of a chemical reaction (e.g., a displacement reaction) between the channel layer 2 and the spacer 3 can be further reduced, thereby further reducing damage to the channel layer 2 and improving the electrical performance of the memory array 10.

[0148] The filling position of the aforementioned interval 3 can be designed differently according to different application scenarios. The following are examples of possible filling positions of the interval 3.

[0149] Figure 7 is a magnified view of a part corresponding to the dashed box D in Figure 4, and Figure 8 is a magnified view of a part corresponding to the dashed box E in Figure 6.

[0150] In some embodiments, as shown in Figures 7 and 8, the spacer 3 covers at least the sidewall of the portion of the channel layer 2 that contacts the first electrode layer 11.

[0151] That is, referring to Figure 7, the channel layer 2 extends in the third direction Z and is in contact with the first electrode layer 11 on one side and with the spacer 3 on the other side, thereby ensuring that the part of the channel layer 2 in contact with the first electrode layer 11 can be protected by the spacer 3, and at least ensuring that the key part of the channel layer 2 that carries out charge carrier transport (the part in contact with the first electrode layer 11) will not be damaged.

[0152] For example, as shown in FIG7, the spacer 3 may be provided only on the surface of the channel layer 2 away from the first electrode layer 11.

[0153] For example, referring to FIG7, when the stacked structure 1 further includes multiple dielectric layers 121, the opening K1 penetrates through the multiple dielectric layers 121, and at least a portion of the dielectric layer 121 is disposed between two adjacent sub-slots K2, that is, the surfaces of two adjacent dielectric layers 121 and the surface of the first electrode layer 11 sandwiched therebetween form a sub-slot K2. In this case, the channel layer 2 includes a portion disposed on the first electrode layer 11 and a portion disposed on the opposing surfaces of the two dielectric layers 121, and only the portion of the channel layer 2 disposed on the first electrode layer 11 is an effective portion (channel transmission is performed).

[0154] By making the spacer 3 only provided on the surface of the channel layer 2 away from the first electrode layer 11, that is, referring to FIG7, the surface of the spacer 3 facing the opening K1 is recessed relative to the surface of the dielectric layer 121 facing the opening K1. At this time, the support 4 fills the opening K1 and the portion of the sub-slot K2 (the portion of the sub-slot K2 near the opening K1). The recessed spacer 3 can ensure that the spacer 3 can separate the effective portion of the channel layer 2 from the support 4, avoiding damage to the channel layer 2, and also avoid blocking the portion of the channel layer 2 located on the dielectric layer 121, thereby avoiding affecting the disconnection process between the two adjacent channel layers 2 and ensuring that the two adjacent channel layers 2 are fully disconnected.

[0155] Alternatively, as exemplarily shown in FIG8, the spacer 3 may be provided on all surfaces of the channel layer 2 away from the inner wall of the sub-slot K2.

[0156] For example, referring to Figure 8, when the stacked structure 1 further includes multiple layers of second electrode layers 122, the opening K1 penetrates through the multiple layers of second electrode layers 122, and at least a portion of the second electrode layers 122 is disposed between two adjacent sub-slots K2. That is, the surfaces of two adjacent layers of second electrode layers 122 and the surface of the first electrode layer 11 sandwiched between them form a sub-slot K2. In this case, the channel layer 2 includes a portion disposed on the first electrode layer 11 and a portion disposed on the opposing surfaces of the two layers of second electrode layers 122. Since both the first electrode layer 11 and the second electrode layer 122 need to transmit electrical signals, the portion of the channel layer 2 disposed on the first electrode layer 11 and the portion disposed on the second electrode layer 122 are both effective portions. For example, the first electrode layer 11 and the second electrode layer 122 can be integrally disposed as the gate structure of a transistor. In this case, the portions of the channel layer 2 located on the first electrode layer 11 and the second electrode layer 122 both serve as transmission channels.

[0157] By providing spacer portions 3 on all surfaces of the channel layer 2 away from the inner wall of the sub-slot K2, i.e., spacer portions 3 completely fill the sub-slot K2, for example, referring to FIG8, the surface of spacer portion 3 facing the opening K1 is flush with the surface of the second electrode layer 122 facing the opening K1, or referring to FIG6, the surface of spacer portion 3 facing the opening K1 protrudes beyond the surface of the second electrode layer 122 facing the opening K1. In this case, support portion 4 only fills the opening K1, and spacer portion 3 completely fills the sub-slot K2, thereby protecting all surfaces (i.e., the effective portion) of the channel layer 2 and preventing the support portion 4 from contacting the effective portion of the channel layer 2, which would lead to a decrease in the electrical performance of the channel layer 2.

[0158] Figure 9 shows some other enlarged views of the area corresponding to the dashed box E in Figure 6.

[0159] It is understood that the foregoing embodiments of this application are merely illustrative of the filling position and degree of the spacer 3, and are not intended to limit it. For example, referring to FIG9, the surface of the spacer 3 facing the opening K1 may be recessed, may protrude from the sub-groove K2, or may be recessed in the sub-groove K2. Similarly, referring to FIG9, the channel layer 2 may cover all the inner walls of the sub-groove K2, or may be recessed in the sub-groove K2. The embodiments of this application do not limit it.

[0160] This application embodiment also provides a method for fabricating a storage array 10. Figures 10 and 11 are some fabrication flowcharts of the storage array 10 provided in this application embodiment, and Figures 12 to 26 are structural schematic diagrams corresponding to each fabrication step of the storage array 10.

[0161] Each of Figures 12 to 26 includes a top view (i.e., a view in the XY direction) of the storage array 10 in the corresponding step, a cross-sectional view along section line C-C' in the top view, and a cross-sectional view along section line D-D' in the top view.

[0162] As shown in Figure 10, the preparation method includes the following steps S1 to S4.

[0163] S1: Refer to Figures 12 to 19 to form a stacked structure 1.

[0164] Referring to Figure 19, the stacked structure 1 may include multiple layers of first electrode layers 11 that are stacked and spaced apart.

[0165] It is understood that the embodiments of this application use the example of the first electrode layer 11 including the first electrode 11, the second electrode 12 and the third electrode 13 to illustrate the structure of the stacked structure 1.

[0166] For example, referring to Figures 12 to 19, step S1 may include the following steps S11 to S18:

[0167] S11: An initial stacked structure P is formed on the substrate N.

[0168] Referring to Figure 12, the initial stacked structure P includes a first functional layer P1 and a second functional layer P2. Both the first functional layer P1 and the second functional layer P2 can be insulating materials, for example, the first functional layer P1 can be silicon oxide and the second functional layer P2 can be silicon nitride. Alternatively, the first functional layer P1 and the second functional layer P2 can be a stack of insulating materials and semiconductor materials, for example, the first functional layer P1 can be silicon oxide and the second functional layer P2 can be polycrystalline silicon.

[0169] S12: Create the first slot U1 on the initial stacked structure P.

[0170] Referring to Figure 13, the first slot U1 is used to expose the multiple first functional layers P1 and multiple second functional layers P2 in the initial stacked structure P, so as to facilitate the subsequent formation of the first electrode 111.

[0171] For example, the area where the first electrode 111 needs to be set can be defined by photolithography, and then a deep hole can be formed by etching. Subsequently, a portion of the second functional layer P2 can be etched laterally by selective etching to form the first groove U1.

[0172] S13: Fill the first slot U1 with conductive material to form the first electrode 111.

[0173] For example, referring to FIG14, a first electrode 111 replaces at least a portion of the second functional layer P2, thereby causing a plurality of first electrodes 111 to be stacked.

[0174] For example, step S13 may include: first filling the first slot U1 with conductive material, then removing the conductive material located in the deep hole, leaving only the conductive material sandwiched between the first functional layers P1, and then filling the deep hole with insulating part P3, thereby forming a plurality of mutually insulated first electrodes 111.

[0175] For example, the material of the first electrode 111 may include metallic materials such as W, Ru, Ti, and Ta, or alloy materials such as NiPt, or conductive oxides or nitrides such as InSnO, TiN, and TaN. The material of the first electrode 111 may also be a double layer or a multilayer stack of the above materials, such as TiN / W, InSnO / W, etc.

[0176] For example, the material of the insulating part P3 may include various insulating oxides, nitrides, carbon oxides, such as SiO, SiN, SiOC, AlO, etc., or other electrically insulating materials and their stacks.

[0177] S14: Create a second slot U2 on the initial stacked structure P.

[0178] Referring to Figure 15, the second slot U2 is used to expose the multiple first functional layers P1 and multiple second functional layers P2 in the initial stacked structure P, so as to facilitate the subsequent formation of the second electrode 112 (or capacitor C).

[0179] For example, the area where the second electrode 112 needs to be set can be defined by photolithography, and then a deep hole can be formed by etching. Subsequently, a portion of the second functional layer P2 can be etched laterally by selective etching to form the second groove U2.

[0180] S15: Referring to Figure 16, a conductive material is filled into the second slot U2 to form a second electrode 112. Referring to Figure 16, the second electrode 112 can serve as a plate of a capacitor C.

[0181] For example, the material of the second electrode 112 can be the same as that of the first electrode 111, and will not be described again here.

[0182] For example, in the fabrication method corresponding to the storage array 10 in FIG4, the conductive material completely fills the second slot U2 so that multiple second electrodes 112 can be integrally set and electrically connected to each other.

[0183] Alternatively, referring to FIG16, in the case where the second electrode 112 is also used as another plate of capacitor C, the preparation process of the second electrode 112 refers to the preparation process of the first electrode 111, that is, the multiple second electrodes 112 are disconnected from each other.

[0184] In this embodiment, referring to FIG17, the preparation method may further include:

[0185] S16: Referring to Figure 17, form dielectric layer C2 and common electrode C1 to form complete capacitor C.

[0186] The material of dielectric layer C2 can include materials with high density and high dielectric constant, such as HfOx, ZrAlO, HfAlO, or other materials suitable for capacitor dielectric layers. The material of common electrode C1 can refer to the first electrode 111, and will not be described again here.

[0187] S17: Create a third slot U3 on the initial stacked structure P.

[0188] For example, the area where the third electrode 113 needs to be set can be defined by photolithography, and then a deep hole can be formed by etching. Subsequently, a portion of the first functional layer P1 can be etched laterally by selective etching to form the first slot U1. Referring to Figure 18, the third slot U3 is set alternately with the first slot U1 and the second slot U2 to avoid unexpected electrical connections between the conductive structures formed inside the three slots.

[0189] S18: A third electrode 113 is formed in the third slot U3.

[0190] Referring to Figure 19, the third electrode 113 includes a gate 1A and a gate oxide layer 1B.

[0191] For example, referring to FIG19, multiple third electrodes 113 corresponding to multiple first electrodes 111 are integrally arranged, thereby facilitating the synchronous gate control of multiple transistors.

[0192] For example, the material of the gate oxide layer 1B can be referenced to the dielectric layer C2, and will not be described again here. The material of the gate 1A can be referenced to the first electrode 111, and will not be described again here.

[0193] S2: A slot K is formed on the stacked structure 1.

[0194] Referring to Figure 21, the groove K is surrounded by a first groove U1, a second groove U2 and a third groove U3, so that the channel layer 2 formed in the groove K can contact the first electrode 111, the second electrode 112 and the third electrode 113.

[0195] Referring to Figure 21, the slot K includes an opening K1 and multiple sub-slots K2.

[0196] For example, referring to Figures 20 and 21, step S2 may include:

[0197] S21: Refer to Figure 20 to form the opening K1.

[0198] Referring to Figure 20, the opening K1 penetrates through the multilayer first electrode layer 11.

[0199] S22: Referring to Figure 21, the remaining second functional layer P2 is removed through the opening K1 to form a sub-groove K2, so as to expose the first electrode 111, the second electrode 112 and the third electrode 113.

[0200] For example, referring to Figure 21, this step also removes the first functional layer P1 remaining on the inner wall of the opening K1.

[0201] Referring to Figure 21, multiple sub-slots K2 are disposed on the sidewall of the opening K1, and the sub-slots K2 are disposed in the same layer as the first electrode layer 11 so that the channel layer 2 formed later can contact the first electrode layer 11.

[0202] S3: Referring to Figures 22 to 25, multiple channel layers 2 and spacers 3 are formed.

[0203] Referring to Figure 25, the channel layer 2 is disposed on the inner wall of the sub-slot K2 and is in contact with the first electrode layer 11. The spacer 3 is disposed in the sub-slot K2 and is disposed at least on the surface of the channel layer 2 away from the first electrode layer 11.

[0204] For example, referring to Figure 11, step S3 includes the following steps S31 to S33:

[0205] S31: Referring to Figure 22, a semiconductor thin film Q1 is formed on the inner wall of the slot K.

[0206] Referring to Figure 22, the semiconductor thin film Q1 is in contact with the first electrode 111, the second electrode 112 and the third electrode 113.

[0207] S32: Referring to Figure 23, a first insulating material Q2 is formed in the slot K.

[0208] For example, the first insulating material Q2 can be prepared using an atomic layer deposition process.

[0209] Referring to Figure 23, the first insulating material Q2 covers the semiconductor thin film Q1.

[0210] For example, the thickness of the first insulating material Q2 deposited needs to be greater than or equal to half the thickness of the sub-groove K2 so that it can fully fill the sub-groove K2.

[0211] S33: Remove the portions of the semiconductor thin film Q1 and the first insulating material Q2 located in the opening K1 to form multiple channel layers 2 and spacers 3.

[0212] In this design, the portion of the semiconductor thin film located in the sub-groove K2 serves as the channel layer 2, and the portion of the first insulating material located in the sub-groove K2 serves as the spacer portion 3.

[0213] For example, portions of the semiconductor thin film Q1 and the first insulating material Q2 located in the opening K1 can be removed simultaneously.

[0214] Alternatively, by way of example, referring to Figures 24 and 25, step S33 may include:

[0215] S331: Referring to Figure 24, the portion of the first insulating material Q2 located in the opening K1 is removed to form the spacer 3.

[0216] For example, isotropic etching or atomic layer etching processes can be used to selectively etch and form the spacer portion 3.

[0217] S332: Referring to Figure 25, remove the portion of the semiconductor thin film Q1 located in the opening K1 to form the channel layer 2.

[0218] For example, selective etching can be used to remove portions of the semiconductor thin film Q1 to achieve a break between the multilayer channel layers 2.

[0219] Before the semiconductor thin film Q1 is disconnected, the spacer 3 has already covered the channel layer 2. The process of disconnecting the semiconductor thin film Q1 will not cause physical or chemical damage to the channel layer 2. That is, the spacer 3 can provide physical protection for the channel layer 2 (i.e., the spacer 3 can serve as a hard mask for preparing the channel layer 2) in order to improve the electrical performance of the prepared memory array 10.

[0220] S4: Referring to Figure 26, a support portion 4 is formed, which at least fills the opening K1, and a spacer portion 3 is disposed between the support portion 4 and the channel layer 2.

[0221] For example, the aforementioned spacer 3 and support 4 can be prepared using an atomic layer deposition method.

[0222] The material of the spacer 3 is different from that of the support 4, and the hydrogen content of the spacer 3 is less than that of the support 4.

[0223] In the method for fabricating the memory array 10 provided in this application embodiment, by setting the spacer 3 on the channel layer 2 before fabricating the support portion 4, the channel layer 2 is protected. This avoids damage to the channel layer 2 caused by the precursor with a high hydrogen content or a precursor with high reducibility in the atomic layer deposition process used in the preparation of the support portion 4, which is limited by the aspect ratio of the aperture K, coming into contact with the channel layer 2. This improves the electrical performance of the fabricated memory array 10.

[0224] In some embodiments, when preparing the spacer 3 (i.e., step S331), the damage to the channel layer 2 can be reduced by controlling the properties (e.g., reducing properties) of the precursor of the spacer 3.

[0225] For example, the reducing power of the precursor of the spacer portion 3 is less than that of the precursor of the support portion 4, and the hydrogen content of the precursor of the spacer portion 3 is less than that of the precursor of the support portion 4.

[0226] In this embodiment, a spacer 3 is provided between the support portion 4 and the channel layer 2. The material of the spacer 3 is a material with weak precursor reducing properties and low hydrogen content. This separates the channel layer 2 from the support portion 4 without affecting the electrical performance of the channel layer 2, thus preventing the precursor of the support portion 4 from contacting the channel layer 2 and causing damage to the channel layer 2 during the preparation of the support portion 4.

[0227] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A storage array, characterized in that, include: A stacked structure includes multiple layers of first electrode layers stacked and spaced apart; the stacked structure has a slot, the slot including an opening and multiple sub-slots, the opening penetrating the multiple layers of first electrode layers, the multiple sub-slots disposed on the sidewall of the opening, and the sub-slots being disposed in the same layer as the first electrode layers; multiple channel layers, the channel layers being disposed on the inner wall of the sub-slots and in contact with the first electrode layers; a spacer portion disposed in the sub-slots and on the side of the channel layer away from the inner wall of the sub-slot; a support portion filling at least the opening, the spacer portion being disposed between the support portion and the channel layer; wherein the material of the spacer portion is different from the material of the support portion, and the hydrogen content of the spacer portion is less than the hydrogen content of the support portion.

2. The storage array according to claim 1, characterized in that, The spacer and the support are electrically insulating, and the material of the spacer includes one or more of GaO, GaZnO, ZnSiO, and ZnAlO.

3. The storage array according to claim 1 or 2, characterized in that, The channel layer is made of a metal oxide semiconductor material.

4. The storage array according to any one of claims 1 to 3, characterized in that, The channel layer material includes one or more of InGaZnO, InSnZnO, InSnGaZnO, InSnO, InGaO, InMgO, InWO and InAlZnO.

5. The storage array according to any one of claims 1 to 4, characterized in that, At least one metallic element in the material of the spacer portion is the same as the element in the material of the channel layer.

6. The storage array according to any one of claims 1 to 5, characterized in that, The spacer portion at least covers the sidewall of the portion of the channel layer that contacts the first electrode layer.

7. The storage array according to any one of claims 1 to 6, characterized in that, The stacked structure further includes: multiple dielectric layers, wherein the multiple dielectric layers and the multiple first electrode layers are alternately stacked in sequence; the opening penetrates the multiple dielectric layers, and at least a portion of the dielectric layer is disposed between two adjacent sub-slots; wherein the surface of the spacer portion facing the opening is recessed relative to the surface of the dielectric layer facing the opening; and the support portion fills the opening and the portion that fills the sub-slot.

8. The storage array according to any one of claims 1 to 6, characterized in that, The stacked structure further includes: multiple layers of second electrode layers, which are alternately stacked with the multiple layers of first electrode layers, and the second electrode layers are electrically connected to the first electrode layers; the opening penetrates the multiple layers of second electrode layers, and at least a portion of the second electrode layers is disposed between two adjacent sub-slots; wherein the surface of the spacer portion facing the opening is flush with or protrudes from the surface of the second electrode layer facing the opening; the support portion only fills the opening.

9. A method for fabricating a storage array, characterized in that, include: A stacked structure is formed; the stacked structure includes multiple layers of first electrode layers that are stacked and spaced apart. A slot is formed on the stacked structure; the slot includes an opening and a plurality of sub-slots, the opening penetrating the multilayer first electrode layer, the plurality of sub-slots being disposed on the sidewall of the opening, and the sub-slots being disposed in the same layer as the first electrode layer; a plurality of channel layers and spacers are formed; the channel layers are disposed on the inner wall of the sub-slots and are in contact with the first electrode layer; the spacers are disposed in the sub-slots and are at least disposed on the surface of the channel layers away from the first electrode layer; a support is formed, the support at least filling the opening, and the spacers are disposed between the support and the channel layers; wherein the material of the spacers is different from the material of the support, and the hydrogen content of the spacers is less than the hydrogen content of the support.

10. The preparation method according to claim 9, characterized in that, The process of forming multiple channel layers and spacers includes: forming a semiconductor thin film on the inner wall of the slot; forming a first insulating material in the slot; the first insulating material covering the semiconductor thin film and filling at least the multiple sub-slots; removing portions of the semiconductor thin film and the first insulating material located in the openings to form the multiple channel layers and the spacers; the portion of the semiconductor thin film located in the sub-slots serving as the channel layer, and the portion of the first insulating material located in the sub-slots serving as the spacer.

11. The preparation method according to claim 9 or 10, characterized in that, The reducing power of the precursor of the spacer portion is less than that of the precursor of the support portion, and / or the hydrogen content of the precursor of the spacer portion is less than that of the precursor of the support portion.

12. A memory, characterized in that, include: Storage array as described in any one of claims 1 to 8; The peripheral circuitry is electrically connected to the storage array.

13. An electronic device, characterized in that, include: The memory as described in claim 12; The bus is electrically connected to the memory.

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