Ceramic substrate power device package

Abstract

A ceramic substrate power device package comprises a power transistor wafer, a drain electrode bonding pad is arranged on the bottom surface of the power transistor wafer, and a source electrode bonding pad and a switch control electrode bonding pad are arranged on the top surface of the power transistor wafer; the circuit board further comprises a ceramic substrate for bearing a wafer, the ceramic substrate comprises a top circuit layer and a ceramic substrate layer, the top circuit layer of the ceramic substrate forms an L-shaped top circuit layer through an etching process, and the thickness of one side, processed through the etching process, of the top circuit layer is small; the power transistor wafer is welded on the top surface of one side with smaller thickness of the L-shaped top circuit layer of the ceramic substrate through the drain electrode bonding pad; the insulating rubber material is filled around the power transistor wafer horizontally. The ceramic substrate is used as a drain electrode conductive pole piece of the power transistor wafer, a packaged drain electrode bonding pad, a cooling fin and a substrate at the same time; through the insulation performance and the high thermal conductivity of the ceramic substrate layer, a cooling fin can be directly arranged on the bottom circuit layer of the ceramic substrate, and the heat dissipation performance of the power device is improved.

Description

Technical Field

[0001] This invention relates to the processing technology of ceramic substrates; to the packaging technology of power devices, the optimization of chip heat dissipation technology and architecture design; and to the packaging technology of silicon-based transistors, third-generation and fourth-generation semiconductor transistors. Background Technology

[0002] Ceramic-based circuit boards consist of a ceramic substrate and one or two conductive layers. They are manufactured using a special process that involves directly bonding copper foil to the surface of the ceramic substrate at high temperatures, resulting in high thermal conductivity.

[0003] Power transistors (such as MOSFETs, diodes, high electron mobility transistors (HEMTs) and IGBTs) are widely used in high-power electronic devices, such as power management modules, electric vehicle drive systems, and industrial motor control.

[0004] Third-generation semiconductor materials GaN (gallium nitride) and SiC (silicon carbide) are representative of wide-bandgap semiconductors. Power devices made of gallium nitride have significant advantages such as fast switching speed, low on-resistance, and small chip area, and are widely used in power adapters, industrial power supplies, and automotive electronics. SiC transistors, including diodes and MOSFETs, are already widely used.

[0005] Fourth-generation semiconductor materials, mainly represented by diamond and gallium oxide, have begun to be applied to ultra-wide bandgap power devices.

[0006] Traditional power transistor packages typically employ complex lead frames and metal clip structures to achieve electrical connections between the source, gate, and drain. However, this packaging method suffers from the following problems: complex manufacturing process; large size; and limited heat dissipation, impacting device performance. Summary of the Invention

[0007] To address the aforementioned issues, this invention proposes a power transistor packaging structure based on a ceramic substrate supporting a wafer. This structure not only simplifies the packaging process and improves device performance, but also reduces the package size by using wafer pads as packaging pads. Furthermore, the insulation properties and high thermal conductivity of the ceramic substrate layer enhance the performance of the power device.

[0008] To achieve this technical objective, a ceramic substrate power device package includes a power transistor wafer. The bottom surface of the power transistor wafer has a drain pad, and the top surface has a source pad and a switch control pad. The pads on the top and bottom surfaces of the wafer are made of solderable materials used in surface mount technology (SMT) manufacturing, typically nickel-gold or nickel-palladium-gold. The package also includes a ceramic substrate supporting the wafer. The ceramic substrate includes a top circuit layer and a ceramic substrate layer. The top circuit layer of the ceramic substrate is etched to form an L-shaped top circuit layer, with the etched side of the top circuit layer having a smaller thickness. The power transistor wafer is soldered to the top surface of the ceramic substrate on the thinner side of the L-shaped top circuit layer via the drain pad. The top surface of the thicker side of the ceramic substrate has a surface mount metal layer for easy soldering, typically nickel or nickel-gold plated to prevent copper oxidation. The top surface of the power transistor wafer is flush with the top surface of the thicker side of the L-shaped top circuit layer on the ceramic substrate. Source and switch control pads are located on the top surface of the thicker side of the L-shaped top circuit layer on the ceramic substrate and the top surface of the power transistor wafer, serving as the drain, source, and switch control pads for the package. Insulating filler is also included, filling the top surface of the thinner side of the L-shaped top circuit layer on the ceramic substrate and around the perimeter of the power transistor wafer. To achieve mass production, the ceramic substrate needs to be fabricated into a multi-plate assembly. After the insulating filler is filled, the assembly is then divided into individual small packages.

[0009] Preferably, the ceramic substrate is a three-layer ceramic substrate, including a top circuit layer, a ceramic substrate layer and a bottom circuit layer. The top circuit layer of the ceramic substrate is formed into an L-shaped top circuit layer by an etching process.

[0010] Preferably, the power transistor wafer is a diode wafer. The bottom surface of the diode wafer has an anode pad, and the top surface has a cathode pad. The diode wafer is soldered to the top surface of the L-shaped top layer of the ceramic substrate (the side with the thinner top layer) via the anode pad. The top surface of the diode wafer is flush with the top surface of the L-shaped top layer of the ceramic substrate (the side with the thicker top layer). A surface-mount metal layer suitable for soldering is deposited on the top surface of the L-shaped top layer of the ceramic substrate. The cathode pads on the top surface of the L-shaped top layer of the ceramic substrate and the top surface of the diode wafer serve as the anode and cathode pads for the package.

[0011] Preferably, the power transistor wafer is a group of two or more transistor wafers, which are respectively soldered to the top surface of the L-shaped top circuit layer of the ceramic substrate with a thinner side via drain pads. The group of transistor wafers are packaged in the same package, and their drains are electrically connected. The finished transistor in this package can be used as a parallel transistor to expand current carrying capacity, or as the high-side circuit in a bridge circuit.

[0012] The beneficial effects of this technical solution are: it simplifies the packaging process by connecting the drain pad or diode anode pad through the L-shaped top circuit layer of the ceramic substrate, eliminating the need for metal clips and complex soldering steps in traditional packaging, thus improving production efficiency. The ceramic substrate can directly contact the external heat sink, shortening the heat dissipation path, reducing thermal resistance, and improving the device's heat dissipation performance. Attached Figure Description

[0013] Figure 1 This is a cross-sectional schematic diagram of a specific embodiment of the present invention.

[0014] Figure 2 This is a top view of a power transistor wafer according to a specific embodiment of the present invention.

[0015] Figure 3 This is a bottom view of a power transistor wafer according to a specific embodiment of the present invention.

[0016] Figure 4 This is a top view of the packaged structure according to a specific embodiment of the present invention.

[0017] Figure 5 This is a bottom view of the packaged structure according to a specific embodiment of the present invention.

[0018] Figure 6 This is a top view of a mass production connecting plate according to a specific embodiment two of the present invention.

[0019] Figure 7 This is a cross-sectional schematic diagram of a specific embodiment three of the present invention.

[0020] Figure 8 This is a top view of the package of a specific embodiment four of the present invention.

[0021] Figure 9 This is a top view of a group of power transistor wafers within the same package, according to a specific embodiment five of the present invention. Detailed Implementation

[0022] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0023] like Figure 1 The image shown is a cross-sectional schematic diagram of a specific embodiment of the present invention. A ceramic substrate power device package includes a power transistor wafer 1. The bottom surface of the power transistor wafer 1 has a drain pad 11, and the top surface of the power transistor wafer 1 has a source pad 12 and a switch control pad 13. The pads 11, 12, and 13 on the top and bottom surfaces of the wafer 1 are made of nickel-gold or nickel-palladium-gold materials that are solderable in surface mount technology (SMT) manufacturing. The package also includes a ceramic substrate 2 supporting the wafer. The ceramic substrate 2 includes a top circuit layer 21 and a ceramic substrate layer 22. The top circuit layer of the ceramic substrate 2 is etched to form an L-shaped top circuit layer 21, with the etched side 212 having a smaller thickness. The power transistor wafer 1 is soldered to the top surface of the thinner side 212 of the L-shaped top circuit layer 21 on the ceramic substrate via the drain pad 11. The top surface of the thicker side 211 of the L-shaped top circuit layer 21 on the ceramic substrate is plated with a surface mountable nickel layer 2111. To prevent copper oxidation; the top surface of the power transistor wafer is flush with the top surface of the thicker side 211 of the L-shaped top circuit layer 21 on the ceramic substrate. The thickness of the power transistor wafer 1 is 0.18 mm, the thickness of the thicker side 211 of the L-shaped top circuit layer 21 on the ceramic substrate is 0.38 mm, and the thickness of the thinner side 212 of the L-shaped top circuit layer 21 on the ceramic substrate is 0.2 mm; the source pad 12 and the switch control electrode pad 13 arranged on the top surface 2111 of the thicker side 211 of the L-shaped top circuit layer on the ceramic substrate and the top surface of the power transistor wafer serve as the drain pad, source pad, and switch control electrode pad for packaging; it also includes an insulating filler 3, which fills the top surface of the thinner side 212 of the L-shaped top circuit layer 21 on the ceramic substrate and around the perimeter of the power transistor wafer 1.

[0024] like Figure 2 The image shown is a top view of a power transistor wafer according to a specific embodiment of the present invention. The top surface of the power transistor wafer 1 is provided with source pads 12 and switch control pads 13. The source pads 12 and switch control pads 13 are made of nickel-gold or nickel-palladium-gold alloys to meet the SMT production requirements of electronic products.

[0025] like Figure 3 The image shown is a bottom view of a power transistor wafer according to a specific embodiment of the present invention. Drain pads 11 are arranged on the bottom surface of the power transistor wafer 1. Nickel-gold or nickel-palladium-gold alloys are used.

[0026] The source and drain pads of a vertical power transistor wafer are located on the top and bottom sides of the wafer, respectively.

[0027] like Figure 4 The image shown is a top view of the packaged structure according to a specific embodiment of the present invention.

[0028] The top surface 2111 of the thicker side 211 of the L-shaped top circuit layer 21 on the ceramic substrate is plated with a nickel layer that is easy to solder using SMT processes. The source pad 12 and the switch control electrode pad 13 arranged on the top surface 2111 and the top surface of the power transistor wafer 1 serve as the drain pad, source pad, and switch control electrode pad for packaging. The insulating filler 3 is applied to the top surface 212 of the thinner side of the L-shaped top circuit layer 21 on the ceramic substrate and is applied to the horizontal perimeter of the power transistor wafer 1.

[0029] like Figure 5 The image shown is a bottom view of a package according to a specific embodiment of the present invention. The bottom surface of the package is the bottom surface 221 of the ceramic substrate 2.

[0030] like Figure 6 The image shown is a top view of a mass-produced interconnect board according to a specific embodiment two of the present invention. The interconnect board consists of two rows and three columns of single-unit packages. A group of six power transistor wafers (1-1 to 1-6) are soldered to the top surface of the L-shaped top layer circuitry layer (which includes six ceramic substrate units) on the side with the thinner layer, via wafer drain pads. After insulating filler is applied to the horizontal perimeter of the group of six power transistor wafers (1-1 to 1-6), transverse cuts are made along line X-1 and longitudinal cuts are made along lines Y-1 and Y-2 to divide the interconnect board into individual packages, enabling mass production. During production, process edges are sometimes added to the interconnect board according to equipment and production line parameters to facilitate production.

[0031] like Figure 7 The diagram shown is a cross-sectional schematic of a specific embodiment three of the present invention. Based on Example 1, the ceramic substrate 2 is a three-layer ceramic substrate, including a top circuit layer 21, a ceramic substrate layer 22, and a bottom circuit layer 23. The top circuit layer 21 of the ceramic substrate 2 is an L-shaped top circuit layer formed by an etching process. Because the ceramic substrate layer 22 is an insulating layer and has excellent thermal conductivity, in the use of power transistors, the bottom circuit layer 23 can be directly soldered with a heat sink, increasing the performance of the power transistor.

[0032] like Figure 8 The image shown is a top view of the package of a specific embodiment four of the present invention. The power transistor wafer is a diode wafer 1. An anode pad is provided on the bottom surface of diode wafer 1, and a cathode pad 12 is provided on the top surface of diode wafer 1. Diode wafer 1 is soldered to the top surface of the ceramic substrate on the side with the smaller thickness of the L-shaped top circuit layer via the anode pad. The top surface of diode wafer 1 is flush with the top surface 2111 on the side with the larger thickness of the L-shaped top circuit layer of the ceramic substrate. Top surface 2111 is a nickel layer that is easily soldered using SMT processes. Insulating filler 3 is applied to the top surface of the ceramic substrate on the side with the smaller thickness of the L-shaped top circuit layer and is applied to the horizontal perimeter of diode wafer 1.

[0033] like Figure 9The image shows a top view of a group of power transistor wafers within the same package according to a specific embodiment five of the present invention. A single package includes three power transistor wafers 1-1, 1-2, and 1-3; a ceramic substrate 2; and power transistor wafers 1-1, 1-2, and 1-3 are respectively soldered to the top surface of the ceramic substrate on the side with the smaller thickness of the L-shaped top layer circuitry layer via drain pads. The top surface of the power transistor wafers is flush with the top surface 2111 on the side with the larger thickness of the L-shaped top layer circuitry layer of the ceramic substrate. Insulating filler is filled around the horizontal perimeter of power transistor wafers 1-1, 1-2, and 1-3. The top surface 2111 on the side with the larger thickness of the L-shaped top layer circuitry layer of the ceramic substrate serves as the drain pad for the package. The top surface 2111 is a solderable nickel-gold layer for SMT processes and is the parallel drain pad for power transistor wafers 1-1, 1-2, and 1-3. The power transistors in this package can be used as parallel transistors or as the high-side circuit of a bridge circuit.

[0034] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any minor modifications, equivalent substitutions, and improvements made to the above embodiments based on the technical essence of the present invention should be included within the protection scope of the present invention.

Claims

1. A ceramic substrate power device package, characterized in that: The system includes a power transistor wafer with drain pads on its bottom surface and source and switch control pads on its top surface; it also includes a ceramic substrate supporting the wafer, comprising a top circuit layer and a ceramic substrate layer. The top circuit layer of the ceramic substrate is etched to form an L-shaped top circuit layer, with the etched side having a thinner thickness; the power transistor wafer is soldered to the top surface of the thinner side of the L-shaped top circuit layer on the ceramic substrate via the drain pads; the top surface of the thicker side of the L-shaped top circuit layer on the ceramic substrate is plated with a surface mount metal layer suitable for soldering circuit boards; the top surface of the power transistor wafer is flush with the top surface of the thicker side of the L-shaped top circuit layer on the ceramic substrate; and it also includes an insulating filler compound, which fills the top surface of the thinner side of the L-shaped top circuit layer on the ceramic substrate and around the perimeter of the power transistor wafer.

2. The ceramic substrate power device package according to claim 1, characterized in that: The ceramic substrate includes a top circuit layer, a ceramic substrate layer, and a bottom circuit layer. The top circuit layer of the ceramic substrate is formed into an L-shaped top circuit layer through an etching process.

3. The ceramic substrate power device package according to claim 1, characterized in that: The power transistor wafer is a diode wafer. The bottom surface of the diode wafer is provided with an anode pad, and the top surface of the diode wafer is provided with a cathode pad. The diode wafer is soldered to the top surface of the L-shaped top circuit layer of the ceramic substrate with a smaller thickness through the anode pad. The top surface of the diode wafer is flush with the top surface of the L-shaped top circuit layer of the ceramic substrate with a larger thickness.

4. The ceramic substrate power device package according to claim 1, characterized in that: The power transistor wafer is a group of two or more transistor wafers, which are respectively soldered to the top surface of the L-shaped top circuit layer of the ceramic substrate with a smaller thickness via drain pads.

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