Ion implantation layer filling optimization method

Abstract

The application provides an ion implantation layer filling optimization method, comprising the following steps: S1. providing a layout; S2. identifying a first pattern and a second pattern from the layout; the first pattern is an ion implantation layer pattern processed by center offset and photolithography offset, comprising a first side parallel to a first direction and a second side parallel to a second direction, and the first side and the second side intersect to form a vertex A; the second pattern is an edge ion implantation layer pattern, comprising a third side parallel to the first direction and a fourth side parallel to the second direction, and the third side and the fourth side intersect to form a vertex B; any one of the following conditions is satisfied: ① the distance Lh between the second side and the fourth side in the first direction is less than L1, and the distance Lv between the first side and the third side in the second direction is less than L2; ② after the layout is simulated by OPC, the simulated distance Ls between the vertex A and the vertex B is less than L3; S3. constructing a filling pattern: moving the vertex A by Bh in the reverse direction of the first direction and by Lv+Bv in the reverse direction of the second direction; moving the vertex B by Bh in the forward direction of the first direction and by Lv+Bv in the forward direction of the second direction; extending the boundary of each moving end point perpendicularly to the corresponding side to form a filling pattern.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an optimization method for ion implantation layer filling. Background Technology

[0002] In the field of chip manufacturing, especially in the fabrication of Static Random Access Memory (SRAM) devices, the implant layer is one of the core functional layers. This layer can precisely and controllably change the electrical properties of specific areas of the silicon wafer, thereby clearly defining the core structure of the transistor (including the source, drain, and channel region below the gate) and other various isolation regions. Its relative position and topological relationship with other functional layers of the chip (such as the active region AA) directly determine the final electrical performance and reliability of the device.

[0003] Currently, the design pattern of the IMPLANT layer in SRAM devices is typically generated using logical calculations such as Boolean operations. However, this generation method introduces inherent defects into the design layout input to the Optical Proximity Correction (OPC) process, negatively impacting the effectiveness and stability of OPC operations, such as... Figure 6 As shown, this manifests in two key issues: First, after OPC correction (post-OPC), the layout is prone to forming abnormal shapes such as point-to-point structures or bridge structures, which may lead to the risk of small photoresist falling off (1), ultimately resulting in functional defects in the wafer; Second, new manufacturing rule check (MRC) violations are likely to occur during the post-OPC process (2), which may cause the photomask to be fabricated in a manner that does not meet the process specifications, thereby causing photomask defects and seriously affecting the mass production yield and manufacturing cost of the chip. Summary of the Invention

[0004] To address all or part of the problems in the prior art, this invention provides an ion implantation layer filling optimization method. By identifying high-risk ion implantation layer pattern pairs and performing targeted boundary extension filling, it effectively avoids the problems of small photoresist drop and MRC violation after OPC, while maintaining the topological relationship between the ion implantation layer and the active region layer, thereby improving the photomask fabrication yield and device reliability.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A method for correcting the pattern of an ion implantation layer includes the following steps: S1. Provides the ion implantation layer layout; S2. Identify the first and second patterns from the layout: The first pattern is an ion implantation layer pattern processed by center offset and photolithography offset, including a first side parallel to the first direction and a second side parallel to the second direction, which intersect perpendicularly to form vertex A; The second pattern is an edge ion implantation layer pattern, including a third side parallel to the first direction and a fourth side parallel to the second direction, which intersect perpendicularly to form vertex B; The first graphic and the second graphic satisfy either of the following conditions: ① In the first direction, the distance Lh between the second side and the fourth side is less than the preset distance L1; and in the second direction, the distance Lv between the first side and the third side is less than the preset distance L2; ② After the layout is corrected by OPC simulation, the simulated graphic distance Ls between vertex A and vertex B is less than the preset distance L3. S3. Construct a filled shape: Move a first predetermined length Bh in the opposite direction of the first direction from vertex A of the first shape, and move Lv+2 predetermined length Bv in the opposite direction of the second direction; move Bh in the forward direction of the first direction from vertex B of the second shape, and move Lv+Bv in the forward direction of the second direction; extend the boundary perpendicularly to the corresponding side from each moving endpoint to enclose and form a filled shape.

[0006] In step S2, the preset distance L1 ranges from 144 to 216; the preset distance L2 ranges from 47 to 94.

[0007] In step S2, the preset distance L3 ranges from 47 to 94.

[0008] The OPC simulation correction method is a process that uses a lithography simulation model based on the current process node to simulate the exposure and imaging process of the lithography machine, predicts the actual graphic shape of the layout after OPC correction, and performs actual adjustments to the layout graphic based on the simulation results. The adjustment results directly affect the final photomask fabrication data.

[0009] The first pattern includes a first offset region and a second offset region. The first offset region is a region formed by a center offset operation, and its boundary is equidistant from the active regions on both sides. The second offset region is located outside the first offset region and is a region formed by a photolithographic offset operation.

[0010] In step S3, if the enclosed area of ​​the filled pattern covers the active region layer, then the corresponding active region layer area is not filled.

[0011] The first set length Bh and the second set length Bv are calculated using the following formula: Bh = (mrcCD - Lh) / 2 + 5nm); Bv = (mrcCD - Lv) / 2 + 5nm); Where mrcCD is the minimum pattern size specified by the photomask rules corresponding to the current process node.

[0012] Step S3 also includes a sub-step for obtaining spacing parameters: the spacing parameters include the actual horizontal spacing Saa between the filled pattern and the adjacent active region layer (distance from the adjacent active region), and the minimum safe spacing mrcSpAA between the ion implantation layer and the active region layer specified in the process document.

[0013] When Saa≥mrcSpAA, it is determined that the spacing between the filled pattern and the active region layer meets the process requirements, and the calculated values ​​of Bh and Bv remain unchanged.

[0014] When Saa < mrcSpAA, it is determined that the spacing between the filled pattern and the active region layer does not meet the process requirements. The first set length Bh and the second set length Bv are adjusted, specifically including the following steps: The first set length Bh of the first graphic is adjusted to Bh1, and the second set length Bv is adjusted to Bv1; the first set length Bh of the second graphic is adjusted to Bh2, while the second set length Bv remains unchanged; the adjustment formula is: Bh1 = Bh - (mrcSpAA – Saa); Bh2 = Bh + (mrcSpAA – Saa); Bv1 = Bv + (mrcSpAA – Saa). Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a process flow diagram of an ion implantation layer filling optimization method according to an embodiment of the present invention.

[0017] Figure 2 This is a schematic diagram of the ion implantation layer layout structure after being processed by the ion implantation layer filling optimization method according to an embodiment of the present invention.

[0018] Figure 3 This is a schematic diagram illustrating the calculation formula for setting the length in the ion implantation layer filling optimization method described in this embodiment of the invention.

[0019] Figure 4The diagram shows a comparison of the layout structures of the embodiments of the present invention with and without the aforementioned ion implantation layer filling optimization method.

[0020] Figure 5 The diagram shows a comparison of the layout structures of the embodiments of the present invention with and without the aforementioned ion implantation layer filling optimization method.

[0021] Figure 6 This is a schematic diagram of the ion implantation layer layout structure in the background art.

[0022] Figure reference numerals: 1. First figure; 101. First side; 102. Second side; Vertex A; 2. Second figure; 201. Third side; 202. Fourth side; Vertex B; 3. OPC simulation figure. Detailed Implementation

[0023] The technical solutions in specific embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] This invention provides an ion implantation layer filling optimization method, such as... Figures 1 to 5 As shown, this method aims to solve technical problems such as the risk of small photoresist falling off structures like Point2Point structures or Bridges, and violations of Manufacturing Rule Check (MRC) during Optical Proximity Correction (OPC) of the ion implantation layer (hereinafter referred to as "implantation layer") generated by Boolean operations in the layout of Static Random Access Memory (SRAM). It ensures the stability of the topological relationship between the implantation layer and the active region layer (AA layer), improves the yield of photomask fabrication and the reliability of the device. This method is specifically applicable to the ion implantation layer processing of SRAM layout. The following is a detailed explanation of the technical principles and steps.

[0025] First, step S1 is executed: This provides the ion implantation layer layout processed by center biasing and lithographic biasing operations. The core purpose of the center biasing operation is to form the first bias region of the implantation layer pattern, ensuring that the boundary of the first bias region is equidistant from the AA layers on both sides (e.g., ...). Figure 1As shown, L=L), ensuring the uniformity of ion implantation in the core region; the photolithography offset operation is used to form a second offset region located outside the first offset region. Its function is to pre-compensate for the pattern distortion caused by the diffraction effect of light during the photolithography process, provide basic pattern guarantee for subsequent filling optimization and OPC correction, and avoid introducing additional process risks in the preprocessing stage.

[0026] Then, step S2 is executed: the first pattern 1 and the second pattern 2 are identified from the implanted layer layout after the above processing. The first pattern 1 is the target ion implantation layer pattern after center offset and photolithographic offset operations, corresponding to the implantation layer structure of the core memory cell region in the SRAM layout; the second pattern 2 is the ion implantation layer pattern adjacent to the first pattern 1, and it is an edge pattern of the SRAM layout, specifically corresponding to the implantation layer structure of the peripheral circuit region at the edge of the SRAM array. Due to the layout characteristics of the peripheral circuit, center offset and photolithographic offset operations are not required. The two are spatially adjacent and constitute a pattern pair that may cause OPC risks.

[0027] Further, the first pattern 1 includes a first side 101, a second side 102, and vertex A. The first side 101 is parallel to the first direction (X-axis) and extends along the row direction of the SRAM memory cell. The second side 102 is parallel to the second direction (Y-axis) and extends along the column direction of the SRAM memory cell. Vertex A is formed where the two sides intersect perpendicularly. The second pattern 2 includes a third side 201, a fourth side 202, and vertex B. The third side 201 is parallel to the X-axis, and the fourth side 202 is parallel to the Y-axis. Vertex B is formed where the two sides intersect perpendicularly. To accurately screen high-risk pattern pairs, the first pattern 1 and the second pattern 2 must satisfy any of the following conditions: ① In the X-axis direction, the distance Lh between the second side 102 of the first graphic 1 and the fourth side 202 of the second graphic 2 is less than the preset distance L1 (the value of L1 ranges from 144 to 216); at the same time, in the Y-axis direction, the distance Lv between the first side 101 of the first graphic 1 and the third side 201 of the second graphic 2 is less than the preset distance L2 (the value of L2 ranges from 47 to 94, and can be positive or negative; when L2 is positive, it indicates that the first side 101 of the first graphic 1 and the fourth side 202 of the second graphic 2 are separated in the Y-axis direction, and the distance is positive; when L2 is negative, it indicates that the two partially overlap in the Y-axis direction). ② After OPC simulation correction, the distance Ls between vertex A of the first graphic 1 and vertex B of the second graphic 2 in the simulation is less than the preset distance L3 (the value of L3 ranges from 47 to 94). OPC simulation is based on the MBOPC (Model-based optical proximity correction) method, which uses a lithography simulation model of the current process node to predict the actual graphic shape of the layout after OPC correction by simulating the lithography machine's exposure and imaging process. The difference between OPC simulation and OPC correction is that OPC simulation is a predictive analysis process before correction, requiring no physical modification to the original layout, while OPC correction is an execution process that actually adjusts the layout graphic based on the simulation results, and the adjustment results directly affect the final photomask fabrication data.

[0028] The above preset distances are all set based on the process file (Tech File) of the current process node. Their core function is to accurately screen out graphic pairs that may form Point2Point or Bridge structures in the post-OPC stage due to excessively small spacing, providing a target basis for subsequent targeted filling.

[0029] Next, step S3 is executed: The identified first pattern 1 and second pattern 2 are constructed with filling patterns, ensuring that the spacing between the filling pattern and the AA layer meets process requirements. The core function of the filling pattern is to eliminate excessively small spacing between the first pattern 1 and the second pattern 2, preventing high-risk structures in the post-OPC stage and ensuring the integrity of ion implantation. Specifically, the first pattern 1 extends from vertex A in the reverse direction along the X-axis by a first predetermined length Bh, and in the reverse direction along the Y-axis by Lv + a second predetermined length Bv; the second pattern 2 extends from vertex B in the forward direction along the X-axis by a first predetermined length Bh, and in the forward direction along the Y-axis by Lv + a second predetermined length Bv; extension boundaries are drawn perpendicular to the corresponding sides from each extension endpoint, and these extension boundaries enclose and form the filling pattern. This filling pattern is an ion implantation layer pattern, with the same material as the first pattern 1 and the second pattern 2, and is only formed in areas where no AA layer is provided. If an AA layer exists within the enclosed area of ​​the filling pattern, the area covered by the corresponding AA layer is not filled to avoid affecting the electrical characteristics of the active region.

[0030] The first predetermined length Bh and the second predetermined length Bv are calculated using the following formula: Bh = (mrcCD - Lh) / 2 + 5nm; Bv = (mrcCD - Lv) / 2 + 5nm.

[0031] Wherein, mrcCD is the minimum pattern size specified by the photomask rules under the current process node; the calculation of (mrcCD-Lh) / 2 and (mrcCD-Lv) / 2 is to make the linewidth at the junction of the extended patterns reach the minimum resolvable critical size, so as to meet the process requirements of photomask fabrication. The additional 5nm provides redundancy for process implementation and further reduces the risk of photomask defects.

[0032] Step S3 also includes a sub-step of obtaining spacing parameters and adjusting Bh and Bv according to the parameters: the spacing parameters include the actual horizontal spacing Saa between the filled pattern and the adjacent AA layer, and the minimum safe spacing mrcSpAA between the injection layer and the AA layer specified in the process document.

[0033] When Saa≥mrcSpAA, the spacing between the filled graphic and the AA layer is determined to meet the process requirements. There is no need to adjust the calculated values ​​of Bh and Bv, and the initial values ​​remain unchanged. When Saa < mrcSpAA, the spacing between the fill pattern and the AA layer is determined to be inconsistent with the process requirements. Bh and Bv need to be adjusted adaptively to ensure that the fill still conforms to the MRC rules. The specific adjustment method is as follows: like Figure 3 As shown, the first set length Bh of the first graphic 1 is adjusted to Bh1, and the second set length Bv is adjusted to Bv1; the first set length Bh of the second graphic 2 is adjusted to Bh2, while the second set length Bv remains unchanged. The adjustment formula is as follows: Bh1 = Bh - (mrcSpAA – Saa); Bh2 = Bh + (mrcSpAA – Saa); Bv1 = Bv + (mrcSpAA – Saa).

[0034] Through the above targeted adjustments, while ensuring the filling effect and avoiding OPC risks, it is possible to ensure that the filling graphic and the AA layer always maintain a safe distance, thus avoiding new MRC violation issues.

[0035] This method addresses two core risks by specifically filling meaningless small gaps in the layout caused by center bias operations, while moderately enlarging the linewidth in critical areas. Firstly, the enlargement operation directly increases the linewidth of the corresponding structure during photomask fabrication, ensuring it meets the minimum resolvable critical size requirements of the current process node and reducing the defect rate during photomask preparation. Secondly, filling the small gaps eliminates the basis for forming Point2Point and Bridge structures after OPC correction, avoiding the risk of small photoresist formation and fallout. Simultaneously, by controlling the safe spacing between the filled pattern and the AA layer through process rules, the relative position and topological relationship between the injection layer and the AA layer in the SRAM core region are ensured to always conform to design specifications, without affecting the core electrical performance of the device.

[0036] To verify the effectiveness of the technical solution of this invention, OPC correction and optical simulation tests were performed on the layouts of two typical application scenarios (case1 and case2). The results are as follows: (1) such as Figure 4 As shown in Figure 1 (Figure a shows the result without using this method, and Figure b shows the result with the method of this invention), the simulation effect of case 1 is as follows: After the pattern filling and expansion operation of this invention, the linewidth at the junction of patterns in the layout is increased by 247% compared to before processing. The linewidth size fully meets the process window requirements for photomask fabrication. The risk of defects such as breakage and deformation caused by excessively small linewidth during photomask fabrication is significantly reduced, and the photomask yield is greatly improved. At the same time, the relative position, spacing and topological relationship between the injection layer and the AA layer remain unchanged, ensuring that the core performance of the device is not affected.

[0037] (2) such as Figure 5 As shown in Figure 2 (Figure a shows the result without using this method, and Figure b shows the result with the method of this invention), the simulation effect is as follows: Through the small gap filling operation of this invention, meaningless small gaps at the junction of patterns in the layout are completely filled, completely eliminating the conditions for the formation of small photoresist after OPC correction, and fundamentally avoiding wafer defects caused by the falling of small photoresist; moreover, the filling operation strictly follows the MRC rules and the safety spacing requirements of the AA layer, and no new manufacturing rule inspection (MRC) violations are generated after filling, the photomask preparation meets the process specifications, and the original design relationship between the injection layer and the AA layer remains stable, thus ensuring both device reliability and mass production yield.

[0038] In summary, this invention effectively solves the core problems in the prior art, such as photomask defects, small photoresist drop, and MRC violations, by precisely filling and expanding specific patterns in the injection layer. While ensuring that the core performance of the device is not affected, it significantly improves the chip manufacturing yield and reduces mass production costs.

[0039] It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this invention.

Claims

1. A method for correcting the pattern of an ion implantation layer, characterized in that, Includes the following steps: S1. Provides the ion implantation layer layout; S2. Identify the first and second patterns from the layout: The first pattern is an ion implantation layer pattern processed by center offset and photolithography offset, including a first side parallel to the first direction and a second side parallel to the second direction, which intersect perpendicularly to form vertex A; The second pattern is an edge ion implantation layer pattern, including a third side parallel to the first direction and a fourth side parallel to the second direction, which intersect perpendicularly to form vertex B; The first graphic and the second graphic satisfy either of the following conditions: ① In the first direction, the distance Lh between the second side and the fourth side is less than the preset distance L1; and in the second direction, the distance Lv between the first side and the third side is less than the preset distance L2; ② After the layout is corrected by OPC simulation, the simulated graphic distance Ls between vertex A and vertex B is less than the preset distance L3. S3. Construct a filled shape: Move a first predetermined length Bh in the opposite direction of the first direction from vertex A of the first shape, and move Lv+2 predetermined length Bv in the opposite direction of the second direction; move Bh in the forward direction of the first direction from vertex B of the second shape, and move Lv+Bv in the forward direction of the second direction; extend the boundary perpendicularly to the corresponding side from each moving endpoint to enclose and form a filled shape.

2. The method according to claim 1, characterized in that, In step S2, the preset distance L1 ranges from 144 to 216; the preset distance L2 ranges from 47 to 94.

3. The method according to claim 1, characterized in that, In step S2, the preset distance L3 ranges from 47 to 94.

4. The method according to claim 1, characterized in that, The OPC simulation correction method is based on the lithography simulation model of the current process node. It predicts the actual graphic shape of the layout after OPC correction by simulating the exposure and imaging process of the lithography machine, and performs actual adjustments to the layout graphic based on the simulation results. The adjustment results directly affect the final photomask fabrication data.

5. The method according to claim 1, characterized in that, The first pattern includes a first offset region and a second offset region. The first offset region is a region formed by a center offset operation, and its boundary is equidistant from the active regions on both sides. The second offset region is located outside the first offset region and is a region formed by a photolithographic offset operation.

6. The method according to claim 1, characterized in that, In step S3, if the enclosed area of ​​the filled pattern covers the active region layer, then the corresponding active region layer area is not filled.

7. The method according to claim 1, characterized in that, The first set length Bh and the second set length Bv are calculated using the following formula: Bh = (mrcCD - Lh) / 2 + 5nm); Bv = (mrcCD - Lv) / 2 + 5nm); Where mrcCD is the minimum pattern size specified by the photomask rules corresponding to the current process node.

8. The method according to claim 7, characterized in that, Step S3 also includes a sub-step for obtaining spacing parameters: the spacing parameters include the actual horizontal spacing Saa between the filled pattern and the adjacent active region layer, and the minimum safe spacing mrcSpAA between the ion implantation layer and the active region layer specified in the process document.

9. The method according to claim 8, characterized in that, When Saa≥mrcSpAA, it is determined that the spacing between the filled pattern and the active region layer meets the process requirements, and the calculated values ​​of Bh and Bv remain unchanged.

10. The method according to claim 8, characterized in that, When Saa < mrcSpAA, it is determined that the spacing between the filled pattern and the active region layer does not meet the process requirements. The first set length Bh and the second set length Bv are adjusted, specifically including the following steps: The first set length Bh of the first graphic is adjusted to Bh1, and the second set length Bv is adjusted to Bv1; the first set length Bh of the second graphic is adjusted to Bh2, while the second set length Bv remains unchanged; the adjustment formula is: Bh1 = Bh - (mrcSpAA – Saa); Bh2 = Bh + (mrcSpAA – Saa); Bv1 = Bv + (mrcSpAA – Saa).

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