circuit components

Abstract

The invention relates to a circuit assembly having an application network (10), a first current source (20), a second current source (25), a differential readout circuit (30) and a signal processing unit (40), wherein the first current source (20) is designed to inject a first predefined signal (S1) into a first impedance of the application network (10) coupled to a first interface (11) via the first interface (11), the second current source (25) is designed to inject a second predefined signal (S2) into a second impedance of the application network (10) coupled to a second interface (12) via the second interface (12), the first current source (20) and the second current source (25) are designed to inject the first signal (S1) and the second signal (S2) into the first impedance and the second impedance simultaneously or time-displaced, the differential readout circuit (30) is designed to generate a differential signal (SD) on the basis of a voltage applied at the first interface (11) and a voltage applied at the second interface (12), and wherein the signal processing unit (40) is designed to determine a deviation of the circuit assembly from a target state on the basis of the differential signal (SD).

Description

Technical Field

[0001] The present invention relates to a circuit assembly, and more particularly to a circuit assembly for determining the deviation between the circuit assembly and a target state based on a differential readout circuit. Background Technology

[0002] Differential readout circuits are known from the prior art, which check the impedance at the interface of the circuit based on a current signal in order to identify, for example, defective connections in the signal transmission path.

[0003] DE000004308280A1 discloses a method for monitoring the electrical connection between a potentiometer and an analysis and processing electronic device, wherein a rectangular AC voltage is coupled into the sliding contact line of the potentiometer, and discloses a circuit assembly for performing the method. Summary of the Invention

[0004] The circuit assembly according to the present invention includes an application network, a first current source, a second current source, a differential readout circuit, and a signal processing unit.

[0005] In principle, the application network can be configured in any way to provide application signals (such as sensor measurement signals, especially DC signals or slowly changing signals, such as temperature measurement signals) via a first interface and a second interface.

[0006] The first current source is configured to inject a first predefined signal (i.e., a first current signal) into a first impedance of the application network coupled to the first interface via a first interface, and the second current source is configured to inject a second predefined signal (i.e., a second current signal) into a second impedance of the application network coupled to the second interface via a second interface. The duration and fundamental frequency of the first signal and the second signal are hereby defined as being the same.

[0007] The first current source and the second current source are configured such that the first signal and the second signal are simultaneously injected into the first impedance and the second impedance, such that the signal change curves of the first signal and the second signal are the same, or that the scaling factor is different only in terms of their amplitude.

[0008] Alternatively, the first current source and the second current source are configured to inject the first signal and the second signal into the first impedance and the second impedance in a time-staggered manner, wherein the second signal is located in time between two consecutive first signals, and wherein a predefined dead time is observed between the respective first signal and the second signal.

[0009] It should be noted that, depending on the application, the use of the first and second signals, which are generated simultaneously or staggered, can be advantageous. Furthermore, the alternating use of simultaneously generated and staggered signals can be considered.

[0010] The application signal of the application network is located in the following frequency range: this frequency range does not intersect with the frequency range of the first and second signals in the target state of the circuit components (i.e., in the fault-free state).

[0011] Furthermore, the differential readout circuit is configured to generate a differential signal based on the voltage applied to the first interface and the voltage applied to the second interface. For example, the differential signal can be amplified and / or converted to digital signal value to advantageously enable downstream signal processing based on the digital signal, rather than being limited to digital signal processing.

[0012] The signal processing unit is configured to calculate the deviation of the circuit components from the target state (i.e., a fault-free state or a deviation-free state) based on the differential signal. Various deviations are advantageously considered here, and these deviations are further described in more detail below in the process of describing the advantageous configuration of the invention.

[0013] The signal processing unit and / or other components of the circuit assembly according to the invention may be configured as, for example, an ASIC, FPGA, processor, digital signal processor, microcontroller, or the like. Furthermore, it is possible that the signal processing unit and / or other components of the circuit assembly are collectively constructed as a single (e.g., integrated) unit and / or at least partially constructed as separate units.

[0014] The first and second signals constructed according to the invention, combined with the differential readout circuit, provide the following particular advantages: they do not interfere with the application signals of the application network in a fault-free state of the circuit assembly; they can compensate for non-critical deviations within the circuit assembly that may affect the application signals; and they can identify different fault states. Therefore, circuit assemblies based on the invention enable particularly reliable operation and / or particularly targeted fault handling of the circuit assembly.

[0015] The dependent claims illustrate preferred extensions of the invention.

[0016] More preferably, the application signal of the application network is essentially a DC voltage signal and / or a signal provided by a sensor, and especially a low-frequency signal. Such a signal may be, for example, a voltage measurement signal and / or a temperature measurement signal and / or a signal different from this.

[0017] Particularly preferably, the first and second signals are rectangular signals, but not limited to this signal shape. In particular, constructing them as rectangular signals is advantageous because this signal shape can be implemented particularly simply and cost-effectively. When the first and second signals are generated in a time-staggered manner, the first and second signals have the same or substantially the same area below their respective signal change curves, wherein the corresponding change curves of the first and second signals, or the corresponding signal shapes of the two signals, may be different from each other. Further preferably, the first and second signals each have a duty cycle corresponding to a value less than 100%. Particularly preferably, when the signals are generated simultaneously, the first and second signals each have a 50% duty cycle. When the first and second signals are generated in a time-staggered manner, the first and second signals preferably each have a 25% duty cycle.

[0018] In an advantageous configuration of the invention, the signal processing unit is configured to generate a first output signal by filtering the differential signal using a first filter (e.g., a low-pass filter and / or a band-pass filter), the passband of which is adapted to the frequency range of the applied signal. In the absence of faults or deviations in the circuit components, this signal corresponds accordingly to the applied signal, which can be directly supplied to further processing, for example, in an unbiased state in downstream processing within and / or outside the circuit components according to the invention. Furthermore, the signal processing unit is configured to generate a second output signal by filtering the differential signal using a second filter (e.g., a band-pass filter and / or a high-pass filter), the passband of which is adapted to the frequency range of the first and second signals. Particularly advantageously, the second filter is configured as a bandpass filter, the center frequency of which corresponds to the fundamental frequency of the first and second signals.

[0019] When the first signal and the second signal are generated simultaneously, the signal processing unit is preferably configured to identify the fault state of the circuit component and / or the cause of the fault state and / or the deviation state of the circuit component based on the height and / or polarity of the first output signal and / or the second output signal, wherein there is a deviation between the first impedance and the second impedance and / or a deviation between the first signal and the second signal.

[0020] Based on the height and / or polarity of the first and / or second output signals, the fault states and / or deviation states described in the table below can be determined, wherein the supply voltage mentioned therein is the voltage used to supply the application network.

[0021] Furthermore, the table shows that, based on the simultaneously generated first and second signals, a short circuit between the first and second interfaces cannot be definitively and uniquely determined, because the first and second output signals do not have voltage in this case, just as they would under fault-free conditions.

[0022] When the first signal and the second signal are generated simultaneously, the circuit assembly is further preferably configured to alternately inject the first signal into the first impedance and the second impedance, and alternately inject the second signal into the corresponding other impedance. In this case, the circuit assembly is also advantageously configured to distinguish, based on information about the alternating injection of signals into the corresponding impedances and based on the second output signal, whether the deviation state is caused by a deviation between impedances or by a deviation between signals.

[0023] When the first and second signals are generated simultaneously, the circuit components are further preferably configured to at least partially correct the deviation state by adapting the amplitudes of the first and / or second signals. This adaptation is preferably based on feedback from the second output signal to the first and / or second current source, so as to compensate for the deviation state by adapting the first and / or second signals. Alternatively or additionally, the circuit components are further preferably configured to at least partially correct the deviation state by obtaining high-level information about the influence of the first and / or second signals on the applied signal based on the second signal, and using this information to correct the first output signal. By correcting the first output signal, the first output signal corresponds to the undistorted applied signal after correction.

[0024] In another advantageous configuration of the invention, in the case where the first and second signals are generated at time-staggered intervals, the signal processing unit is configured to generate a third output signal by filtering the differential signal using a third filter whose passband is adapted to a frequency corresponding to twice the fundamental frequency of the first and second signals. The signal processing unit is further configured to identify a fault state and / or the cause of the fault state and / or a deviation state of the circuit components based on the height of the second output signal and based on the height and / or polarity of the third output signal, wherein a deviation exists between the first and second impedances and / or between the first and second signals. Here, preferably, the duty cycles of the first and second signals are respectively 25%, but not limited to such duty cycles.

[0025] When the first and second signals are generated at staggered times, the first and second current sources are preferably the same current source, and the first and second signals are preferably the same signal. Furthermore, the circuit assembly is configured to alternately inject the signal generated by the current source into the first impedance as the first signal and into the second impedance as the second signal. This avoids a misalignment state, in which the first and second signals could have different amplitudes due to the use of separate current sources.

[0026] Based on the height and / or polarity of the second and third output signals, the fault states and / or deviation states described in the table below can be determined, wherein the supply voltage is the voltage used to supply the application network. Furthermore, the table below exemplarily uses a single current source configured to generate a first signal and alternately inject that first signal into a first impedance and a second impedance.

[0027] In the case where the first and second signals are generated at time-staggered intervals, the signal processing unit is particularly advantageously configured to detect a short circuit between the first and second interfaces when the second and third output signals each have zero amplitude, i.e., zero voltage. Alternatively or additionally, the circuit components are configured to at least partially correct the deviation state by obtaining high-level information about the influence of the first and second signals on the application signal based on the third output signal, and using this information about the high-level influence to correct the first output signal. The corrected first output signal corresponds accordingly to the undistorted application signal in the corrected state. Attached Figure Description

[0028] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the drawings: Figure 1 An exemplary embodiment of a circuit component according to the present invention is shown; Figure 2 Exemplary signal variation curves of the first and second signals generated simultaneously are shown; and Figure 3 An exemplary signal variation curve is shown for a first signal and a second signal that are generated at different times. Detailed Implementation

[0029] Figure 1 An exemplary embodiment of a circuit assembly according to the present invention is shown, the circuit assembly having an application network 10, a first current source 20, a second current source 25, a differential readout circuit 30, and a signal processing unit 40, wherein the application network is a component of a temperature sensor configured to generate an application signal SA, the application signal SA representing a temperature measurement value of the temperature sensor.

[0030] Application network 10 is configured to provide application signal SA to a receiver via a first interface 11 and a second interface 12, wherein the receiver is, for example, an ASIC that may contain at least a portion of the following components.

[0031] The first current source 20 of the circuit assembly is configured to inject a first predefined signal S1 into a first impedance of the application network 10 coupled to the first interface 11 via the first interface 11. The second current source 25 is configured to inject a second predefined signal S2 into a second impedance of the application network 10 coupled to the second interface 12 via the second interface 12, wherein the duration and fundamental frequency of the first signal S1 and the second signal S2 are the same.

[0032] The first current source 20 and the second current source 25 are configured to simultaneously inject the first signal S1 and the second signal S2 into the first impedance and the second impedance, such that the signal change curves of the first signal S1 and the second signal S2 are the same or differ only in amplitude due to the scaling factor.

[0033] The first current source 20 and the second current source 25 are further configured to inject the first signal S1 and the second signal S2 into the first impedance and the second impedance in a time-staggered manner, wherein the second signal S2 is located in time between two consecutive first signals S1, and wherein a predefined dead time T is observed between the respective first signal S1 and the second signal S2.

[0034] Not only are the first signal S1 and the second signal S2 generated simultaneously, but the first signal S1 and the second signal S2 generated at different times also have rectangular shapes. The signals S1 and S2 generated simultaneously each have a duty cycle of 50%, and the signals generated at different times each have a duty cycle of 25%.

[0035] In addition, the application signal SA of the application network 10 is located in the following frequency range: this frequency range does not intersect with the frequency range of the first signal S1 and the second signal S2 in the target state of the circuit components.

[0036] The differential readout circuit 30 has an amplifier 80 for amplifying the differential signal SD and an A / D converter 90 for digitizing the amplified differential signal SD, wherein the differential signal SD is generated by a voltage applied to a first interface 11 and a voltage applied to a second interface 12.

[0037] The signal processing unit 40 is configured to generate a first output signal SO1 by filtering the differential signal SD with a first filter 50. The first filter is constructed as a low-pass filter and has a passband that is adapted to the frequency range of the application signal SA.

[0038] The signal processing unit 40 is further configured to generate a second output signal SO2 by filtering the differential signal SD with the aid of a second filter 60. The second filter is constructed as a bandpass filter and has a center frequency that corresponds to the fundamental frequency of the first signal S1 and the second signal S2.

[0039] The signal processing unit 40 is further configured to generate a third output signal SO3 by filtering the differential signal SD with the aid of a third filter 70. The third filter is also constructed as a bandpass filter and has a center frequency that corresponds to a frequency that is twice the fundamental frequency of the first signal S1 and the second signal S2.

[0040] Based on the analysis and processing logic 45 of the received output signals SO1, SO2, and SO3, the signal processing unit 40 is configured to calculate the deviation between the circuit components and the target state, wherein the deviation may represent impedance deviation and / or signal deviation and / or fault state. The deviation calculated according to the present invention can be used in the deviation compensation unit 110 of the analysis and processing logic 40 to correct the effect of the deviation state on the first output signal SO1, so that the application signal SA can be recovered based on the corrected output signal SO1, which can then be output to a downstream processing chain (not shown) for the application signal SA.

[0041] The analysis and processing logic 45 is further configured to determine the specific cause of the deviation and / or fault and output the relevant information as a fault signal SF.

[0042] In addition, the circuit components according to the invention are configured to guide the second output signal SO2 back to the first current source 20 and / or the second current source 25 via feedback control 100, so as to compensate for the deviation between the first signal S1 and the second signal S2 and / or the deviation between the first impedance and the second impedance by means of adjustment based on the feedback.

[0043] Figure 2 An exemplary signal variation curve of a first signal S1 and a second signal S2 generated simultaneously is shown. The first and second signals are respectively constructed as rectangular signals and each has a 50% duty cycle, which is generated by a dead time T.

[0044] In addition, Figure 2The diagram shows a differential signal SD generated according to the present invention, which is subjected to the unexpected influence of a first signal S1 and / or a second signal S2 due to a fault event 120.

[0045] Figure 3 An exemplary signal variation curve is shown for a first signal S1 and a second signal S2 that are generated in time staggered. The first and second signals are respectively constructed as rectangular signals and have a duty cycle of 25% respectively, and have a dead time T between the first signal S1 and the second signal S2.

[0046] In addition, Figure 3 The diagram shows a differential signal SD generated according to the present invention, which is subjected to the unexpected influence of a first signal S1 and / or a second signal S2 due to a fault event 120.

Claims

1. A circuit component having - Application Network (10) - First current source (20). - Second current source (25). - Differential readout circuit (30), and - Signal processing unit (40). in, - The application network (10) is configured to provide application signals (SA) via a first interface (11) and a second interface (12). - The first current source (20) is configured to inject a first predefined signal (S1) into a first impedance of the application network (10) coupled to the first interface (11) via the first interface (11). - The second current source (25) is configured to inject a second predefined signal (S2) into the second impedance of the application network (10) coupled to the second interface (12) via the second interface (12). - The duration and fundamental frequency of the first signal (S1) and the second signal (S2) are the same. - The first current source (20) and the second current source (25) are configured to transmit the first signal (S1) and the second signal (S2). - Simultaneously injected into the first impedance and the second impedance, such that the signal change curves of the first signal (S1) and the second signal (S2) are the same, or because the scaling factor differs only in its amplitude, or - The signal is injected into the first impedance and the second impedance in a time-staggered manner, wherein the second signal (S2) is located in time between two consecutive first signals (S1), and wherein a predefined dead time (T) is observed between the respective first signals (S1) and the second signal (S2). - The application signal (SA) of the application network (10) is located in a frequency range that does not intersect with the frequency ranges of the first signal (S1) and the second signal (S2) in the target state of the circuit component. - The differential readout circuit (30) is configured to be based on - The voltage applied to the first interface (11) and the voltage applied to the second interface (12) generate a differential signal (SD), and - The signal processing unit (40) is configured to calculate the deviation between the circuit component and the target state based on the differential signal (SD).

2. The circuit assembly according to any one of the preceding claims, wherein, The application signal (SA) of the application network (10) - Essentially a DC voltage signal, and / or - This is the signal provided by the sensor, especially the low-frequency signal.

3. The circuit assembly according to any one of the preceding claims, wherein, The first signal (S1) and the second signal (S2) - These are rectangular signals, and / or - In the case where the first signal and the second signal are signals generated at time staggered (S1, S2), they have the same or substantially the same area under their respective signal change curves, and / or - Each has a duty cycle corresponding to a value less than 100%.

4. The circuit assembly according to any one of the preceding claims, wherein, The signal processing unit (40) is configured as follows: - A first output signal (SO1) is generated by filtering the differential signal (SD) using a first filter (50), the passband of which is adapted to the frequency range of the applied signal (SA), and - A second output signal (SO2) is generated by filtering the differential signal (SD) with the aid of a second filter (60), the passband of which is adapted to the frequency range of the first signal (S1) and the second signal (S2).

5. The circuit assembly according to claim 4, wherein, In the case of simultaneous generation of a first signal (S1) and a second signal (S2), the signal processing unit (40) is configured to, based on the height and / or polarity of the first output signal (S1) and / or the second output signal (S2), - Identify the fault condition of the circuit components, and / or - Identify the cause of the aforementioned fault condition, and / or - Identify the deviation state of the circuit components, in which there is a deviation between the first impedance and the second impedance and / or a deviation between the first signal (S1) and the second signal (S2).

6. The circuit assembly according to claim 5, wherein, The circuit components are configured as follows: - The first signal (S1) is alternately injected into the first impedance and the second impedance, and the second signal (S2) is alternately injected into the corresponding other impedance, and - Based on information about alternately injecting the signals (S1, S2) into the corresponding impedances and based on the second output signal (SO2), it is distinguished whether the deviation state is caused by a deviation between impedances or by a deviation between signals (S1, S2).

7. The circuit assembly according to any one of claims 4 to 6, wherein, The circuit assembly is configured to at least partially correct the deviation state in the following manner: - Adapting the amplitude of the first signal (S1) and / or the second signal (S2), and / or - Based on the second signal (S2), obtain high-level information about the influence of the first signal (S1) and / or the second signal (S2) on the application signal (SA), and use the information to correct the first output signal (SO1).

8. The circuit assembly of claim 4, wherein, In the case where the first signal (S1) and the second signal (S2) are generated at different times, the signal processing unit (40) is configured to, - A third output signal (SO3) is generated by filtering the differential signal (SD) using a third filter (70), the passband of which is adapted to a frequency corresponding to twice the fundamental frequency of the first signal (S1) and the second signal (S2). - Based on the height of the second output signal (SO2) and based on the height and / or polarity of the third output signal (SO3). - Identify the fault condition of the circuit components, and / or - Identify the cause of the aforementioned fault condition, and / or - Identify the deviation state of the circuit component, in which there is a deviation between the first impedance and the second impedance and / or a deviation between the first signal and the second signal.

9. The circuit assembly of claim 8, wherein, - The first current source (20) and the second current source (25) are the same current source (20), and the first signal (S1) and the second signal (S2) are the same signal (S1), and - The circuit assembly is configured to alternately inject the signal (S1) generated by the current source (20) into the first impedance as a first signal (S1) and into the second impedance as a second signal (S2).

10. The circuit assembly according to claim 8 or 9, wherein, - The signal processing unit (40) is configured to detect a short circuit between the first interface (11) and the second interface (12) when the second output signal (SO2) and the third output signal (SO3) each have an amplitude of zero, and / or - The circuit assembly is configured to at least partially correct the deviation state by obtaining high-level information about the influence of the first signal (S1) and the second signal (S2) on the applied signal (SA) based on the third output signal (SO3), and using the high-level information about the influence to correct the first output signal (SO1).

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