Photoelectric co-packaging module based on advanced packaging

Abstract

The utility model discloses a photoelectric co-packaging module group based on advanced packaging. The photoelectric co-packaging module group comprises a photoelectric intermediary substrate; the optical chip and the electric chip are located on the first surface of the photoelectric intermediary substrate and are electrically connected through the photoelectric intermediary substrate; the circuit board is located on the second surface of the photoelectric intermediary substrate and is electrically connected with the optical chip and the electric chip through the photoelectric intermediary substrate; the optical fiber array component is positioned on the first surface of the photoelectric intermediary substrate and is coupled with the photoelectric intermediary substrate; a grating coupler and a first optical waveguide are arranged in the photoelectric intermediary substrate and are used for transmitting optical signals between the optical fiber array component and the optical chip; the optical chip comprises a waveguide layer and a device layer, and optical interconnection between the waveguide layer and the device layer adopts evanescent wave coupling. According to the technical scheme provided by the utility model, the problems that the high-speed optical module is large in high-frequency loss, low in integration level and small in heat dissipation area are solved, and meanwhile, the problem that the optical port of the optical chip is difficult to protect in the advanced packaging process is solved.

Description

Technical Field

[0001] The embodiment of the utility model relates to the technical field of optoelectronic hybrid integration, and in particular to an optoelectronic co-sealing module based on advanced packaging. Background Art

[0002] With the rapid development of cloud computing, big data, high-definition video and VR technology, broadband has put forward higher requirements on the capacity of switching equipment, making high-speed and high-density optical interconnection the basis for building future high-speed networks. To achieve high-density optical interconnection, optical modules with high data capacity are the key.

[0003] At present, the TX / RX chips in the commonly used pluggable optical modules and CPO (Co-packaged Optics) products are mainly packaged in COB (Chips on Board), the pad of the internal chip is a positive structure, and the signal connection between the chip and the PCB (Printed Circuit Board) is realized by wire bonding; the COB packaging solution leads to low integration of the internal chip and difficult heat dissipation; at the same time, due to the shape limitation of the gold wire, the impedance matching is difficult, the bandwidth of the COB packaged optical module is low, and as the number of module channels increases, the accumulated power loss will also increase; advanced packaging is relatively mature in chiplet and other technologies, and it has great performance advantages in terms of channel number and bandwidth; however, for the optical chip inside the optical module or used for transmission between modules, the injection molding and polishing processes in the advanced packaging process are very easy to damage and pollute the optical port, introducing additional losses in the optical transmission system; the structures such as bump and BGA (Ball Grid Array) in the advanced packaging introduce multiple material systems, so the traditional method of using tungsten copper substrate to carry PIC (Photonics Integrated The packaging form of integrated photonic circuit (IC) optical chip and FA (Fiber Array) is no longer applicable; manufacturing TSV (Through Silicon Via) on the SOI (Silicon On Insulator) wafer of PIC optical chip is one of the advanced packaging solutions for optoelectronic co-sealing, but TSV will introduce large warping in the SOI device layer, which will affect the performance of active devices on the PIC. Utility Model Content

[0004] The embodiment of the utility model provides an optoelectronic co-sealed module based on advanced packaging to improve the problems of high-frequency loss, low integration, small heat dissipation area, etc. of high-speed optical modules, while solving the technical difficulties of PIC optical port protection in the advanced packaging process.

[0005] The utility model provides an optoelectronic co-sealing module based on advanced packaging, comprising:

[0006] An optoelectronic interposer substrate including a first surface and a second surface opposite to each other;

[0007] An optical chip and an electrical chip; the optical chip and the electrical chip are located on the first surface of the optoelectronic intermediary substrate and are both electrically connected to the optoelectronic intermediary substrate, and the electrical connection between the optical chip and the electrical chip is achieved through the optoelectronic intermediary substrate;

[0008] A PCB circuit board, the PCB circuit board is located on the second surface of the optoelectronic intermediate substrate and is electrically connected to the optoelectronic intermediate substrate, and is electrically connected to both the optical chip and the electrical chip through the optoelectronic intermediate substrate;

[0009] An optical fiber array assembly is located on the first surface of the optoelectronic intermediary substrate and is coupled to the grating coupler in the optoelectronic intermediary substrate;

[0010] Among them, a grating coupler and a first optical waveguide are arranged in the optoelectronic interposer substrate, the grating coupler and the first optical waveguide are coupled and connected, and the first optical waveguide extends from the area corresponding to the grating coupler to the area corresponding to the optical chip; the optical chip includes a waveguide layer and a device layer, the waveguide layer and the device layer are coupled through evanescent waves, the waveguide layer is coupled and connected to the first optical waveguide, and the grating coupler and the first optical waveguide are used to transmit the optical signal transmitted between the optical fiber array component and the optical chip.

[0011] Optionally, the optoelectronic intermediate substrate comprises a silicon substrate and a first dielectric layer and a second dielectric layer located on opposite sides of the silicon substrate;

[0012] Wherein, the surface of the first dielectric layer away from the silicon substrate is the first surface; the surface of the second dielectric layer away from the silicon substrate is the second surface; the material of the first dielectric layer and the second dielectric layer includes silicon dioxide;

[0013] The grating coupler and the first optical waveguide are arranged in the first dielectric layer.

[0014] Optionally, in the optical chip, the waveguide layer includes a second optical waveguide; the device layer includes at least a functional module;

[0015] The end of the first optical waveguide and the end of the second optical waveguide are coupled and connected; the first optical waveguide and the second optical waveguide are used to form an optical path; the functional module is used to receive an optical signal input through the optical path and perform preset processing on the optical signal.

[0016] Optionally, the device layer further comprises a third optical waveguide; the third optical waveguide is used to transmit an optical signal between the functional module and the second optical waveguide;

[0017] The first optical waveguide is provided with a first waveguide coupler at an end close to the second optical waveguide; the first end of the second optical waveguide is provided with a second waveguide coupler, the second end of the second optical waveguide is provided with a third waveguide coupler; the end of the third optical waveguide close to the second optical waveguide is provided with a fourth waveguide coupler;

[0018] The first waveguide coupler and the second waveguide coupler are coupled and connected to complete the transmission of optical signals between the first optical waveguide and the second optical waveguide; the third waveguide coupler and the fourth waveguide coupler are coupled and connected to complete the transmission of optical signals between the second optical waveguide and the third optical waveguide;

[0019] The material of the first optical waveguide includes SiN, the material of the second optical waveguide includes SiN, and the material of the third optical waveguide includes Si.

[0020] Optionally, the electrical chip is used to drive and control the optical chip; and / or, the electrical chip is used to receive the electrical signal converted by the detector in the optical chip to amplify and demodulate the electrical signal;

[0021] The surface of the optical chip is provided with a solder pad, and the first surface of the optoelectronic intermediate substrate is exposed with the solder pad; the surface of the electrical chip is provided with a conductive bump, and the first surface of the optoelectronic intermediate substrate is exposed with a conductive bump; the conductive bump on the surface of the electrical chip is fixedly connected to the conductive bump on the first surface of the optoelectronic intermediate substrate by a flip-packaging method;

[0022] The optical chip and the electrical chip are electrically connected via a conductive path in the optoelectronic interposer substrate.

[0023] Optionally, a top surface of a solder pad disposed on the surface of the optical chip is higher than a surface of a cladding layer in the optical chip.

[0024] Optionally, the PCB circuit board is electrically connected to both the optical chip and the electrical chip at least through a conductive through hole in the optoelectronic intermediate substrate;

[0025] The PCB circuit board is used to provide electrical signals for the optical chip and the electrical chip to work; and / or the PCB circuit board is used to output electrical signals processed by the electrical chip.

[0026] The technical solution provided by the embodiment of the utility model is to form an optoelectronic co-sealed module through advanced packaging technology, replacing the COB packaging technology. In this solution, no leads are required to achieve electrical connection, so the problems of large high-frequency loss, low integration and small heat dissipation area of ​​the existing optoelectronic co-sealed module can be effectively improved; moreover, the utility model introduces a waveguide layer into the PIC optical chip, and low insertion loss optical coupling can be achieved between the waveguide layer and the active device layer through evanescent wave coupling light; in addition, the first waveguide and the grating coupler are embedded in the optoelectronic intermediate substrate through the Damascus process, the grating coupler in the optoelectronic intermediate substrate is aligned with the optical fiber array component, the first optical waveguide extends from the area corresponding to the grating coupler to the area corresponding to the optical chip, and the first waveguide is only used as a passive optical link, which not only reduces the difficulty of the TSV process, but also ensures the quality of optical transmission, avoids the injection molding and polishing processes that are very easy to damage and pollute the optical port, and introduces additional losses in the optical transmission system, thereby solving the technical difficulty of difficult protection of the PIC optical port in the advanced packaging process.

[0027] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present utility model, nor are they intended to limit the scope of the present utility model. Other features of the present utility model will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 It is a schematic cross-sectional structure diagram of an optoelectronic co-sealing module based on advanced packaging provided by an embodiment of the utility model;

[0030] Figure 2 yes Figure 1 A schematic diagram of the structure of the optoelectronic interposer substrate in the structure shown;

[0031] Figure 3 yes Figure 1 A schematic diagram of the structure of the optical chip in the structure shown;

[0032] Figure 4 yes Figure 1 a top view of the structure shown;

[0033] Figure 5 It is a structural block diagram of an optoelectronic co-sealing module based on advanced packaging provided by an embodiment of the utility model;

[0034] Figure 6 to Figure 23 It is a schematic cross-sectional structure diagram of step S1120 in a method for preparing an optoelectronic co-sealed module based on advanced packaging provided by an embodiment of the utility model;

[0035] Figures 24 to 30 It is a schematic diagram of the cross-sectional structure in step S1130 in a method for preparing an optoelectronic co-sealed module based on advanced packaging provided by an embodiment of the present utility model. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the utility model and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the utility model described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0038] As mentioned in the background technology, high-speed and large-capacity optical interconnection has become the basis for building future high-speed networks. To achieve high-capacity optical interconnection, optical modules with high data capacity are the key. For pluggable optical modules, the increase in the rate of a single optical module also means an increase in the number of internal optoelectronic chips. How to achieve the interconnection of multiple chips and multiple transceiver channels while meeting the existing optical module housing and rate standards, and reduce the power consumption and signal loss of optical modules, is an important technical challenge facing optical modules.

[0039] The utility model inventor discovered during the research on the packaging form of optical modules that the power consumption, delay and bandwidth limitation of existing high-speed optical modules are mainly caused by the cumulative number of leads due to the increased integration of the COB packaging method. Currently, the TX / RX chips inside the commonly used pluggable optical modules and CPO products are mainly COB-packaged. The pad of the internal chip is a positive structure, and the signal connection between the chip and the PCB is achieved through wire bonding. The COB solution leads to a low integration of the internal chip and difficult heat dissipation. At the same time, due to the shape limitation of the gold wire, impedance matching is difficult, and the bandwidth of the COB-packaged optical module is low. As the number of module channels increases, the cumulative power consumption loss will also increase. Advanced packaging has great performance advantages in terms of the number of channels and bandwidth, and the use of advanced packaging methods can effectively improve the above problems.

[0040] However, for optical chips inside optical modules or used for transmission between modules, the injection molding and polishing processes in advanced packaging processes are very likely to damage and contaminate the optical ports, introducing additional losses in the optical transmission system; structures such as bumps and BGAs in advanced packaging introduce multiple material systems, so the traditional packaging form of using a tungsten-copper substrate to carry PIC and FA is no longer applicable; manufacturing TSV on the SOI wafer of the PIC chip is one of the advanced packaging solutions for optoelectronic co-sealing, but TSV will introduce a large warp in the SOI device layer, which will affect the performance of the active devices on the PIC.

[0041] In view of this, the embodiment of the utility model provides an optoelectronic co-sealing module based on advanced packaging. Figure 1 is a schematic cross-sectional structure diagram of an optoelectronic co-sealing module based on advanced packaging provided by an embodiment of the utility model, Figure 2 yes Figure 1 A schematic diagram of the structure of the optoelectronic interposer substrate in the structure shown, Figure 3 yes Figure 1 The schematic diagram of the structure of the optical chip in the structure shown, Figure 4 yes Figure 1 A top view of the structure shown, see Figure 1 to Figure 4 , optoelectronic co-sealing modules based on advanced packaging include:

[0042] The optoelectronic intermediary substrate 4 includes a first surface and a second surface opposite to each other;

[0043] The optical chip 1 and the electrical chip 2 are located on the first surface of the optoelectronic intermediary substrate 4 and are both electrically connected to the optoelectronic intermediary substrate 4, and the electrical connection between the optical chip 1 and the electrical chip 2 is achieved through the optoelectronic intermediary substrate 4;

[0044] PCB circuit board 5, the PCB circuit board 5 is located on the second surface of the optoelectronic intermediate substrate 4 and is electrically connected to the optoelectronic intermediate substrate 4, and is electrically connected to the optical chip 1 and the electrical chip 2 through the optoelectronic intermediate substrate 4;

[0045] The optical fiber array assembly 3 is located on the first surface of the optoelectronic intermediary substrate 4 and is coupled to the grating coupler in the optoelectronic intermediary substrate 4;

[0046] Among them, a grating coupler 18 and a first optical waveguide 15 are arranged in the optoelectronic intermediary substrate 4, the grating coupler 18 is coupled to the first optical waveguide 15, and the first optical waveguide 15 extends from the area corresponding to the grating coupler 18 to the area corresponding to the optical chip 1; the optical chip 1 includes a waveguide layer 110 and a device layer 100, and the optical interconnection between the waveguide layer 110 and the device layer 100 adopts evanescent wave coupling, the waveguide layer 110 is coupled to the first optical waveguide 15, and the grating coupler 18 and the first optical waveguide 15 are used to transmit the optical signal transmitted between the optical fiber array component 3 and the optical chip 1.

[0047] Specifically, the optical chip 1 realizes the mutual conversion function between optical signals and electrical signals in the field of optical communication technology. The optical chip 1 includes an optical port and an electrical port. The optical chip 1 realizes optical communication with information transmission equipment such as optical fiber or optical waveguide through the optical port, and realizes electrical connection with the optical network terminal (for example, optical modem) through the electrical port. The electrical connection is mainly used for power supply, I2C signal transmission, data information transmission and grounding. The electrical chip 2 can be a driver chip for driving the optical chip 1, or a trans-impedance amplifier (TIA) chip for trans-impedance amplification, or a switch chip, a processing chip or a storage chip.

[0048] The optoelectronic intermediary substrate 4 includes two passive links, optical and electrical. The optical fiber array assembly 3, the optical chip 1 and the electrical chip 2 are all located on the first surface of the optoelectronic intermediary substrate 4. The optical signal between the optical fiber array assembly 3 and the optical chip 1 is transmitted through the optical path in the optoelectronic intermediary substrate 4; the electrical signal between the optical chip 1 and the electrical chip 2 is transmitted through the electrical path in the optoelectronic intermediary substrate 4. The PCB circuit board 5 is fixedly connected to the second surface of the optoelectronic intermediary substrate 4. The PCB circuit board 5 is electrically connected to the optical chip 1 and the electrical chip 2 through the electrical path in the optoelectronic intermediary substrate 4. Among them, the optical path includes a grating coupler 18 for coupling with the optical fiber array assembly 3 and a passive waveguide (first optical waveguide 15) for optical transmission. The electrical path may include copper pads located on the surface of the optoelectronic intermediary substrate 4 (for example, copper pads 21 located on the first surface), bumps (for example, bumps 22 located on the first surface, bumps 23 located on the second surface), wiring layers located in the optoelectronic intermediary substrate 4 (for example, upper wiring layer 16, lower wiring layer 17), and through holes passing through the optoelectronic intermediary substrate 4; conductive material is arranged in the through hole, forming, for example, a Cu channel 20.

[0049] Optionally, the surface of the optical chip 1 is provided with a pad, and the first surface of the optoelectronic intermediate substrate 4 exposes the pad; the pad on the surface of the optical chip 1 is fixedly connected to the pad on the first surface of the optoelectronic intermediate substrate 4 by hybrid bonding; optionally, the top surface of the pad provided on the surface of the optical chip 1 is higher than the surface of the cladding layer 8 in the optical chip 1. The surface of the electric chip 2 is provided with a conductive bump, and the first surface of the optoelectronic intermediate substrate 4 exposes the conductive bump; the conductive bump on the surface of the electric chip 2 is fixedly connected to the conductive bump on the first surface of the optoelectronic intermediate substrate 4 by flip-packaging. The PCB circuit board 5 is electrically connected to both the optical chip 1 and the electric chip 2 at least through the conductive through-hole in the optoelectronic intermediate substrate 4; the PCB circuit board 5 is used to provide electrical signals for the optical chip 1 and the electric chip 2 to work; and / or, the PCB circuit board 5 is used to output the electrical signal processed by the electric chip 2.

[0050] It is pointed out here that Figure 1 The structure shown in FIG. 1 is a cross-sectional view of a photovoltaic co-sealed module. Specifically, how many photovoltaic co-sealed modules are included in the photovoltaic co-sealed module? Figure 1 The cross-sectional structure shown can be set according to actual needs, specifically according to the number of I / O interfaces of the optoelectronic co-sealed module. However, when the PCB circuit board has the function of outputting the electrical signal processed by the electrical chip 2, the electrical signal processed by the electrical chip 2 and the link that provides the electrical signal for the optical chip 1 and the electrical chip 2 are two identical links, and the two can work in parallel, but they are not the same link.

[0051] The technical solution provided by the embodiment of the utility model forms an optoelectronic co-sealed module through advanced packaging technology, replacing the COB packaging technology, and can realize the electrical connection between different devices in the optoelectronic co-sealed module without wires, which can improve the problems of large high-frequency loss, low integration and small heat dissipation area of ​​the optoelectronic co-sealed module; moreover, with the gradual improvement of the manufacturing process of the PIC optical chip 1, the utility model introduces the waveguide layer 110 into the PIC optical chip 1, and can realize low insertion loss optical coupling between the waveguide layer 110 and the active device layer 100 through evanescent wave coupling light; in addition, the first optical waveguide 15 and the grating coupler 18 are embedded in the optoelectronic intermediate substrate 4 through the Damascus process to form an optoelectronic intermediate substrate 4 having the first optical waveguide 15 and the grating coupler 18. The grating coupler 18 in the optoelectronic intermediate substrate 4 is aligned with the optical fiber array assembly 3, and the first optical waveguide 15 extends from the position of the grating coupler 18 to the position of the optical chip 1. The first optical waveguide 15 only serves as a passive optical link, which not only reduces the difficulty of the TSV process, but also ensures the quality of optical transmission, avoids the problem that the injection molding and polishing processes are very easy to damage and pollute the optical port, and introduces additional losses in the optical transmission system, thereby solving the technical difficulty of protecting the PIC optical port in the advanced packaging process.

[0052] The above is the core utility model concept of the present utility model. The components in the optoelectronic co-sealing module are described in detail below in conjunction with the accompanying drawings.

[0053] Based on the above embodiments, in one embodiment of the present utility model, reference Figure 2 The optoelectronic intermediate substrate 4 includes a silicon substrate 41 and a first dielectric layer 42 and a second dielectric layer 43 located on opposite sides of the silicon substrate 41; the materials of the first dielectric layer 42 and the second dielectric layer 43 include silicon dioxide;

[0054] Among them, the surface of the first dielectric layer 42 away from the silicon substrate 41 is the first surface; the surface of the second dielectric layer 43 away from the silicon substrate 41 is the second surface; the grating coupler 18 and the first optical waveguide 15 are arranged in the first dielectric layer 42 to reduce the path length of the optical path and facilitate the transmission of the optical signal between the optical fiber array component 3 and the optical chip 1. The material of the grating coupler 18 and the first optical waveguide 15 includes SiN. The wiring layer in the optoelectronic interposer substrate 4 is located in the first dielectric layer 42 and the second dielectric layer 43. The material of the wiring layer includes a metal material. The wiring layer located in the first dielectric layer 42 is the upper wiring layer 16, and the wiring layer located in the second dielectric layer 42 is the lower wiring layer 17.

[0055] Based on the above embodiments, in one embodiment of the present invention, reference is made to Figure 3 , and combined with Figure 1 , Figure 2 and Figure 4 , in the optical chip 1, the waveguide layer 110 includes the second optical waveguide 11; the device layer 100 includes the third optical waveguide 10 and the functional module 7. That is, the optical chip 1 includes the functional module 7 and the second optical waveguide 11 and the third optical waveguide 10 arranged in different layers; the end of the first optical waveguide 15 is coupled to one end of the second optical waveguide 11, the end of the third optical waveguide 10 is coupled to the other end of the second optical waveguide 11, and the first optical waveguide 15, the second optical waveguide 11 and the third optical waveguide 10 are used to form an optical path. In other embodiments of the utility model, the device layer 100 may only include the functional module 7, and the optical path is formed by the first optical waveguide 15 and the second optical waveguide 11.

[0056] Functional module 7 is used to receive an optical signal input through an optical path and perform a preset process on the optical signal. Exemplarily, functional module 7 is used to receive an optical signal input from an optical path and convert the optical signal into an electrical signal, or functional module 7 is used to modulate an optical signal and output the modulated optical signal to the optical path.

[0057] Specifically, a waveguide layer 110 and a device layer 100 are provided in different layers in the cladding layer 8 of the optical chip 1, and the second optical waveguide 11 is located in the waveguide layer 110, and the material of the second optical waveguide 11 includes SiN. The third optical waveguide 10 and the functional module 7 are located in the device layer 100. The materials of the third optical waveguide 10 and the functional module 7 include Si. The functional module 7 is bonded to the pad 21 on the first surface of the optoelectronic interposer substrate 4 through the pad 9. The second optical waveguide 11 is coupled to the first optical waveguide 15 and the third optical waveguide 10. As an optional embodiment, the vertical projection of the second optical waveguide 11 on the silicon substrate 41 may be arranged between the vertical projection of the first optical waveguide 15 on the silicon substrate 41 and the vertical projection of the third optical waveguide 10 on the silicon substrate 41, and the first end of the second optical waveguide 11 is coupled to the end of the first optical waveguide 15, such as the vertical projections of the two on the silicon substrate 41 overlap; the second end of the second optical waveguide 11 is coupled to the end of the third optical waveguide 10, such as the vertical projections of the two on the silicon substrate 41 overlap, so as to ensure that the first optical waveguide 15, the second optical waveguide 11 and the third optical waveguide 10 form an optical path.

[0058] Among them, a first waveguide coupler 19 is provided at the end of the first optical waveguide 15 close to the second optical waveguide 11; a second waveguide coupler 14 is provided at the first end of the second optical waveguide 11, and a third waveguide coupler 13 is provided at the second end of the second optical waveguide 11; a fourth waveguide coupler 12 is provided at the end of the third optical waveguide 10 close to the second optical waveguide 11; the first waveguide coupler 19 and the second waveguide coupler 14 are coupled and connected to complete the transmission of optical signals between the first optical waveguide 15 and the second optical waveguide 11; the third waveguide coupler 13 and the fourth waveguide coupler 12 are coupled and connected to complete the transmission of optical signals between the second optical waveguide 11 and the third optical waveguide 10. As an optional embodiment, the end of an optical waveguide 15 close to the second optical waveguide 11 can be set to a tip shape to serve as a first waveguide coupler 19. Similarly, the first end and the second end of the second optical waveguide 11 can be set to a tip structure to serve as a second waveguide coupler 14 and a third waveguide coupler 13, and the end of the third optical waveguide 10 close to the second optical waveguide 11 can be set to a tip shape to serve as a fourth waveguide coupler 12.

[0059] The optical path formed by the first optical waveguide 15, the second optical waveguide 11 and the third optical waveguide 10 can be used as an input optical path, and the functional module 7 is used to receive the optical signal input by the third optical waveguide 10, that is, to receive the optical signal of the optical fiber array component 3. The optical path formed by the first optical waveguide 15, the second optical waveguide 11 and the third optical waveguide 10 can also be used as an output optical path, and the functional module 7 is used to output the optical signal to the third optical waveguide 10, that is, to output the optical signal to the optical fiber array. It can be understood that in an optional embodiment of the utility model, the cladding layer 8 of the optical chip 1 contains two waveguide layers, namely the second waveguide layer 110 and the third waveguide layer, and the second waveguide layer can be provided with a plurality of second optical waveguides 11, and the third waveguide layer (which is part of the device layer 100) can be provided with a plurality of third optical waveguides 10; correspondingly, the optoelectronic intermediate substrate 4 includes a first waveguide layer, and the first waveguide layer includes a plurality of first optical waveguides 15. The second optical waveguide 11 is arranged in one-to-one correspondence with the first optical waveguide 15 and the third optical waveguide 10, so as to form a plurality of optical paths, some of which are light-incoming paths and some of which are light-outgoing paths.

[0060] On the basis of the above embodiments, optionally, the functional module 7 includes a detector, the first optical waveguide 15 includes a first optical input waveguide, the second optical waveguide 11 includes a second optical input waveguide, and the third optical waveguide 10 includes a third optical input waveguide; the first optical input waveguide, the second optical input waveguide and the third optical input waveguide are used to form an optical input path; the detector is used to receive an optical signal input by the optical input path and convert the optical signal into an electrical signal. As an optional embodiment, the number of detectors may be the same as the number of optical input paths.

[0061] And / or, the functional module 7 includes a modulator, the first optical waveguide 15 includes a first output optical waveguide, the second optical waveguide 11 includes a second output optical waveguide, and the third optical waveguide 10 includes a third output optical waveguide; the first output optical waveguide, the second output optical waveguide, and the third output optical waveguide work together to form an output optical path; the modulator is used to output the modulated optical signal to the output optical path. The number of modulators is the same as the number of output optical paths.

[0062] Figure 5 This is a structural block diagram of an optoelectronic co-sealing module based on advanced packaging provided by an embodiment of the utility model, with reference to Figure 5 , exemplarily showing that the optical chip includes four detectors 701 and four modulators 702. There is an input light path between each detector 701 and the optical fiber array assembly 3, and the electrical chip includes a transimpedance amplifier chip 201, which is used to receive the electrical signal converted by the detector 701 in the optical chip 1 and complete the subsequent amplification and demodulation. There is an output light path between each modulator 702 and the optical fiber array assembly 3, and the electrical chip includes a driver chip 202, which is used to drive and control the modulator in the optical chip 1 to complete the adjustment of the optical signal.

[0063] In summary, the optical fiber channel in the optical fiber array assembly 3 in the embodiment of the utility model is aligned and bonded with the SiN waveguide of the optoelectronic intermediate substrate 4 through active coupling, and the tip waveguide coupler 14 of the optical chip 1 and the tip waveguide coupler 19 on the optoelectronic intermediate substrate 4 are passively coupled by a high alignment precision bonding process; the light of the external light source and the high-speed optical signal is emitted through the optical fiber of the optical fiber array assembly 3, and then coupled into the SiN waveguide 15 in the optoelectronic intermediate substrate 4 through the grating coupler 18; the high-frequency optical signal is introduced into the SiN waveguide 11 of the optical chip 1 by using the tip waveguide couplers 14 and 19 made of SiN material; the above optical signal is further coupled into the Si waveguide 10 by using the tip waveguide couplers 12 and 13, and the optical signal is received by the detector in the optical chip 1. The optical signal modulated by the modulator is transmitted through the third optical waveguide 10 made of Si, the second optical waveguide 11 made of SiN, and the first optical waveguide 15 made of SiN in sequence using the tip-shaped fourth waveguide coupler 12, the third waveguide coupler 13, the second waveguide coupler 14, and the first waveguide coupler 19, and is output from the optical fiber array assembly 3 using the grating coupler 18.

[0064] Based on the above embodiments, in one embodiment of the present invention, reference is made to Figure 5 The optoelectronic co-sealed module based on advanced packaging also includes a laser 25; the optoelectronic intermediate substrate 4 also includes a first laser input optical waveguide; the optical chip 1 also includes a second laser input optical waveguide and a third laser input optical waveguide arranged in different layers (the arrangement of the first laser input optical waveguide, the second laser input optical waveguide and the third laser input optical waveguide can be referred to Figure 2 to Figure 4 The arrangement of the first optical waveguide 15, the second optical waveguide 11 and the third optical waveguide 13);

[0065] The first laser input optical waveguide, the second laser input optical waveguide and the third laser input optical waveguide are used to form a laser input path; wherein, the vertical projection of the second laser input optical waveguide on the silicon substrate 41 is located between the vertical projection of the first laser input optical waveguide on the silicon substrate 41 and the vertical projection of the third laser input optical waveguide on the silicon substrate 41, and the first end of the second laser input optical waveguide is coupled and connected with the end of the first laser input optical waveguide. As an optional implementation, the first end of the second laser input optical waveguide can be arranged to overlap with the vertical projection of the end of the first laser input optical waveguide on the silicon substrate 41. Similarly, the second end of the second laser input optical waveguide can be arranged to overlap with the vertical projection of the end of the third laser input optical waveguide on the silicon substrate 41, so that the second end of the second laser input optical waveguide and the end of the third laser input optical waveguide are coupled and connected.

[0066] The modulator 702 in the optical chip 1 is used to receive the laser signal from the third laser input optical waveguide and modulate the laser signal.

[0067] Specifically, the first laser input optical waveguide can be arranged in the same layer as the first optical waveguide 15, so that the first laser input optical waveguide and the first optical waveguide 15 can be prepared at the same time, simplifying the preparation process of the optoelectronic intermediate substrate 4. In addition, the second laser input optical waveguide can be arranged in the same layer as the second optical waveguide 11, and the third laser input optical waveguide can be arranged in the same layer as the third optical waveguide 10, so that the second laser input optical waveguide and the second optical waveguide 11 can be prepared at the same time, and the third laser input optical waveguide and the third optical waveguide 10 can be prepared at the same time, simplifying the preparation process of the optical chip 1.

[0068] Among them, the end of the first laser input optical waveguide close to the second laser input optical waveguide includes a first laser waveguide coupler; the first end of the second laser input optical waveguide includes a second laser waveguide coupler, and the second end of the second laser input optical waveguide includes a third laser waveguide coupler; the end of the third laser input optical waveguide close to the second laser input optical waveguide includes a fourth laser waveguide coupler; the first laser waveguide coupler and the second laser waveguide coupler are used to complete the transmission of optical signals between the first laser input optical waveguide and the second laser input optical waveguide; the third laser waveguide coupler and the fourth laser waveguide coupler are used to complete the transmission of optical signals between the second laser input optical waveguide and the third laser input optical waveguide.

[0069] In the embodiment of the utility model, a first laser input optical waveguide is further provided in the optoelectronic intermediate substrate 4; a second laser input optical waveguide and a third laser input optical waveguide are further provided in the optical chip 1, so that the optical loss of the laser input can be reduced.

[0070] Optionally, a beam splitting module 26 is further provided at the output end of the laser 25 for splitting the light output by the laser 25 into multiple paths, thereby reducing the number of lasers 25 in the optoelectronic co-sealed module.

[0071] The present utility model embodiment further provides a method for preparing an optoelectronic co-sealed module based on advanced packaging, which is used to prepare the optoelectronic co-sealed module based on advanced packaging described in any embodiment of the utility model, comprising:

[0072] S110, preparing a photoelectric intermediate substrate.

[0073] S120, fixing the optical chip and the electrical chip to the first surface of the optoelectronic intermediate substrate; the optical chip and the electrical chip are electrically connected through the optoelectronic intermediate substrate.

[0074] S130, fixing the PCB circuit board to the second surface of the optoelectronic intermediate substrate; the PCB circuit board is electrically connected to both the optical chip and the electrical chip through the optoelectronic intermediate substrate.

[0075] S140, disposing an optical fiber array assembly on the first surface of an optoelectronic intermediary substrate, wherein the optical fiber array assembly is coupled to a grating coupler; wherein a grating coupler and a first optical waveguide are disposed in the optoelectronic intermediary substrate, the grating coupler is coupled to the first optical waveguide, and the first optical waveguide extends from an area corresponding to the grating coupler to an area corresponding to the optical chip; the optical chip comprises a waveguide layer and a device layer, the waveguide layer and the device layer are coupled via evanescent waves, the waveguide layer is coupled to the first optical waveguide, and the grating coupler and the first optical waveguide are used to transmit an optical signal transmitted between the optical fiber array assembly and the optical chip.

[0076] The order of the above steps S120, S130, and S140 can be adjusted according to actual conditions.

[0077] The technical solution provided by the embodiment of the utility model can improve the problems of large high-frequency loss, low integration and small heat dissipation area of ​​the optoelectronic co-sealed module by packaging the optoelectronic co-sealed module through advanced packaging technology, replacing the COB packaging technology; and with the gradual improvement of the manufacturing technology of PIC optical chips, the utility model introduces the waveguide layer into the PIC optical chip, and can realize low insertion loss optical coupling between the waveguide layer and the active device layer through evanescent wave coupling light; in addition, the first waveguide and the grating coupler are embedded in the optoelectronic intermediate substrate through the Damascus process to form an optoelectronic intermediate substrate with the first waveguide and the grating coupler. The grating coupler in the optoelectronic intermediate substrate is arranged in alignment with the optical fiber array component, and the first optical waveguide extends from the position of the grating coupler to the position of the optical chip. The first waveguide only serves as a passive optical link, which not only reduces the difficulty of the TSV process, but also ensures the quality of optical transmission, avoids the problem that the injection molding and polishing processes are very easy to damage and pollute the optical port, and introduce additional losses in the optical transmission system, thereby solving the technical difficulty of the difficulty of protecting the PIC optical port in the advanced packaging process.

[0078] Optionally, the specific steps of preparing the optoelectronic intermediate substrate in step S110 include:

[0079] S1110, providing a silicon substrate;

[0080] S1120, forming a first dielectric layer on one side of the silicon substrate, and forming a grating coupler, a first optical waveguide and a wiring layer in the first dielectric layer;

[0081] S1130, forming a second dielectric layer on the far side of the silicon substrate, and forming a wiring layer in the second dielectric layer.

[0082] Specifically, step S1120 forms a first dielectric layer on one side of the silicon substrate, and forms a grating coupler, a first optical waveguide and a wiring layer in the first dielectric layer, specifically including:

[0083] refer to Figure 6, a first silicon oxide material layer 4211 and a first photoresist layer 4221 are sequentially formed on the front surface of the silicon substrate 41, and the first photoresist layer 4221 is patterned to form a first opening Q1 and a second opening Q2 exposing the first silicon oxide material layer 4211 in the first photoresist layer 4221; Figure 7 , etching the first silicon oxide material layer 4211 exposed by the first opening Q1 and the second opening Q2, and continuing to etch the silicon substrate 41 to a first preset position, forming a first groove G1 and a second groove G2 in the silicon substrate 41; Figure 8 After removing the first photoresist layer 4221, a first metal layer 4231, such as a Cu / Ti layer, is formed on the surface of the first silicon oxide material layer 4211 and the surface of the etched groove; Fig. 9 , forming a second metal layer 4232, such as a Cu layer, on the surface of the first metal layer 4231, and the second metal layer 4232 fills the etched groove; Fig.10 , remove the second metal layer 4232 and the first metal layer 4231 outside the groove, and expose the first silicon oxide material layer 4211. Fig.11 , a second silicon oxide material layer 4212 and a second photoresist layer 4222 are sequentially formed on the surface of the exposed first silicon oxide material layer 4211, and the second silicon oxide material layer covers the metal material in the groove; Fig.12 , patterning the second photoresist layer 4222, forming an opening of a preset pattern of the upper wiring layer in the second photoresist layer 4222; wherein the opening in the second photoresist layer 4222 includes a third opening Q3 located above the first groove and a fourth opening Q4 located above the second groove; continue to refer to Fig.12 , etching the second silicon oxide material layer 4212 exposed by the opening of the second photoresist layer 4222 until the metal material in the first groove and the second groove is exposed; Fig.13 After removing the second photoresist layer, a third metal layer, such as a Cu layer, is formed on the surface of the second silicon oxide material layer 4212 and in the etched grooves, and the third metal layer outside the grooves is removed, thereby forming an upper wiring layer 16.

[0084] refer to Fig.14 , a third silicon oxide material layer 4213 and a third photoresist layer 4223 are sequentially formed on the surface of the upper wiring layer 16, and the third photoresist layer 4223 is patterned to form a fifth opening Q5 and a sixth opening Q6 in the third photoresist layer 4223; Fig.15 , etching the third silicon oxide material layer 4213 based on the fifth opening Q5 and the sixth opening Q6 until the wiring layer above the first groove and the wiring layer above the second groove are exposed; referring to Fig.16, forming a metal conductive structure a2 and a metal conductive structure b2 in the opening of the third silicon oxide material layer 4213 exposing the wiring layer; the metal conductive structure a2 is electrically connected to the metal conductive structure a1 in the first groove, and the metal conductive structure b2 is electrically connected to the metal conductive structure b1 in the second groove; Fig.17 and Fig.18 , continuing to sequentially form a fourth silicon oxide material layer 4214 and a fourth photoresist layer 4224 on the surface of the third silicon oxide material layer, and patterning the fourth photoresist layer 4224 to form an opening of a grating coupler and a preset pattern of the first optical waveguide; Fig.19 , based on the opening in the fourth photoresist layer 4224, etching the fourth silicon oxide material layer 4214 to form a groove of a preset pattern of a grating coupler and a first optical waveguide in the fourth silicon oxide material layer 4214; Fig. 20 , SiN material is deposited in the groove of the fourth silicon oxide material layer 4214 to form a grating coupler 18 and a first optical waveguide 15 respectively.

[0085] refer to Fig.21 , continuing to sequentially form a fifth silicon oxide material layer 4215 and a fifth photoresist layer 4225 on the surfaces of the grating coupler and the first optical waveguide, and patterning the fifth photoresist layer 4225 to form a seventh opening Q7 and an eighth opening Q8 in the fifth photoresist layer 4225; referring to Fig. 22 , based on the seventh opening Q7 and the eighth opening Q8, the fifth silicon oxide material layer 4215 is etched until the conductive structure a2 above the first groove and the conductive structure b2 above the second groove are exposed; Fig.23 , forming pads and / or bumps for external connection in the openings of the fifth silicon oxide material layer 4215 exposing the conductive structure, and removing the fifth photoresist layer 4225. The first silicon oxide material layer, the second silicon oxide material layer, the third silicon oxide material layer, the fourth silicon oxide material layer and the fifth silicon oxide material layer are used to form the first dielectric layer.

[0086] Step S1130 forms a second dielectric layer on the far side of the silicon substrate, and forms a wiring layer in the second dielectric layer, specifically including:

[0087] refer to Fig.24 and Fig.25 , forming a first dielectric layer on one side of the silicon substrate, and inverting the structure after forming a grating coupler, a first optical waveguide and a wiring layer in the first dielectric layer to expose the back side of the silicon substrate 41; thinning the back side of the silicon substrate 41 to at least a first preset position of the silicon substrate 41 to expose the metal material (metal conductive structure a1 and metal conductive structure b1) in the first groove and the second groove;

[0088] refer to Fig.26A sixth silicon oxide material layer 4311 and a sixth photoresist layer 4321 are sequentially formed on the back side of the thinned silicon substrate 41, and the sixth photoresist layer 4321 is patterned to form an opening of a preset pattern of a lower wiring layer in the sixth photoresist layer 4321; wherein the openings in the sixth photoresist layer 4321 include a ninth opening Q9 located above the bottom of the first groove and a tenth opening Q10 located above the bottom of the second groove; continue to refer to Fig.26 , etching the sixth silicon oxide material layer 4311 exposed by the opening of the sixth photoresist layer 4321 until the metal material (metal conductive structure a1 and metal conductive structure b1) in the first groove and the second groove is exposed; Fig. 27 After removing the sixth photoresist layer, a metal layer, such as a Cu layer, is formed on the surface of the sixth silicon oxide material layer 4311 and in the etched grooves, and the metal layer outside the grooves is removed, thereby forming a lower wiring layer 17.

[0089] refer to Fig.28 , continue to sequentially form a seventh silicon oxide material layer 4312 and a seventh photoresist layer 4322 on the surface of the lower wiring layer, and pattern the seventh photoresist layer 4322, and form an eleventh opening Q11 and a twelfth opening Q12 in the seventh photoresist layer 4322; Fig.29 , etching the seventh silicon oxide material layer 4312 based on the eleventh opening Q11 and the twelfth opening Q12 until the wiring layer above the bottom of the first groove is exposed and the wiring layer above the bottom of the second groove is exposed; Fig.30 , forming pads and / or bumps 23 for external connection in the openings of the seventh silicon oxide material layer 4312 exposing the wiring layer, and removing the seventh photoresist layer. The sixth silicon oxide material layer and the seventh silicon oxide material layer are used to form the second dielectric layer. The metal conductive structure a1 and the metal conductive structure a2 can be used to form a Cu channel 20 in a through hole of an optoelectronic interposer substrate for connecting a PCB circuit board and an optical chip, and the metal conductive structure b1 and the metal conductive structure b2 can be used to form a Cu channel 20 in a through hole of an optoelectronic interposer substrate for connecting a PCB circuit board and an electrical chip.

[0090] Optionally, in step S120, the optical chip and the electrical chip are fixedly connected to the first surface of the optoelectronic interposer substrate, specifically including:

[0091] The pads on the surface of the optical chip are fixedly connected to the pads on the first surface of the optoelectronic intermediate substrate by hybrid bonding; wherein the top surface of the pads arranged on the surface of the optical chip is higher than the surface of the cladding layer in the optical chip;

[0092] The conductive bumps on the surface of the electric chip are fixedly connected to the conductive bumps on the first surface of the optoelectronic intermediate substrate by means of flip packaging.

[0093] Optionally, in the optical chip, the waveguide layer includes a second optical waveguide; the device layer includes at least a functional module; when the optical chip is fixedly connected to the first surface of the optoelectronic intermediate substrate, it includes:

[0094] The end of the second optical waveguide is arranged above the end of the first optical waveguide so that the end of the first optical waveguide is coupled to the end of the second optical waveguide; wherein the first optical waveguide and the second optical waveguide are used to form an optical path; and the functional module is used to receive an optical signal input through the optical path and perform preset processing on the optical signal.

[0095] The above specific implementations do not constitute a limitation on the protection scope of the present utility model. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present utility model shall be included in the protection scope of the present utility model.

Claims

1. An optoelectronic co-sealing module based on advanced packaging, characterized in that: include: An optoelectronic interposer substrate including a first surface and a second surface opposite to each other; An optical chip and an electrical chip; the optical chip and the electrical chip are located on the first surface of the optoelectronic intermediary substrate and are both electrically connected to the optoelectronic intermediary substrate, and the electrical connection between the optical chip and the electrical chip is achieved through the optoelectronic intermediary substrate; A PCB circuit board, the PCB circuit board is located on the second surface of the optoelectronic intermediate substrate and is electrically connected to the optoelectronic intermediate substrate, and is electrically connected to the optical chip and the electrical chip through the optoelectronic intermediate substrate; An optical fiber array assembly is located on the first surface of the optoelectronic intermediary substrate and is coupled to the grating coupler in the optoelectronic intermediary substrate; Among them, a grating coupler and a first optical waveguide are arranged in the optoelectronic interposer substrate, the grating coupler and the first optical waveguide are coupled and connected, and the first optical waveguide extends from the area corresponding to the grating coupler to the area corresponding to the optical chip; the optical chip includes a waveguide layer and a device layer, the waveguide layer and the device layer are coupled through evanescent waves, the waveguide layer and the first optical waveguide are coupled and connected, and the grating coupler and the first optical waveguide are used to transmit the optical signal transmitted between the optical fiber array component and the optical chip.

2. The optoelectronic co-sealing module based on advanced packaging according to claim 1, characterized in that: The optoelectronic intermediate substrate comprises a silicon substrate and a first dielectric layer and a second dielectric layer located on opposite sides of the silicon substrate; Wherein, the surface of the first dielectric layer away from the silicon substrate is the first surface; the surface of the second dielectric layer away from the silicon substrate is the second surface; the materials of the first dielectric layer and the second dielectric layer include silicon dioxide; The grating coupler and the first optical waveguide are arranged in the first dielectric layer.

3. The optoelectronic co-sealing module based on advanced packaging according to claim 2, characterized in that: In the optical chip, the waveguide layer includes a second optical waveguide; the device layer includes at least a functional module; The end of the first optical waveguide and the end of the second optical waveguide are coupled and connected; the first optical waveguide and the second optical waveguide are used to form an optical path; The functional module is used to receive an optical signal input through the optical path and perform preset processing on the optical signal.

4. The optoelectronic co-sealing module based on advanced packaging according to claim 3, characterized in that: The device layer further comprises a third optical waveguide; the third optical waveguide is used to transmit an optical signal between the functional module and the second optical waveguide; The first optical waveguide is provided with a first waveguide coupler at an end close to the second optical waveguide; the first end of the second optical waveguide is provided with a second waveguide coupler, the second end of the second optical waveguide is provided with a third waveguide coupler; the end of the third optical waveguide close to the second optical waveguide is provided with a fourth waveguide coupler; The first waveguide coupler and the second waveguide coupler are coupled and connected to complete the transmission of optical signals between the first optical waveguide and the second optical waveguide; the third waveguide coupler and the fourth waveguide coupler are coupled and connected to complete the transmission of optical signals between the second optical waveguide and the third optical waveguide; The material of the first optical waveguide includes SiN, the material of the second optical waveguide includes SiN, and the material of the third optical waveguide includes Si.

5. The optoelectronic co-sealing module based on advanced packaging according to claim 1, characterized in that: The electrical chip is used to drive and control the optical chip; and / or, the electrical chip is used to receive an electrical signal output from the optical chip to perform a preset operation on the electrical signal; The surface of the optical chip is provided with a solder pad, and the first surface of the optoelectronic intermediate substrate is exposed with a solder pad; the solder pad on the surface of the optical chip is fixedly connected to the solder pad on the first surface of the optoelectronic intermediate substrate by hybrid bonding; The surface of the electric chip is provided with conductive bumps, and the first surface of the optoelectronic intermediate substrate is exposed with conductive bumps; the conductive bumps on the surface of the electric chip are fixedly connected to the conductive bumps on the first surface of the optoelectronic intermediate substrate by flip-packaging; The optical chip and the electrical chip are electrically connected via a conductive path in the optoelectronic interposer substrate.

6. The optoelectronic co-sealing module based on advanced packaging according to claim 5, characterized in that: The PCB circuit board is electrically connected to the optical chip and the electrical chip at least through the conductive through-holes in the optoelectronic intermediate substrate; The PCB circuit board is used to provide electrical signals for the optical chip and the electrical chip to work; and / or The PCB circuit board is used to lead out the electrical signals output by the optical chip and the electrical signals processed by the electrical chip.

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