Semiconductor integrated circuit packaging structure
By using limit shrapnel and guide structure in semiconductor integrated circuit packaging structure, the problem of semiconductor product placement offset is solved, the packaging accuracy and housing combination accuracy are improved, and a higher quality packaging effect is achieved.
Patent Information
- Application Number
- CN202323383714.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-12
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2033-12-12
AI Technical Summary
In existing semiconductor integrated circuit packages, the placement of semiconductor products between the upper and lower shells is prone to offset, resulting in a decrease in packaging accuracy and inconvenient use.
By setting limit shrapnel 1 and limit shrapnel 2, combining guide columns, guide holes and protective edges, ensure accurate placement of semiconductor products and housing combination, avoid offsets, and improve packaging accuracy and quality.
It effectively avoids the placement offset of semiconductor products, improves the packaging accuracy and housing combination accuracy, and enhances the packaging quality and convenience of use.
Smart Images
Figure CN222146143U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of packaging structures, in particular to a semiconductor integrated circuit packaging structure. Background Art
[0002] Semiconductor is a material with electrical conductivity between insulator and conductor. Its electrical conductivity is easy to control and can be used as a component material for information processing. When processing semiconductors, integrated circuits need to be packaged, which requires the use of packaging structures.
[0003] In the prior art, packaging is formed by bonding a lower half shell and an upper half shell, and a semiconductor is placed between the upper half shell and the lower half shell. However, the position where the semiconductor is placed is easily offset, resulting in reduced packaging accuracy and inconvenience in use. Utility Model Content
[0004] In order to overcome the shortcomings of the prior art, one of the purposes of the utility model is to provide a semiconductor integrated circuit packaging structure. By setting a limit spring piece 1 and a limit spring piece 2, the placement deviation of the semiconductor product can be avoided, thereby improving the packaging accuracy; the set guide columns, guide holes, and protective edges can increase the accuracy of the combination of the upper half shell and the lower half shell, improve the quality of the packaging, and facilitate use.
[0005] One of the purposes of the utility model is achieved by the following technical solution: a semiconductor integrated circuit packaging structure, including a lower half shell and an upper half shell, the lower half shell is fixedly connected with a protective edge, the middle part of the lower half shell is provided with a placement groove, the lower half shell and the outer side of the placement groove are fixedly connected with a limiting spring piece 1 and a limiting spring piece 2, the limiting spring piece 1 and the limiting spring piece 2 are fixedly connected, the upper part of the lower half shell and the inner side of the protective edge are fixedly connected with a guide column, the upper half shell is provided with a guide hole, the lower part of the upper half shell is provided with a clearance groove, the lower part of the upper half shell is provided with a packaging groove and a receiving groove, the receiving groove cooperates with the limiting spring piece 1 and the limiting spring piece 2. By providing the limiting spring piece 1 and the limiting spring piece 2, the placement deviation of the semiconductor product can be avoided, thereby improving the accuracy of the packaging; the provided guide column, guide hole, and protective edge can increase the accuracy of the combination of the upper half shell and the lower half shell, improve the quality of the packaging, and facilitate use.
[0006] According to the semiconductor integrated circuit packaging structure, the number of the guide pillars is four and they are axially symmetrically arranged.
[0007] According to the semiconductor integrated circuit packaging structure, the guide post and the guide hole cooperate with each other, and the guide post is located outside the first limiting spring piece and the second limiting spring piece.
[0008] According to the semiconductor integrated circuit packaging structure, the first limiting spring piece and the second limiting spring piece are perpendicular to each other.
[0009] According to the semiconductor integrated circuit packaging structure, a semiconductor product is arranged inside the placement groove.
[0010] According to the semiconductor integrated circuit packaging structure, a pin hole for a pin to pass through is provided inside the placement groove.
[0011] According to the semiconductor integrated circuit packaging structure, the packaging groove and the receiving groove are communicated with each other.
[0012] According to the semiconductor integrated circuit packaging structure, the upper parts of the first limiting spring piece and the second limiting spring piece are both provided with arc parts.
[0013] Beneficial Effects
[0014] Compared with the prior art, the present invention can avoid the placement deviation of semiconductor products by setting the limiting spring piece 1 and the limiting spring piece 2, thereby improving the packaging accuracy; the set guide column, guide hole, and protective edge can increase the accuracy of the combination of the upper half shell and the lower half shell, improve the quality of the packaging, and facilitate use.
[0015] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The utility model is further described below in conjunction with the accompanying drawings and embodiments;
[0017] Figure 1 This is a schematic structural diagram of a semiconductor integrated circuit packaging structure of the utility model;
[0018] Figure 2 It is a structural schematic diagram of the upper half shell portion of a semiconductor integrated circuit packaging structure of the utility model from a bottom perspective;
[0019] Figure 3 This is a schematic structural diagram of the lower half shell portion of a semiconductor integrated circuit packaging structure of the utility model;
[0020] Figure 4 The utility model is a schematic structural diagram of an upper half shell portion of a semiconductor integrated circuit packaging structure.
[0021] Legend:
[0022] 1. Lower shell; 101. Protective edge; 102. Limit spring piece 1; 103. Guide column; 104. Limit spring piece 2; 105. Placement slot; 2. Upper shell; 201. Guide hole; 202. Make way slot; 203. Accommodation slot; 204. Packaging slot; 3. Semiconductor product. DETAILED DESCRIPTION
[0023] This section will describe in detail the specific embodiments of the utility model. The preferred embodiments of the utility model are shown in the accompanying drawings. The purpose of the accompanying drawings is to supplement the description of the text part of the specification with graphics, so that people can intuitively and vividly understand each technical feature and the overall technical solution of the utility model, but it cannot be understood as a limitation on the protection scope of the utility model.
[0024] Reference Figure 1-4 The present invention is a semiconductor integrated circuit packaging structure according to an embodiment of the present invention, which comprises a lower half shell 1 and an upper half shell 2, wherein a protective edge 101 is fixedly connected to the lower half shell 1, a placement groove 105 is arranged in the middle of the lower half shell 1, a conductor product 3 is arranged inside the placement groove 105, a pin hole for a pin to pass through is arranged inside the placement groove 105, a limiting spring piece 102 and a limiting spring piece 2 104 are fixedly connected to the lower half shell 1 and located outside the placement groove 105, an arc portion is arranged on the upper part of the limiting spring piece 102 and the limiting spring piece 2 104, the limiting spring piece 102 and the limiting spring piece 2 104 are perpendicular to each other, the limiting spring piece 102 and the limiting spring piece 2 104 are fixedly connected, a guide column 103 is fixedly connected to the upper part of the lower half shell 1 and located inside the protective edge 101, the number of the guide columns 103 is four, and they are axially symmetrically arranged, and the guide columns 103 and the guide holes 201 are matched with each other. The guide column 103 is located on the outside of the limiting spring piece 102 and the limiting spring piece 2 104, a guide hole 201 is arranged on the upper half shell 2, a yield groove 202 is arranged at the lower part of the upper half shell 2, a packaging groove 204 and a receiving groove 203 are arranged at the lower part of the upper half shell 2, the packaging groove 204 and the receiving groove 203 are communicated with each other, the receiving groove 203 and the limiting spring piece 102 and the limiting spring piece 2 104 cooperate with each other, when in use, the semiconductor product 3 is placed in the placement groove 105, under the limiting effect of the limiting spring piece 102 and the limiting spring piece 2 104, the accurate placement of the semiconductor product is guaranteed, the packaging accuracy is improved, and the pin damage is avoided; then the upper half shell 2 is assembled with the lower half shell 1, the guide column 103 passes through the guide hole 201, the protective edge 101 and the yield groove 202 are engaged with each other, so as to complete the packaging, wherein the pin passes through the pin hole inside the placement groove 105, and the packaging quality is good. By setting the limiting spring piece 102 and the limiting spring piece 2 104, the placement deviation of the semiconductor product 3 can be avoided, thereby improving the packaging accuracy; the set guide column 103, guide hole 201, and protective edge 101 can increase the combination accuracy of the upper half shell 2 and the lower half shell 1, improve the packaging quality, and facilitate use.
[0025] Working principle: When in use, the semiconductor product 3 is placed in the placement groove 105. Under the limiting action of the limiting spring piece 102 and the limiting spring piece 2 104, the semiconductor product 3 is accurately placed, the packaging accuracy is improved, and the pin damage is avoided; then the upper half shell 2 and the lower half shell 1 are assembled, the guide column 103 passes through the guide hole 201, and the protective edge 101 and the give way groove 202 are engaged with each other, thereby completing the packaging, wherein the pin passes through the pin hole inside the placement groove 105, and the packaging quality is good.
[0026] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.
Claims
1. A semiconductor integrated circuit packaging structure, comprising a lower half shell (1) and an upper half shell (2), characterized in that: The lower half shell (1) is fixedly connected with a protective edge (101), a placement groove (105) is provided in the middle of the lower half shell (1), a limiting spring piece 1 (102) and a limiting spring piece 2 (104) are fixedly connected on the lower half shell (1) and located outside the placement groove (105), the limiting spring piece 1 (102) and the limiting spring piece 2 (104) are fixedly connected, a guide column (103) is fixedly connected on the upper part of the lower half shell (1) and located inside the protective edge (101), a guide hole (201) is provided on the upper half shell (2), a yield groove (202) is provided at the lower part of the upper half shell (2), a packaging groove (204) and a receiving groove (203) are provided at the lower part of the upper half shell (2), and the receiving groove (203) cooperates with the limiting spring piece 1 (102) and the limiting spring piece 2 (104).
2. A semiconductor integrated circuit packaging structure according to claim 1, characterized in that: There are four guide posts (103) which are arranged axially symmetrically.
3. The semiconductor integrated circuit packaging structure according to claim 1, characterized in that: The guide column (103) cooperates with the guide hole (201), and the guide column (103) is located outside the first limiting spring piece (102) and the second limiting spring piece (104).
4. The semiconductor integrated circuit packaging structure according to claim 1, characterized in that: The first limiting spring piece (102) and the second limiting spring piece (104) are perpendicular to each other.
5. The semiconductor integrated circuit packaging structure according to claim 1, characterized in that: A semiconductor product (3) is arranged inside the placement groove (105).
6. The semiconductor integrated circuit packaging structure according to claim 1, characterized in that: A pin hole for a pin to pass through is arranged inside the placement groove (105).
7. The semiconductor integrated circuit packaging structure according to claim 1, characterized in that: The packaging groove (204) and the containing groove (203) are communicated with each other.
8. The semiconductor integrated circuit packaging structure according to claim 1, characterized in that: The upper parts of the limiting spring piece 1 (102) and the limiting spring piece 2 (104) are both provided with arc parts.