Semiconductor structure
By introducing an electric field adjustment structure into the semiconductor structure and adjusting the electric field distribution, the problem of improving the BVds of the MOSFET device is solved, and performance optimization is achieved, with simple process and low cost.
Patent Information
- Application Number
- CN202420877223.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-25
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2034-04-25
AI Technical Summary
When the prior art regulates the source-drain breakdown voltage (BVds) of MOSFET devices, it will affect other performance indicators, making it difficult to effectively improve BVds without affecting other performance.
An electric field adjustment structure is introduced into the semiconductor structure, which is located on the isolation structure. By adjusting the electric field distribution, the electric field strength at the corner of the drain region and the body contact area is reduced, thereby increasing the BVds.
It effectively improves BVds, reduces the peak of electric field intensity, simplifies the preparation process, and does not require additional masks or changes in process steps, avoiding the introduction of additional costs.
Smart Images
Figure CN222146234U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of semiconductors and relates to a semiconductor structure. Background Art
[0002] In the semiconductor field, a metal oxide field effect transistor (MOSFET) is a semiconductor device that uses the electric field effect of a control input loop to control the current in an output loop. It is a four-terminal device with source (S), gate (G), drain (D) and body (B) terminals.
[0003] Among them, for MOSFET devices, breakdown voltage (BV), especially source-drain breakdown voltage (BVds), is a more important performance parameter in MOSFET devices. For the performance parameter BVds, the industry usually uses the method of changing the injection (IMP) conditions to adjust the BVds of MOSFET devices. However, when changing the IMP conditions, other performance indicators of MOSFET devices will also be affected.
[0004] Therefore, it is necessary to provide a semiconductor structure to effectively improve the BVds of MOSFET devices and reduce the impact on other performance indicators of the devices. Utility Model Content
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a semiconductor structure for solving the BVds problem of MOSFET devices in the prior art.
[0006] In order to achieve the above-mentioned object and other related objects, the utility model provides a semiconductor structure, which includes:
[0007] a first conductivity type well region;
[0008] a first conductivity type body contact region, the first conductivity type body contact region being located in the first conductivity type well region;
[0009] A second conductivity type drain region, wherein the second conductivity type drain region is located in the first conductivity type well region, and a spacer region is provided between the second conductivity type drain region and the first conductivity type body contact region;
[0010] an isolation structure, the isolation structure being located in the spacing region and contacting both the second conductivity type drain region and the first conductivity type body contact region;
[0011] An electric field adjustment structure is located on the isolation structure.
[0012] Optionally, in the width direction, a projection of the channel of the semiconductor structure on the electric field adjustment structure is completely located within the electric field adjustment structure.
[0013] Optionally, a center line of the electric field adjustment structure coincides with a center line of the isolation structure.
[0014] Optionally, the length of the electric field adjustment structure is less than 1 / 2 of the length of the isolation structure; or the length of the electric field adjustment structure is 0.4-0.6 μm.
[0015] Optionally, the electric field adjustment structure includes one of a metal layer and a polysilicon layer located on the isolation structure, or a stack of a metal layer and a polysilicon layer.
[0016] Optionally, the electric field adjustment structure and the gate conductive layer in the semiconductor structure have the same material.
[0017] Optionally, the semiconductor structure includes a HVMOS semiconductor structure.
[0018] Optionally, the semiconductor structure includes one of NMOS, PMOS and CMOS, or a composite structure composed of NMOS, PMOS and CMOS.
[0019] Optionally, the semiconductor structure further includes an electric field regulating isolation structure located in the second conductivity type drain region.
[0020] Optionally, the first conductivity type is P type, and the corresponding second conductivity type is N type; or the first conductivity type is N type, and the corresponding second conductivity type is P type.
[0021] As described above, the semiconductor structure of the utility model includes a first conductive type well region, a first conductive type body contact region, a second conductive type drain region, an isolation structure and an electric field regulation structure, wherein the first conductive type body contact region and the second conductive type drain region are both located in the first conductive type well region, and there is a spacing region between the second conductive type drain region and the first conductive type body contact region, the isolation structure is located in the spacing region and is in contact with both the second conductive type drain region and the first conductive type body contact region, and the electric field regulation structure is located on the isolation structure.
[0022] The semiconductor structure of the utility model is provided with an electric field regulating structure on the isolation structure between the drain region and the body contact region. The electric field distribution can be adjusted by the electric field regulating structure, so as to solve the problem that the electric field strength at the corner of the isolation structure between the drain region and the body contact region is high and prone to breakdown due to the tip effect, so as to achieve the effect of improving the BVds of the semiconductor structure. The preparation process is simple, no additional mask is required, no process steps need to be changed, and no additional cost will be introduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 Shown is a schematic structural diagram of a semiconductor structure in a comparative example.
[0024] Figure 2 Display as Figure 1 Schematic diagram of the cross-sectional structure along AA.
[0025] Figure 3 Shown is a schematic structural diagram of the semiconductor structure in the present invention.
[0026] Figure 4 Display as Figure 3 Schematic diagram of the cross-sectional structure along CC.
[0027] Figure 5 Display as Figure 1 TCAD simulation results of the semiconductor structure in .
[0028] Figure 6 Display as Figure 3 TCAD simulation results of the semiconductor structure in FIG. 1 when it has electric field adjustment structures of different lengths.
[0029] Figure 7 The graph shows the comparison of the electric field strength results of the semiconductor structures in the comparative example and the embodiment.
[0030] Figure 8 A comparison chart of the breakdown voltage results of the semiconductor structures in the comparative example and the embodiment is shown.
[0031] Fig. 9 Display as Figure 8 A partial enlarged view of the middle M area.
[0032] Component number description
[0033] 100 First conductivity type well region
[0034] 200 First conductivity type body contact region
[0035] 300 Second conductivity type drain region
[0036] 400 Interval
[0037] 500 Isolation Structure
[0038] 600 Electric field regulation structure
[0039] 700 Gate Structure
[0040] 701 Gate dielectric layer
[0041] 702 gate conductive layer
[0042] 800 Electric field regulation isolation structure
[0043] 900 Second conductivity type source region DETAILED DESCRIPTION
[0044] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0045] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0046] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0047] Comparative Example
[0048] like Figure 1 and Figure 2 The comparative example provides a semiconductor structure, which includes: a first conductive type well region 100 , a first conductive type body contact region 200 , a second conductive type drain region 300 , and an isolation structure 500 .
[0049] Among them, the first conductive type body contact region 200 is located in the first conductive type well region 100; the second conductive type drain region 300 is located in the first conductive type well region 100, and there is a spacer region 400 between the second conductive type drain region 300 and the first conductive type body contact region 200; the isolation structure 500 is located in the spacer region 400 and is in contact with both the second conductive type drain region 300 and the first conductive type body contact region 200.
[0050] In this comparative example, the semiconductor structure takes HVNMOS as an example, and an electric field regulation isolation structure 800 and a gate structure 700 are also provided in the second conductive type drain region 300 , and the gate structure 700 includes a gate dielectric layer 701 located below and a gate conductive layer 702 located on the gate dielectric layer 701 .
[0051] See also Figure 5 , Figure 7 , Figure 8 and Fig. 9 After wafer acceptance testing (WAT) and semiconductor device simulation (TCAD) of the semiconductor structure, it is known that the electric field distribution of the semiconductor structure is uneven, especially at the corner of the isolation structure 500 adjacent to the second conductive type drain region 300 and across the PN junction, where the electric field is particularly concentrated. Figure 5 In the D area.
[0052] Example
[0053] like Figure 3 and Figure 4 This embodiment provides a semiconductor structure, and the main difference between the semiconductor structure and the semiconductor structure in comparative example 1 is that an electric field adjustment structure 600 is added.
[0054] In this embodiment, the semiconductor structure includes a first conductivity type well region 100 , a first conductivity type body contact region 200 , a second conductivity type drain region 300 , an isolation structure 500 and the electric field adjustment structure 600 .
[0055] Among them, the first conductive type body contact region 200 is located in the first conductive type well region 100; the second conductive type drain region 300 is located in the first conductive type well region 100, and there is a spacer region 400 between the second conductive type drain region 300 and the first conductive type body contact region 200; the isolation structure 500 is located in the spacer region 400 and is in contact with both the second conductive type drain region 300 and the first conductive type body contact region 200; the electric field adjustment structure 600 is located on the isolation structure 500.
[0056] As an example, the first conductivity type may be P type, and the corresponding second conductivity type may be N type; or the first conductivity type may be N type, and the corresponding second conductivity type may be P type.
[0057] In this embodiment, the first conductivity type is P type, and the corresponding second conductivity type is N type which is the opposite conductivity type; however, it is not limited to this. In another embodiment, the first conductivity type may also be N type, and the corresponding second conductivity type may be P type. No excessive limitation is made here.
[0058] As an example, the semiconductor structure may be one of NMOS, PMOS and CMOS, or a composite structure composed of NMOS, PMOS and CMOS, but is not limited thereto.
[0059] like Figure 3 and Figure 4 In this embodiment, the semiconductor structure is a high voltage MOS, namely, HVMOS, and HVNMOS is taken as an example, but the type of the semiconductor structure is not limited thereto, such as the semiconductor structure may also be HVPMOS, etc.
[0060] Specifically, in this embodiment, the gate structure 700 in the semiconductor structure includes a gate dielectric layer 701 located below and a gate conductive layer 702 located on the gate dielectric layer 701, wherein the material of the gate dielectric layer 701 may be silicon oxide, but is not limited to this, and the gate conductive layer 702 may be one of a metal layer and a polysilicon layer, or a stack of metal layers and polysilicon layers, and no excessive restrictions are made here.
[0061] Regarding the second conductivity type source region 900 in the semiconductor structure and the configuration of the related isolation structure in the second conductivity type source region 900 , reference may be made to the second conductivity type drain region 300 , which will not be described in detail herein.
[0062] It should be noted that, in this embodiment, the morphology of each functional area in the semiconductor structure is not limited to the morphology shown in the figure, and can be flexibly selected according to needs, and no excessive restrictions are made here.
[0063] In this embodiment, an electric field regulating isolation structure 800 is also included in the second conductive type drain region 300, so as to adjust and optimize the electric field distribution in the drain region through the electric field regulating isolation structure 800. The material of the electric field regulating isolation structure 800 may be silicon oxide, but is not limited to this.
[0064] As an example, preferably in the width direction, the projection of the channel of the semiconductor structure on the electric field adjustment structure 600 is completely located within the electric field adjustment structure 600 .
[0065] Specifically, Figure 3 , the X direction is shown as the length direction, and the Y direction is shown as the width direction. In the width direction, when the projection of the channel of the semiconductor structure on the electric field adjustment structure 600 is completely located within the electric field adjustment structure 600, the electric field adjustment structure 600 can completely cover the corner of the isolation structure 500 between the drain region and the body contact region, where the electric field strength is high and breakdown is prone to occur due to the tip effect, so as to play a good adjustment role and avoid missing some areas.
[0066] In this embodiment, Figure 3 The width of the electric field adjustment structure 600 along the Y direction is greater than the width of the channel in the Y direction to ensure that the projection of the channel in the electric field adjustment structure 600 is completely located inside the electric field adjustment structure 600 .
[0067] As an example, the center line of the electric field adjustment structure 600 coincides with the center line of the isolation structure 500. Further, it is preferred that the length of the electric field adjustment structure 600 is less than 1 / 2 of the length of the isolation structure 500. Figure 3 wherein, preferably, the length of the electric field adjustment structure 600 is 0.4 to 0.6 μm.
[0068] Specifically, as shown in Table 1, Figure 6 , Figure 7 , Figure 8 and Fig. 9 Taking an HVNMOS device with a channel width of 55.55 μm (along the Y direction) and a length of 2.78 μm (along the X direction) as an example, the HVNMOS device without the electric field regulating structure 600 in the comparative example, that is, the length of the electric field regulating structure 600 is 0, and the HVNMOS device with different lengths of the electric field regulating structure 600 in this embodiment, that is, the lengths of the electric field regulating structure 600 are 0.24 μm, 0.44 μm, 0.64 μm, and 0.84 μm respectively, are subjected to WAT test and TCAD simulation.
[0069] The results show that after adding the electric field adjustment structure 600, the electric field in the D region at the corner of the isolation structure 500 is improved, the peak field strength is effectively reduced, and the BVds is significantly improved. Among them, when the electric field adjustment structure 600 adopts different lengths, the improvement of the electric field is not linear with the increase of the length of the electric field adjustment structure 600. The field strength in the D region at the corner of the isolation structure 500 decreases with the increase of the length of the electric field adjustment structure 600, and the field strength below the electric field adjustment structure 600 increases with the increase of the length of the electric field adjustment structure 600. When the length of the electric field adjustment structure 600 is 0.4 to 0.6 μm, its overall field strength is at the optimal value; or when the length of the electric field adjustment structure 600 is less than 1 / 2 of the length of the isolation structure 500, such as 1 / 4, 1 / 3, 1 / 2, etc., the electric field adjustment structure 600 can have a good adjustment effect on the electric field distribution.
[0070] Table 1:
[0071]
[0072] There is no excessive restriction on the selection of the specific size and shape of the electric field adjustment structure 600, and it can be selected according to needs.
[0073] As an example, the electric field adjustment structure 600 may include one of a metal layer and a polysilicon layer located on the isolation structure 500 , or a stack of a metal layer and a polysilicon layer.
[0074] Specifically, the electric field regulating structure 600 may be a conductive metal layer or a conductive polysilicon layer, or a stacked layer consisting of a conductive metal layer and a conductive polysilicon layer. The specific structure of the electric field regulating structure 600 is not limited herein.
[0075] Among them, it is preferred that the electric field adjustment structure 600 and the gate conductive layer 702 in the semiconductor structure have the same material, so that when preparing the electric field adjustment structure 600, the electric field adjustment structure 600 can be prepared synchronously with the gate conductive layer 702, so that the preparation of the semiconductor structure can be completed without adding an additional mask or changing the process steps, so that the preparation process is simple and no additional cost is introduced. However, the preparation of the electric field adjustment structure 600 is not limited to this, and it can also be prepared separately from the gate conductive layer 702, and no excessive restrictions are made here.
[0076] To sum up, the semiconductor structure of the present invention includes a first conductive type well region, a first conductive type body contact region, a second conductive type drain region, an isolation structure and an electric field regulation structure, wherein the first conductive type body contact region and the second conductive type drain region are both located in the first conductive type well region, and there is a spacing region between the second conductive type drain region and the first conductive type body contact region, the isolation structure is located in the spacing region and is in contact with both the second conductive type drain region and the first conductive type body contact region, and the electric field regulation structure is located on the isolation structure.
[0077] The semiconductor structure of the utility model is provided with an electric field regulating structure on the isolation structure between the drain region and the body contact region, and the electric field distribution can be adjusted by the electric field regulating structure, so as to solve the problem that the electric field strength at the corner of the isolation structure between the drain region and the body contact region is high and easy to break down due to the tip effect, so as to achieve the effect of improving the BVds of the semiconductor structure, and the preparation process is simple, without the need to add additional masks, without changing the process steps, and without introducing additional costs. Therefore, the utility model effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0078] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.
Claims
1. A semiconductor structure, characterized in that: The semiconductor structure comprises: a first conductivity type well region; a first conductivity type body contact region, the first conductivity type body contact region being located in the first conductivity type well region; A second conductivity type drain region, wherein the second conductivity type drain region is located in the first conductivity type well region, and a spacer region is provided between the second conductivity type drain region and the first conductivity type body contact region; an isolation structure, the isolation structure being located in the spacing region and contacting both the second conductivity type drain region and the first conductivity type body contact region; An electric field adjustment structure is located on the isolation structure.
2. The semiconductor structure according to claim 1, wherein: In the width direction, a projection of the channel of the semiconductor structure on the electric field adjustment structure is completely located within the electric field adjustment structure.
3. The semiconductor structure according to claim 1, wherein: A center line of the electric field adjustment structure coincides with a center line of the isolation structure.
4. The semiconductor structure according to claim 3, characterized in that: The length of the electric field adjustment structure is less than 1 / 2 of the length of the isolation structure; Or the length of the electric field adjustment structure is 0.4-0.6 μm.
5. The semiconductor structure according to claim 1, wherein: The electric field adjustment structure includes one of a metal layer and a polysilicon layer located on the isolation structure, or a stacked layer consisting of a metal layer and a polysilicon layer.
6. The semiconductor structure according to claim 1, wherein: The electric field adjustment structure and the gate conductive layer in the semiconductor structure are made of the same material.
7. The semiconductor structure according to claim 1, wherein: The semiconductor structure includes a HVMOS semiconductor structure.
8. The semiconductor structure according to claim 1, wherein: The semiconductor structure includes one of NMOS, PMOS and CMOS or a composite structure composed of NMOS, PMOS and CMOS.
9. The semiconductor structure according to claim 1, wherein: The semiconductor structure also includes an electric field regulating isolation structure located in the second conductivity type drain region.
10. The semiconductor structure according to claim 1, wherein: The first conductivity type is P type, and the corresponding second conductivity type is N type; or the first conductivity type is N type, and the corresponding second conductivity type is P type.