Zero setting circuit and zero drift operational amplifier using same
The zero adjustment circuit and zero-drift operational amplifier address performance deviations by alternately operating two amplifiers to adjust offset voltages, achieving precise zero adjustment and reducing drift to 13uV, thus improving accuracy and stability.
Patent Information
- Application Number
- CN202420572546.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-22
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2034-03-22
AI Technical Summary
Existing zero-drift operational amplifiers suffer from performance deviations due to slight differences in device characteristics and temperature changes, affecting accuracy and stability.
A zero adjustment circuit and zero-drift operational amplifier design that alternately operates two zeroing amplifiers in signal output and zeroing states, utilizing a logic module to control switches and storage capacitors to cyclically adjust offset voltages.
The solution achieves precise zero adjustment with a simple structure, reducing offset drift to 13uV, enhancing accuracy and stability at minimal cost.
Smart Images
Figure CN222147575U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of zero adjustment circuits, in particular to a zero adjustment circuit and a zero-drift operational amplifier using the same. Background Art
[0002] An operational amplifier (Operational Amplifier, referred to as Op-Amp) is an electronic device used to amplify the voltage of an input signal and output it as a signal after gain. The characteristics of an operational amplifier include high gain, high input impedance, low output impedance, dual power supply, etc. Ideally, the operational amplifier should have zero input voltage difference, but in reality, even in the absence of an input signal, there will be a tiny voltage output at the output end. This tiny voltage output may be caused by factors such as asymmetry in the device manufacturing process, differences in internal materials of the device, temperature changes, etc., which is usually called offset voltage. The offset voltage is usually measured in millivolts (mV) and is an important indicator of the operational amplifier because it affects the performance and accuracy of the amplifier.
[0003] A zero-drift operational amplifier that can offset zero drift through self-calibration is designed by adding an internal feedback network to the operational amplifier structure, thereby achieving precise control of the input signal and zero drift. Although the characteristics of the zero-drift operational amplifier give it high performance in zero-point drift, problems such as slight differences in device characteristics, temperature changes, and operating time may still affect its performance, causing the output signal to deviate from the expected zero point position, affecting the accuracy and stability of the amplifier. For this reason, we propose a zero adjustment circuit and a zero-drift operational amplifier using it. Utility Model Content
[0004] The utility model provides a zero adjustment circuit and a zero drift operational amplifier using the same, so as to solve the zero adjustment problem of the zero drift operational amplifier in the prior art. To achieve the above object, the utility model provides the following scheme: a zero adjustment circuit and a zero drift operational amplifier using the same, used for zero adjustment of the output of the zero drift operational amplifier, comprising a first zero adjustment amplifier, a second zero adjustment amplifier and a LOGIC module;
[0005] The first zeroing amplifier has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal, and has a storage capacitor inside, wherein the positive input terminal and the negative input terminal are electrically connected to the first switch group and the second switch group respectively, and a first short circuit is electrically connected between the positive output terminal and the negative output terminal;
[0006] The second zeroing amplifier has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal, and has a storage capacitor inside, wherein the positive input terminal and the negative input terminal are electrically connected to the third switch group and the fourth switch group respectively, and a second short circuit is electrically connected between the positive output terminal and the negative output terminal;
[0007] The pulse clock output by the LOGIC module acts on the switch group, the short circuit and the storage capacitor to control the first zeroing amplifier and the second zeroing amplifier to cyclically operate in four working states. In these four working states, the first zeroing amplifier and the second zeroing amplifier are alternately in the signal output state and the zeroing state.
[0008] The first switch group includes three channels, each of which is equipped with a switch. The three channels are respectively input with voltages vin2, vin1 and vin2, and the output ends are electrically connected to the positive input end of the first zeroing amplifier. The second switch group includes three channels, each of which is equipped with a switch. The three channels are respectively input with voltages vin1, vin2 and vin2, and the output ends are electrically connected to the negative input end of the first zeroing amplifier. The switches on the three channels of the first switch group and the second switch group are respectively controlled by pulse clocks S1001, S0100, and S0010.
[0009] The third switch group includes three channels, each of which is provided with a switch. The three channels are respectively input with voltages vin2, vin1 and vin2, and the output ends are electrically connected to the positive input end of the second zeroing amplifier. The fourth switch group includes three channels, each of which is provided with a switch. The three channels are respectively input with voltages vin1, vin2 and vin2, and the output ends are electrically connected to the negative input end of the second zeroing amplifier. The switches on the three channels of the third switch group and the fourth switch group are respectively controlled by pulse clocks S1000, S0110 and S0001.
[0010] The first short-circuit circuit is connected in series with a plurality of switches, and the switches can be controlled by a pulse clock S0001.
[0011] The second short-circuit circuit is connected in series with a plurality of switches, and the switches can be controlled by a pulse clock S0100.
[0012] In the first working state, the pulse clock output by the LOGIC module controls the input channel, the positive input terminal and the negative input terminal of the first zeroing amplifier are respectively connected to vin2 and vin1, the storage capacitor is turned off, the output terminal is in a signal output state, the positive input terminal and the negative input terminal of the second zeroing amplifier are short-circuited, the storage capacitor is connected to the output terminal and stores the offset voltage, and;
[0013] In the second working state, the positive input terminal and the negative input terminal of the first zeroing amplifier are respectively input with vin1 and vin2, the storage capacitor is turned off, and the output terminal is in a signal output state, the positive input terminal and the negative input terminal of the second zeroing amplifier are respectively input with vin2 and vin1, the storage capacitor is turned off, the positive and negative output terminals are short-circuited, and the voltage of the storage capacitor is used to adjust the offset of the second zeroing amplifier.
[0014] In the third working state, the pulse clock output by the LOGIC module controls the input channel, the positive input terminal and the negative input terminal of the first zeroing amplifier are short-circuited, the storage capacitor is connected to the output terminal and stores the offset voltage, the positive input terminal and the negative input terminal of the second zeroing amplifier are connected to vin2 and vin1 respectively, the storage capacitor is turned off, and the output terminal is in a signal output state, and;
[0015] In the fourth working state, the positive input terminal and the negative input terminal of the first zeroing amplifier are respectively input with vin2 and vin1, the storage capacitor is turned off, and the voltage of the storage capacitor is used to adjust the offset of the first zeroing amplifier. The positive input terminal and the negative input terminal of the second zeroing amplifier are respectively input with vin1 and vin2, the storage capacitor is turned off, and the output terminal is in a signal output state.
[0016] Compared with the prior art, the beneficial effects of the utility model are:
[0017] Compared with the prior art, the zero-drift operational amplifier using the zero-drift circuit of the utility model has the advantages that the circuit of the utility model has a simple structure, is easy to use and easy to implement by setting two zero-drift operational amplifiers to work alternately in a signal output state and a zero-drift state. The zero-drift operational amplifier can be controlled within 13uV by the zero-drift circuit at a minimum cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:
[0019] Figure 1 This is the overall circuit diagram of the zero adjustment circuit of the utility model;
[0020] Figure 2 This is the external circuit diagram of the first zeroing amplifier of the utility model;
[0021] Figure 3 This is the external circuit diagram of the second zeroing amplifier of the utility model;
[0022] Figure 4 This is a functional simulation diagram of the first zeroing amplifier of the utility model; DETAILED DESCRIPTION
[0023] The technical solutions in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all of the embodiments; based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the utility model.
[0024] The utility model provides a zero adjustment circuit and a zero drift operational amplifier using the same, which are used for zeroing the output of the zero drift operational amplifier, and include a first zero adjustment amplifier, a second zero adjustment amplifier and a LOGIC module, wherein the first zero adjustment amplifier has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal, and has a storage capacitor inside, wherein the positive input terminal and the negative input terminal are electrically connected to the first switch group and the second switch group respectively, and a first short circuit is electrically connected between the positive output terminal and the negative output terminal; the second zero adjustment amplifier has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal, and has a storage capacitor inside, wherein the positive input terminal and the negative input terminal are electrically connected to the third switch group and the fourth switch group respectively, and a second short circuit is electrically connected between the positive output terminal and the negative output terminal; the pulse clocks S1001, S0100, S0010 and S1000, S0110, S0001 output by the LOGIC module act on the switch group, the short circuit and the storage capacitor to control the first zero adjustment amplifier and the second zero adjustment amplifier to cyclically work in four working states, in which, if Figure 1 In the zeroing circuit shown as a whole, the first zeroing amplifier and the second zeroing amplifier are alternately in a signal output state and a zeroing state.
[0025] like Figure 2 In the structure given by the external circuit of the first zeroing amplifier shown, the first switch group includes three channels, each channel is provided with a switch, the three channels are respectively input with voltages vin2, vin1 and vin2, and the output ends are electrically connected to the positive input end of the first zeroing amplifier; the second switch group includes three channels, each channel is provided with a switch, the three channels are respectively input with voltages vin1, vin2 and vin2, and the output ends are electrically connected to the negative input end of the first zeroing amplifier, and the switches on the three channels of the first switch group and the second switch group are respectively controlled by pulse clocks S1001, S0100, and S0010.
[0026] like Figure 3In the structure given by the external circuit of the first zeroing amplifier shown, the first switch group includes three channels, the third switch group includes three channels, each channel is provided with a switch, the three channels are respectively input with voltages vin2, vin1 and vin2, and the output ends are electrically connected to the positive input end of the second zeroing amplifier, the fourth switch group includes three channels, each channel is provided with a switch, the three channels are respectively input with voltages vin1, vin2 and vin2, and the output ends are electrically connected to the negative input end of the second zeroing amplifier, and the switches on the three channels of the third switch group and the fourth switch group are respectively controlled by pulse clocks S1000, S0110, and S0001.
[0027] The first short-circuit circuit is connected in series with a plurality of switches, and the switches can be controlled by a pulse clock S0001.
[0028] The second short-circuit circuit is connected in series with a plurality of switches, and the switches can be controlled by a pulse clock S0100.
[0029] In the first working state, the pulse clock S1000 output by the LOGIC module is high, S0100 is low, S0010 is low, S0001 is low, S1001 is high, and S0110 is low, the input channel is controlled, the positive input terminal and the negative input terminal of the first zeroing amplifier are connected to vin2 and vin1 respectively, the storage capacitor is turned off, the output terminal is in a signal output state, the positive input terminal and the negative input terminal of the second zeroing amplifier are short-circuited with the input vin1, the storage capacitor is connected to the output terminal and stores the offset voltage, and;
[0030] In the second working state, the pulse clock S1000 output by the LOGIC module is low, S0100 is high, S0010 is low, S0001 is low, S1001 is low, and S0110 is high. The positive input and negative input terminals of the first zeroing amplifier are respectively input with vin1 and vin2, the storage capacitor is turned off, and the output terminal is in the signal output state. The positive input and negative input terminals of the second zeroing amplifier are respectively input with vin2 and vin1, the storage capacitor is turned off, the positive and negative output terminals are short-circuited, and the voltage of the storage capacitor is used to adjust the offset of the second zeroing amplifier.
[0031] In the third working state, the pulse S1000 output by the LOGIC module is low, S0100 is low, S0010 is high, S0001 is low, S1001 is low, and S0110 is high, the input channel is controlled, the positive input terminal and the negative input terminal of the first zeroing amplifier are short-circuited to input vin2, the storage capacitor is connected to the output terminal and stores the offset voltage, the positive input terminal and the negative input terminal of the second zeroing amplifier are connected to vin2 and vin1 respectively, the storage capacitor is turned off, and the output terminal is in a signal output state, and;
[0032] In the fourth working state, the pulse S1000 output by the LOGIC module is low, S0100 is low, S0010 is low, S0001 is high, S1001 is high, and S0110 is low. The positive input and negative input terminals of the first zeroing amplifier of the control input channel are respectively input with vin2 and vin1, the storage capacitor is turned off, the positive and negative output terminals are short-circuited, and the voltage of the storage capacitor is used to adjust the offset of the first zeroing amplifier. The positive input and negative input terminals of the second zeroing amplifier are respectively input with vin1 and vin2, the storage capacitor is turned off, and the output terminal is in the signal output state.
[0033] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.
[0034] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.
Claims
1. A zero adjustment circuit and a zero-drift operational amplifier using the same, used for zero adjustment of the output of a zero-drift operational amplifier, characterized in that: It includes a first zeroing amplifier, a second zeroing amplifier and a LOGIC module; The first zeroing amplifier has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal, and has a storage capacitor inside, wherein the positive input terminal and the negative input terminal are electrically connected to the first switch group and the second switch group respectively, and a first short circuit is electrically connected between the positive output terminal and the negative output terminal; The second zeroing amplifier has a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal, and has a storage capacitor inside, wherein the positive input terminal and the negative input terminal are electrically connected to the third switch group and the fourth switch group respectively, and a second short circuit is electrically connected between the positive output terminal and the negative output terminal; The pulse clock output by the LOGIC module acts on the switch group, the short circuit and the storage capacitor to control the first zeroing amplifier and the second zeroing amplifier to cyclically operate in four working states. In these four working states, the first zeroing amplifier and the second zeroing amplifier are alternately in the signal output state and the zeroing state.
2. The zero adjustment circuit and the zero-drift operational amplifier using the same according to claim 1, characterized in that: The first switch group includes three channels, each of which is equipped with a switch. The three channels are respectively input with voltages vin2, vin1 and vin2, and the output ends are electrically connected to the positive input end of the first zeroing amplifier. The second switch group includes three channels, each of which is equipped with a switch. The three channels are respectively input with voltages vin1, vin2 and vin2, and the output ends are electrically connected to the negative input end of the first zeroing amplifier. The switches on the three channels of the first switch group and the second switch group are respectively controlled by pulse clocks S1001, S0100, and S0010.
3. The zero adjustment circuit and the zero-drift operational amplifier using the same according to claim 1, characterized in that: The third switch group includes three channels, each of which is provided with a switch. The three channels are respectively input with voltages vin2, vin1 and vin2, and the output ends are electrically connected to the positive input end of the second zeroing amplifier. The fourth switch group includes three channels, each of which is provided with a switch. The three channels are respectively input with voltages vin1, vin2 and vin2, and the output ends are electrically connected to the negative input end of the second zeroing amplifier. The switches on the three channels of the third switch group and the fourth switch group are respectively controlled by pulse clocks S1000, S0110 and S0001.
4. The zero adjustment circuit and the zero-drift operational amplifier using the same according to claim 1, characterized in that: The first short-circuit circuit is connected in series with a plurality of switches, and the switches can be controlled by a pulse clock S0001.
5. The zero adjustment circuit and the zero-drift operational amplifier using the same according to claim 1, characterized in that: The second short-circuit circuit is connected in series with a plurality of switches, and the switches can be controlled by a pulse clock S0100.
6. The zero adjustment circuit and the zero-drift operational amplifier using the same according to claim 1, characterized in that: In the first working state, the pulse clock output by the LOGIC module controls the input channel, the positive input terminal and the negative input terminal of the first zeroing amplifier are respectively connected to vin2 and vin1, the storage capacitor is turned off, the output terminal is in a signal output state, the positive input terminal and the negative input terminal of the second zeroing amplifier are short-circuited, the storage capacitor is connected to the output terminal and stores the offset voltage, and; In the second working state, the positive input terminal and the negative input terminal of the first zeroing amplifier are respectively input with vin1 and vin2, the storage capacitor is turned off, and the output terminal is in a signal output state, the positive input terminal and the negative input terminal of the second zeroing amplifier are respectively input with vin2 and vin1, the storage capacitor is turned off, the positive and negative output terminals are short-circuited, and the voltage of the storage capacitor is used to adjust the offset of the second zeroing amplifier.
7. The zero adjustment circuit and the zero-drift operational amplifier using the same according to claim 6, characterized in that: In the third working state, the pulse clock output by the LOGIC module controls the input channel, the positive input terminal and the negative input terminal of the first zeroing amplifier are short-circuited, the storage capacitor is connected to the output terminal and stores the offset voltage, the positive input terminal and the negative input terminal of the second zeroing amplifier are connected to vin2 and vin1 respectively, the storage capacitor is turned off, and the output terminal is in a signal output state, and; In the fourth working state, the positive input terminal and the negative input terminal of the first zeroing amplifier are respectively input with vin2 and vin1, the storage capacitor is turned off, and the voltage of the storage capacitor is used to adjust the offset of the first zeroing amplifier. The positive input terminal and the negative input terminal of the second zeroing amplifier are respectively input with vin1 and vin2, the storage capacitor is turned off, and the output terminal is in a signal output state.