Neural signal readout circuit test system

Abstract

The utility model discloses a neural signal readout circuit test system, which comprises an FPGA, a DAC module, a neural interface and a stimulation interface, the neural interface is connected with the input end of a neural signal readout circuit to be tested, the output end of the neural signal readout circuit to be tested is connected with the FPGA, the output end of the FPGA is connected with the input end of the DAC module, and the stimulation interface is connected with the input end of the DAC module. The output end of the DAC module is connected with the stimulation interface. After a predetermined waveform test signal generated by the FPGA is converted into an analog signal through the DAC, the analog signal is safely transmitted to the bionic liquid medium simulating cerebrospinal fluid through the isolation drive and stimulation interface, captured by the nerve interface, and converted back to a digital signal by the reading circuit to be processed by the FPGA. According to the neural signal reading circuit, the test signal with specific frequency and amplitude can be generated through the FPGA and the DAC module, the neural signal is accurately collected, the quality and reliability of the signal are improved, and the performance of the neural signal reading circuit can be evaluated and tested more accurately.

Description

Technical Field

[0001] The utility model relates to the technical field of biomedical engineering, in particular to a neural signal readout circuit testing system. Background Art

[0002] Existing neural signal readout circuit test systems generally rely on oscilloscopes and signal generators to perform system tests on CMOS readout circuits. The operation process of such systems is relatively complex and involves the coordinated work of multiple independent devices.

[0003] Traditional neural signal readout circuit testing systems usually involve manual operations and lack the necessary standardized and automated processes, which affects the repeatability and reliability of test results. One of the main limitations of these systems is that it is difficult to effectively distinguish between valid signals and background noise in the circuit readout data during the test process. This deficiency is particularly evident when dealing with weak signals, which may lead to errors and inaccuracies in data interpretation.

[0004] In addition, current testing methods often fail to adequately simulate the characteristics of the human physiological environment, which may result in significant differences between the test results obtained in a laboratory environment and the performance in real in vivo applications. Therefore, these traditional systems may be limited in evaluating the actual performance of readout circuits in actual medical or bioscience applications. Utility Model Content

[0005] The utility model aims to solve at least one of the technical problems existing in the prior art and proposes a neural signal readout circuit testing system.

[0006] The technical solution of the utility model is implemented as follows: the utility model discloses a neural signal readout circuit test system, including a main control module, a stimulation circuit, a neural interface for signal acquisition, and a stimulation interface for stimulation signal output, wherein the neural interface is connected to the input end of the neural signal readout circuit to be tested, the output end of the neural signal readout circuit to be tested is connected to the main control module, the output end of the main control module is connected to the input end of the stimulation circuit, and the output end of the stimulation circuit is connected to the stimulation interface.

[0007] In some embodiments, the stimulation circuit includes a DAC module, an input end of the DAC module is connected to a main control module, and an output end of the main control module is connected to an input end of the DAC module.

[0008] In some embodiments, the stimulation circuit further includes an enhanced driving circuit, the input end of the enhanced driving circuit is connected to the output end of the DAC module, and the output end of the enhanced driving circuit is connected to the stimulation interface.

[0009] In some embodiments, the enhanced driving circuit uses a voltage follower.

[0010] In some embodiments, the neural signal readout circuit test system of the present invention further includes an isolation drive circuit, wherein the input end of the isolation drive circuit is connected to the main control module, and the output end of the isolation drive circuit is connected to the input end of the DAC module.

[0011] In some embodiments, the isolation driving circuit uses a digital isolator chip, the FPGA is connected to the digital isolator chip via an SPI interface, and the digital isolator chip is connected to the DAC module via the SPI interface.

[0012] In some embodiments, the neural signal readout circuit testing system of the present invention further includes a power supply, which is used to supply power to the entire system, and the ground of the neural signal readout circuit to be tested is connected to the ground of the stimulation circuit.

[0013] In some embodiments, the neural signal readout circuit testing system of the present invention further includes an industrial computer, which is connected to the main control module.

[0014] In some embodiments, the main control module uses FPGA.

[0015] In some embodiments, the neural signal readout circuit testing system of the present invention further comprises a container, wherein the container is filled with a bionic fluid simulating cerebrospinal fluid, and the electrodes of the stimulation interface and the neural interface are located in the bionic fluid.

[0016] Compared with the prior art, the utility model has the following beneficial effects:

[0017] The system of the utility model can realize high-precision signal generation and acquisition. Through the FPGA main control module and the high-precision DAC module, the system can generate a test signal with a specific frequency and amplitude and accurately acquire neural signals, which improves the quality and reliability of the signal, which is difficult to achieve with traditional systems.

[0018] The system of the utility model can simulate a real neural environment: the system uses a bionic liquid that simulates cerebrospinal fluid to simulate human brain tissue, providing a realistic medium for signal transmission. This innovative method is closer to the real biological environment and helps to more accurately evaluate and test the performance of the neural signal readout circuit.

[0019] The ground of the neural signal readout circuit to be measured is connected to the ground of the stimulation circuit, the main purpose of which is to reduce noise, and it also has the benefits of improving safety, stability and performance.

[0020] The system of the utility model can improve the test efficiency: the predetermined waveform signal generated by the FPGA is safely transmitted to the simulation environment after DAC conversion, and the efficient data processing capability of the industrial computer significantly shortens the time required for signal acquisition and analysis. This optimization not only improves the safety and accuracy of the test process, but also greatly improves the efficiency of the overall test process, making the development and calibration of neural interface devices faster and more efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of a neural signal readout circuit testing system provided by an embodiment of the utility model;

[0022] Figure 2 A principle block diagram of a neural signal readout circuit test system provided by an embodiment of the utility model;

[0023] Figure 3 A circuit diagram of a DAC module part provided for one embodiment of the utility model;

[0024] Figure 4 A schematic diagram of a stimulation circuit of a neural signal readout circuit testing system provided in one embodiment of the utility model. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0026] Unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described target changes, the relative positional relationship may also change accordingly.

[0027] In each of the accompanying drawings, identical elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not all drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0028] Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques and technologies of the components, so as to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0029] See also Figures 1 to 3 The embodiment of the utility model provides a neural signal readout circuit test system, including a power supply, a main control module, a stimulation circuit, a neural interface for signal acquisition (the neural interface is a neural interface matching the neural signal readout circuit to be tested) and a stimulation interface for stimulation signal output, the power supply is used to power the entire system, the neural interface is connected to the input end of the neural signal readout circuit to be tested, the output end of the neural signal readout circuit to be tested is connected to the main control module, the output end of the main control module is connected to the input end of the stimulation circuit, and the output end of the stimulation circuit is connected to the stimulation interface.

[0030] The power supply includes a power module for providing stable power to the system.

[0031] In some embodiments, the main control module adopts FPGA. The FPGA main control module is responsible for generating test signals of specific frequency and amplitude, and processing and uploading the data collected by the readout circuit. The FPGA model used in this embodiment is GWIN5NR-4C, which is an FPGA device produced by Gaoyun Semiconductor, with a hard-core MCU for generating waveform signals. The main functions of FPGA include using DDS technology / PWM technology to generate sinusoidal or square wave signals with corresponding accurate amplitude and phase according to the selected parameters, and generating waveforms by controlling DAC. At the same time, FPGA is responsible for collecting signals from the neural readout circuit, and transmitting multi-channel data to the industrial computer for in-depth waveform template comparison and correlation processing.

[0032] In some embodiments, the stimulation circuit includes a DAC module, the input end of the DAC module is connected to the main control module, and the output end of the main control module is connected to the input end of the DAC module. The DAC module of this embodiment adopts a digital-to-analog converter of model DAC8551, which is responsible for converting digital signals into analog signals, and the FPGA communicates with the DAC using the SPI protocol. The FPGA controls the digital-to-analog converter DAC8551 through the SPI protocol, uses DDS technology to generate sine / triangle / square wave signals, enhances the signal driving capability through a voltage follower, and imports the signal into a simulated cerebrospinal fluid environment.

[0033] The power supply also includes a DAC reference power supply for providing a reference voltage for the DAC module, the input end of the DAC reference power supply is connected to the output end of the power supply module, and the output end of the DAC reference power supply outputs the reference voltage.

[0034] In some embodiments, the stimulation circuit further includes an enhanced driving circuit, the input end of the enhanced driving circuit is connected to the output end of the DAC module, and the output end of the enhanced driving circuit is connected to the stimulation interface.

[0035] The high-precision DAC module, together with the enhanced drive circuit, ensures that the generated millivolt (mV) signal has high accuracy and stability, making it suitable for precise testing and signal quality assessment.

[0036] The enhanced driving circuit is used to ensure that the analog signal output from the DAC can drive the load of the next stage without being affected.

[0037] In some embodiments, the enhanced driving circuit uses a voltage follower, which is used to buffer the signal to prevent the signal source from being affected by the load.

[0038] In some embodiments, see Figure 4 The neural signal readout circuit test system of the utility model also includes an isolation drive circuit, the input end of the isolation drive circuit is connected to the main control module, and the output end of the isolation drive circuit is connected to the input end of the DAC module. The isolation drive circuit is used to provide isolation between different parts of the electronic system to prevent high voltage or current from damaging sensitive components. The isolation drive circuit of this embodiment adopts a digital isolator chip of model ADuM1440. ADuM1440 plays an isolation role to protect the DAC and subsequent circuits from voltage fluctuations or noise in the previous circuit. The FPGA is connected to the digital isolator chip via the SPI interface (SPI digital interface). The digital isolator chip is connected to the DAC module via the SPI interface.

[0039] The embodiment of the utility model uses a digital isolator to isolate the FPGA and the DAC. The main purpose is to improve the system reliability. Through isolation, the impact of the failure of one component on the rest of the system can be reduced. This isolation enhances the overall reliability and stability of the system and also improves safety: in applications that handle high voltages or work in harsh environments, isolation can provide an additional layer of safety.

[0040] In some embodiments, the ground of the neural signal readout circuit to be tested is connected to the ground of the stimulation circuit. That is, the stimulation circuit and the neural readout circuit of the system of the present invention are connected to the same ground. The following are the benefits of sharing the same ground:

[0041] 1. Improved safety: Common grounding can prevent the risk of electric shock due to equipment failure. When the current is abnormal (for example, due to a short circuit), common grounding provides a safe path for the current to flow back to the power source instead of through the human body.

[0042] 2. Improve stability and performance: In electronic systems, common ground can help ensure signal stability between devices. It provides a common reference point for electronic components, which is very important for ensuring accurate signal transmission.

[0043] 3. Reduce noise: Electrical noise is a common problem in electronic devices, and it can come from a variety of sources, including other electronic devices or natural interference. Common ground can help reduce this noise and improve the overall performance and reliability of the system.

[0044] 4. Electromagnetic compatibility: Common grounding helps control electromagnetic interference, which is very important for complying with electromagnetic compatibility (EMC) standards, which ensures the correct operation of the equipment in the electromagnetic environment and reduces interference with other devices.

[0045] 5. Prevent voltage fluctuations: In a system without a common ground, the voltage may fluctuate, resulting in unstable performance. The common ground provides a stable reference point to keep the voltage at the expected level.

[0046] In some embodiments, the main control module is connected to the neural signal readout circuit to be tested via an I2C interface.

[0047] The I2C of this embodiment is a control interface, and there may be different requirements for different neural signal readout circuits to be tested. The test of this embodiment uses the I2C interface. In addition, there should be a data interface between the main control module and the neural signal readout circuit to be tested. Here, it can also be adapted according to the circuit to be tested. The readout circuit to be tested in this embodiment uses the I2C interface.

[0048] In some embodiments, the neural signal readout circuit test system of the utility model further includes an industrial computer or a host computer, and the industrial computer or the host computer is connected to the main control module. The industrial computer has a waveform setting function, and the host computer can send a waveform parameter instruction to the main control module, the main control module generates a waveform according to the parameters, and the DAC module outputs a waveform signal. The acquisition signal of the neural readout circuit to be tested is sent to the main control module, and the main control module sends the acquisition data to the host computer. The host computer can compare the acquisition waveform signal with the set waveform (that is, the DAC module outputs the waveform signal) to draw a conclusion, or the host computer can also display the acquisition waveform signal and the set waveform signal, and draw a conclusion by comparing the acquisition waveform signal with the set waveform signal by the user, such as drawing a conclusion on the signal noise level and correlation difference of different channels.

[0049] In some embodiments, the industrial computer communicates with the FPGA to control the entire test process and perform waveform and data comparison to test and evaluate the performance of the neural signal readout circuit, thereby obtaining an accurate assessment of the signal noise level and correlation difference. The industrial computer is responsible for issuing control instructions, receiving collected signals, and performing noise comparison, and uses a USB interface to communicate with the FPGA. The industrial computer of the utility model can also display the output and collected waveforms and data for the user to compare the waveforms and data.

[0050] In some embodiments, the neural signal readout circuit test system of the utility model further comprises a container, wherein the container is filled with a bionic liquid simulating cerebrospinal fluid, and the electrodes of the stimulation interface and the neural interface are located in the bionic liquid and are independent of each other. The stimulation signal output by the stimulation circuit is output to the bionic liquid via the stimulation interface, and the neural interface is used to obtain the stimulation signal of the bionic liquid and transmit it to the neural signal readout circuit to be tested.

[0051] During the test, the microneedles of the neural interface and the stimulation interface are placed in the bionic liquid. The bionic liquid can be, but is not limited to, physiological saline. That is, the utility model can use physiological saline to simulate the brain area. The utility model simulates the human brain tissue by simulating the bionic liquid medium of cerebrospinal fluid, providing a realistic transmission medium for the signal. By simulating the conductivity of the human brain tissue by simulating the bionic liquid of cerebrospinal fluid, this design provides a realistic transmission medium for the test signal.

[0052] The neural readout circuit to be tested is a chip or circuit system for collecting EEG signals. The FPGA uses I2C or other communication methods to control the circuit and collect data according to the difference in chips. The neural readout circuit used in this embodiment is a CMOS chip to be tested, which is combined and connected with the microneedle interface. The microneedle is placed in a simulated cerebrospinal fluid environment for signal collection. The FPGA communicates with the CMOS chip through the I2C interface / SPI port, controls the CMOS chip for data collection, collects the collected data through the LVDS interface, and integrates and uploads the data through the USB protocol.

[0053] like Figure 2 The figure shows the entire process from signal generation to output, as well as the various stages of signal processing. In the entire process, the waveform parameters are transmitted from the host computer to the FPGA via USB, the FPGA communicates with the isolation module ADuM1440 via SPI, and the isolation module communicates with the DAC8551. Finally, the signal output by the DAC is processed by voltage follower and output to the liquid in the simulated brain area. After that, the neural readout circuit collects the signal and sends the collected data to the FPGA, which then sends the data to the host computer, and finally the data is compared on the host computer.

[0054] The system of the utility model mainly realizes signal generation, simulates neural environment, accurately collects neural signals, and comprehensively analyzes and compares the collected data. The predetermined waveform test signal generated by the FPGA of the utility model is converted into an analog signal by DAC, and then safely transmitted to the bionic liquid medium simulating cerebrospinal fluid through the isolation drive and stimulation interface. The signal propagates in this medium, is captured by the neural electrode, and is converted back into a digital signal by the readout circuit for FPGA processing. The processed data is then uploaded to the industrial computer, which is responsible for performing signal fidelity verification and readout accuracy analysis. This test method not only simulates and analyzes the transmission characteristics of neural signals, but also plays a vital role in the development and precise calibration of neural interface equipment.

[0055] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A neural signal readout circuit test system, characterized in that: It includes a main control module, a stimulation circuit, a neural interface for signal acquisition, and a stimulation interface for stimulation signal output. The neural interface is connected to the input end of the neural signal readout circuit to be tested, the output end of the neural signal readout circuit to be tested is connected to the main control module, the output end of the main control module is connected to the input end of the stimulation circuit, and the output end of the stimulation circuit is connected to the stimulation interface.

2. The neural signal readout circuit test system according to claim 1, characterized in that: The stimulation circuit comprises a DAC module, an input end of the DAC module is connected to a main control module, and an output end of the main control module is connected to an input end of the DAC module.

3. The neural signal readout circuit test system according to claim 2, characterized in that: The stimulation circuit also includes an enhanced driving circuit, the input end of the enhanced driving circuit is connected to the output end of the DAC module, and the output end of the enhanced driving circuit is connected to the stimulation interface.

4. The neural signal readout circuit test system according to claim 3, characterized in that: The enhanced driving circuit adopts a voltage follower.

5. The neural signal readout circuit test system according to claim 2, characterized in that: It also includes an isolation driving circuit, the input end of the isolation driving circuit is connected to the main control module, and the output end of the isolation driving circuit is connected to the input end of the DAC module.

6. The neural signal readout circuit test system according to claim 5, characterized in that: The isolation drive circuit adopts a digital isolator chip, the main control module is connected to the digital isolator chip through an SPI interface, and the digital isolator chip is connected to the DAC module through the SPI interface.

7. The neural signal readout circuit test system according to claim 1, characterized in that: It also includes a power supply, which is used to supply power to the entire system. The ground of the neural signal readout circuit to be tested is connected to the ground of the stimulation circuit.

8. The neural signal readout circuit testing system according to claim 1, characterized in that: It also includes an industrial computer, which is connected to the main control module.

9. The neural signal readout circuit test system according to any one of claims 1 to 8, characterized in that: The main control module adopts FPGA.

10. The neural signal readout circuit testing system according to claim 1, characterized in that: It also includes a container, in which is filled a bionic liquid simulating cerebrospinal fluid, and the electrodes of the stimulation interface and the neural interface are located in the bionic liquid.

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