Chip frame structure and chip packaging structure
By introducing hollowed-out through holes, trenches and silicon wafers into the chip frame structure, and combining with metal heat sinks, the cracking problem caused by mismatch in the thermal expansion coefficient of the gallium nitride chip packaging is solved, and the packaging is improved Stability and lifespan.
Patent Information
- Application Number
- CN202420910602.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-28
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2034-04-28
AI Technical Summary
Gallium nitride (GaN) chip packaging causes cracking between the chip and the packaging material due to mismatched thermal expansion coefficients, which in turn leads to cracking of the packaging material interface.
A chip frame structure is designed, including a base island and multiple pins. The base island is equipped with a packaged internal stress reduction structure, such as hollow through holes, trenches and silicon wafers, to reduce the between chip and base island. Package internal stress and release stress through heat dissipation structures such as metal heat sinks to avoid cracking.
It effectively avoids cracking between the chip and the packaging material, improves the stability and life of the chip package, and reduces the risk of cracks spreading to the chip and plastic sealing layer.
Smart Images
Figure CN222168389U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of packaging, and in particular to a chip frame structure and a chip packaging structure. Background Art
[0002] At present, the packaging of gallium nitride (GaN) chips mainly includes double-sided or quad flat leadless packages (DFN / QFN), with structures such as Figure 1 and Figure 2 As shown, Figure 1 It is a top view of a chip packaging structure provided by the prior art. Figure 2 yes Figure 1 The schematic diagram of the cross-sectional structure of the chip packaging structure in the A1-A2 direction is shown, and the chip packaging structure includes: a chip frame structure 100, a chip 200 and a plastic encapsulation layer 300. The chip frame structure 100 is made of metal copper. The chip frame structure 100 includes a base island 101 and a plurality of pins 102. The base island 101 is located in the middle of the chip frame structure 100, and the pins 102 are located on both sides of the base island 101. The pads of the chip 200 are connected to the pins 102 through copper wires. The first surface of the base island 101 is encapsulated with the chip 200, and the chip 200 and the base island 101 are bonded by a die bonding adhesive 201. The base island 101 is used to carry the chip 200. The plastic encapsulation layer 300 is located on one side of the first surface of the base island 101, covering the first surface of the base island 101, the chip 200, the pins 102, and the area between the base island 101 and the pins 102. The plastic encapsulation layer 300 exposes the pins 102 on one side of the second surface of the base island 101 which is arranged opposite to the first surface, and the surface of the base island 101. The second surface of the base island 101 can be used as a heat dissipation channel, and the pins 102 can be electrically connected to the printed circuit board. The chip frame structure 100 also includes a bonding conductive layer 103, and the area of the bonding conductive layer 103 is larger than the area of the pins 102. The pads of the chip 200 are connected to the bonding conductive layer 103 through copper wires, which reduces the difficulty of welding the copper wires to the bonding conductive layer 103, thereby achieving electrical connection between the pads of the chip 200 and the pins 102. It should be noted that in Figure 2 The cross-sectional structural diagram in FIG. 1 does not show the wire bonding conductive layer 103 .
[0003] With the development of electronic products, the size of the chip 200 is getting larger and larger. Due to the mismatch in thermal expansion coefficients between the chip 200 and the base island 101, cracks occur at the interface between the chip 200 and the packaging material, such as between the base island 101 and the plastic layer 300. Utility Model Content
[0004] The utility model provides a chip frame structure and a chip packaging structure to avoid cracking between the chip and the packaging material.
[0005] According to one aspect of the present invention, a chip frame structure is provided, comprising:
[0006] A base island, the base island comprising a first surface and a second surface arranged opposite to the first surface, and a chip is packaged in a chip packaging area of the first surface of the base island;
[0007] A plurality of pins, the plurality of pins are located on at least one side of the base island, and the pins are connected to pads of the chip through conductive wires;
[0008] The base island is provided with a package internal stress reduction structure, and the package internal stress reduction structure is used to reduce the package internal stress between the chip and the base island. Part or all of the package internal stress reduction structure is located in the chip packaging area.
[0009] Optionally, the stress reduction structure within the package includes a plurality of hollow through holes, and the plurality of hollow through holes are located on the base island.
[0010] Optionally, the thermal expansion coefficient of the stress reduction structure in the package matches the thermal expansion coefficient of the chip;
[0011] The base island is provided with a first groove, the first groove is located in the central area of the base island, the depth of the first groove is equal to the thickness of the base island, and the orthographic projection of the chip packaging area on the chip frame structure is located within the orthographic projection of the first groove on the chip frame structure;
[0012] The internal stress reduction structure of the package is located in the first groove and is used to support the chip.
[0013] Optionally, the stress reduction structure in the package includes a silicon chip, and the substrate of the chip is made of silicon material.
[0014] Optionally, the first groove includes a first sub-groove and a second sub-groove;
[0015] The first sub-groove is located on the first surface of the base island;
[0016] The second sub-groove is connected to the first sub-groove, and the second sub-groove is located on the second surface of the base island;
[0017] The opening of the first sub-groove is larger than the opening of the second sub-groove, and the sidewall of the first groove is in a step shape.
[0018] Optionally, the base island is provided with a second groove, the second groove is located in the central area of the base island, the depth of the second groove is equal to the thickness of the base island, and the orthographic projection of the second groove on the chip frame structure is located within the orthographic projection of the chip packaging area on the chip frame structure;
[0019] The base island is also provided with a heat dissipation structure, the heat dissipation structure is located in the second groove, and a gap is provided between the heat dissipation structure and the side wall of the second groove, and the gap serves as a stress reduction structure within the package;
[0020] The heat dissipation structure is connected to the chip via an adhesive layer.
[0021] Optionally, the heat dissipation structure includes a metal heat sink.
[0022] Optionally, the second groove includes a third sub-groove and a fourth sub-groove;
[0023] The third sub-groove is located on the first surface of the base island;
[0024] The fourth sub-groove is connected to the third sub-groove, and the fourth sub-groove is located on the second surface of the base island;
[0025] The opening of the third sub-groove is smaller than the opening of the fourth sub-groove, and the sidewall of the second groove is in a step shape;
[0026] The heat dissipation structure and the sidewall of the third sub-groove are provided with a first gap;
[0027] The heat dissipation structure and the sidewall of the fourth sub-groove are provided with a second gap, and the first gap and the second gap constitute the gap between the heat dissipation structure and the sidewall of the second groove;
[0028] The heat dissipation structure contacts a portion of the bottom surface of the fourth sub-trench.
[0029] Optionally, a groove is provided on a side of the base island away from the internal stress reduction structure of the package, the groove is located on the second surface of the base island, and the depth of the groove is less than the thickness of the base island.
[0030] According to another aspect of the present invention, a chip packaging structure is provided, comprising:
[0031] A chip frame structure, wherein the chip frame structure is the chip frame structure described in any of the embodiments of the present utility model;
[0032] A chip, wherein the chip is packaged in a chip packaging area on the first surface of the base island;
[0033] A plastic encapsulation layer, wherein the plastic encapsulation layer is located on one side of the first surface of the base island, and the plastic encapsulation layer covers the first surface of the base island, the chip, the pins, and an area between the base island and the pins.
[0034] The technical solution provided by the embodiment of the utility model is that a package internal stress reduction structure is set on the base island, and part or all of the package internal stress reduction structure is located in the chip packaging area. The package internal stress reduction structure can be used to reduce the package internal stress generated by the mismatch of thermal expansion coefficients between the chip and the base island, thereby avoiding cracks between the chip and the base island, and then avoiding the cracks from extending to between the chip and the plastic sealing layer, thereby avoiding cracks between the chip and the plastic sealing layer. In summary, the package internal stress reduction structure in the above technical solution is used to reduce the package internal stress generated by the mismatch of thermal expansion coefficients between the chip and the base island, thereby avoiding cracks between the chip and the packaging material.
[0035] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present utility model, nor are they intended to limit the scope of the present utility model. Other features of the present utility model will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0037] Figure 1 It is a top view of a chip packaging structure provided by the prior art;
[0038] Figure 2 yes Figure 1 A schematic cross-sectional structure diagram of a chip packaging structure in the A1-A2 direction is shown;
[0039] Figure 3 It is a top view of a chip packaging structure provided by an embodiment of the utility model;
[0040] Figure 4 yes Figure 3 A schematic cross-sectional structure diagram of a chip packaging structure in the A1-A2 direction is shown;
[0041] Figure 5 is a top view of another chip packaging structure provided by an embodiment of the utility model;
[0042] Figure 6 yes Figure 5 A schematic cross-sectional structure diagram of a chip packaging structure in the A1-A2 direction is shown;
[0043] Figure 7 It is a top view of another chip packaging structure provided by an embodiment of the utility model;
[0044] Figure 8 yes Figure 7 The schematic diagram of the cross-sectional structure of the chip packaging structure in the A1-A2 direction is shown. DETAILED DESCRIPTION
[0045] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.
[0046] It should be noted that the terms "first", "second", etc. in the specification and claims of the utility model and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the utility model described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or devices that are not clearly listed or inherent to these processes, methods, products or devices.
[0047] In order to avoid cracking between the chip and the packaging material, the embodiment of the utility model provides the following technical solutions:
[0048] like Figure 3 and Figure 4 As shown, Figure 3 is a top view of a chip packaging structure provided by an embodiment of the utility model, Figure 4 yes Figure 3 The schematic diagram of the cross-sectional structure of the chip packaging structure in the A1-A2 direction is shown, and the chip frame structure 400 includes: a base island 401, the base island 401 includes a first surface and a second surface arranged opposite to the first surface, and the chip 500 is packaged in the chip packaging area of the first surface of the base island 401; a plurality of pins 402, the plurality of pins 402 are located on at least one side of the base island 401, and the pins 402 are connected to the pads of the chip 500 through conductive wires; the base island 401 is provided with a package internal stress reduction structure 403, and the package internal stress reduction structure 403 is used to reduce the package internal stress between the chip 500 and the base island 401, and part or all of the package internal stress reduction structure 403 is located in the chip packaging area.
[0049] It should be noted that Figure 3 and Figure 4 In addition to the chip frame structure 400, the chip 500 and the plastic packaging layer 600 are also shown. Figure 3 The plastic encapsulation layer 600 is not shown. The chip frame structure 400, the chip 500 and the plastic encapsulation layer 600 constitute a chip packaging structure.
[0050] In this embodiment, the chip 500 is located in the chip packaging area and is bonded to the base island 401 by a die bonding adhesive 501 . The base island 401 is used to carry the chip 500 .
[0051] The technical solution provided by the embodiment of the utility model is that a package internal stress reduction structure 403 is set on the base island 401, and part or all of the package internal stress reduction structure 403 is located in the chip packaging area. The package internal stress reduction structure 403 can be used to reduce the package internal stress generated by the mismatch of thermal expansion coefficients between the chip 500 and the base island 401, thereby avoiding cracks between the chip 500 and the base island 401, and further avoiding cracks from extending to between the chip 500 and the plastic sealing layer 600, thereby avoiding cracks between the chip 500 and the plastic sealing layer 600. In summary, the package internal stress reduction structure 403 in the above technical solution is used to reduce the package internal stress generated by the mismatch of thermal expansion coefficients between the chip 500 and the base island 401, thereby avoiding cracks between the chip 500 and the packaging material.
[0052] Optionally, based on the above technical solution, Figure 3 and Figure 4 As shown, the stress reduction structure 403 in the package includes a plurality of hollow through holes, and the plurality of hollow through holes are located on the base island 401 .
[0053] Specifically, a plurality of hollow through holes are located on the base island 401, and the plurality of hollow through holes form a honeycomb structure. When the chip frame structure 400 is used to encapsulate the chip 500, the plurality of hollow through holes are used to release the internal stress of the package, thereby avoiding cracking between the chip 500 and the base island 401, and further avoiding the crack from extending to between the chip 500 and the plastic encapsulation layer 600, thereby avoiding cracking between the chip 500 and the plastic encapsulation layer 600. In summary, the package internal stress reduction structure 403 in the above technical solution is used to reduce the package internal stress generated by the mismatch of thermal expansion coefficients between the chip 500 and the base island 401, thereby avoiding cracking between the chip 500 and the packaging material.
[0054] Optionally, based on the above technical solution, Figure 5 and Figure 6 As shown, Figure 5 is a top view of another chip packaging structure provided by an embodiment of the utility model, Figure 6 yes Figure 5The schematic diagram of the cross-sectional structure of the chip packaging structure in the A1-A2 direction is shown, in which the thermal expansion coefficient of the internal stress reduction structure 403 in the chip frame structure 400 matches the thermal expansion coefficient of the chip 500; the base island 401 is provided with a first groove T1, the first groove T1 is located in the central area of the base island 401, the depth of the first groove T1 is equal to the thickness of the base island 401, and the orthographic projection of the chip packaging area on the chip frame structure 400 is located within the orthographic projection of the first groove T1 on the chip frame structure 400; the internal stress reduction structure 403 in the package is located in the first groove T1, and is used to support the chip 500.
[0055] Specifically, the orthographic projection of the chip packaging area on the chip frame structure 400 is located within the orthographic projection of the first groove T1 on the chip frame structure 400, so as to ensure that the package internal stress reduction structure 403 can support the chip 500, and the thermal expansion coefficient of the package internal stress reduction structure 403 matches the thermal expansion coefficient of the chip 500. The setting of the package internal stress reduction structure 403 makes it possible for there to be no package internal stress generated due to the mismatch of thermal expansion coefficients between the chip 500 and the base island 401, thereby avoiding cracks between the chip 500 and the base island 401, and further avoiding cracks from extending between the chip 500 and the plastic encapsulation layer 600, thereby avoiding cracks between the chip 500 and the plastic encapsulation layer 600. In summary, the package internal stress reduction structure 403 in the above technical solution is used to reduce the package internal stress generated due to the mismatch of thermal expansion coefficients between the chip 500 and the base island 401, thereby avoiding cracks between the chip 500 and the packaging material.
[0056] Optionally, based on the above technical solution, Figure 6 As shown, the stress reduction structure 403 in the package includes a silicon chip, and the substrate of the chip 500 is a silicon material.
[0057] Specifically, the package internal stress reduction structure 403 includes a silicon wafer, and the substrate of the chip 500 is a silicon material. The thermal expansion coefficients of the silicon wafer and the substrate of the chip 500 match. The setting of the package internal stress reduction structure 403 makes it possible for there to be no package internal stress generated by the mismatch of thermal expansion coefficients between the substrate of the chip 500 and the base island 401, thereby avoiding cracks between the chip 500 and the base island 401, and further avoiding cracks from extending between the chip 500 and the plastic sealing layer 600, thereby avoiding cracks between the chip 500 and the plastic sealing layer 600. In summary, the package internal stress reduction structure 403 in the above technical solution is used to reduce the package internal stress generated by the mismatch of thermal expansion coefficients between the chip 500 and the base island 401, thereby avoiding cracks between the chip 500 and the packaging material. And the silicon wafer can also be used as a heat dissipation channel.
[0058] Optionally, based on the above technical solution, Figure 6As shown, the first trench T1 includes a first sub-trench T01 and a second sub-trench T02; the first sub-trench T01 is located on the first surface of the base island 401; the second sub-trench T02 is connected to the first sub-trench T01, and the second sub-trench T02 is located on the second surface of the base island 401; the opening of the first sub-trench T01 is larger than the opening of the second sub-trench T02, and the sidewall of the first trench T1 is stepped.
[0059] Specifically, the stress reduction structure 403 in the package is located in the first groove T1 and is used to support the chip 500. The first groove T1 includes a first sub-groove T01 and a second sub-groove T02, so that the side wall of the first groove T1 is stepped, thereby increasing the contact area between the stress reduction structure 403 in the package and the side wall of the first groove T1, making the connection between the stress reduction structure 403 in the package and the base island 401 stronger, thereby improving the structural stability of the chip frame structure.
[0060] Optionally, based on the above technical solution, Figure 7 and Figure 8 As shown, Figure 7 is a top view of another chip packaging structure provided by an embodiment of the utility model, Figure 8 yes Figure 7 The schematic diagram of the cross-sectional structure of the chip packaging structure in the A1-A2 direction is shown, the base island 401 is provided with a second groove T2, the second groove T2 is located in the central area of the base island 401, the depth of the second groove T2 is equal to the thickness of the base island 401, and the orthographic projection of the second groove T2 on the chip frame structure 400 is located within the orthographic projection of the chip packaging area on the chip frame structure 400; the base island 401 is also provided with a heat dissipation structure 404, the heat dissipation structure 404 is located within the second groove T2, and a gap is set between the heat dissipation structure 404 and the side wall of the second groove T2, and the gap serves as a stress reduction structure 403 in the package; the heat dissipation structure 404 is connected to the chip 500 through an adhesive layer such as solder paste or silver glue.
[0061] Specifically, when the chip frame structure 400 is used to package the chip 500, the gap provided between the heat dissipation structure 404 and the sidewall of the second groove T2 is used to release the internal stress of the package, thereby avoiding cracking between the chip 500 and the base island 401, and further avoiding the crack from extending to between the chip 500 and the plastic encapsulation layer 600, thereby avoiding cracking between the chip 500 and the plastic encapsulation layer 600. In summary, the package internal stress reduction structure 403 in the above technical solution is used to reduce the package internal stress generated by the mismatch of thermal expansion coefficients between the chip 500 and the base island 401, thereby avoiding cracking between the chip 500 and the packaging material. And the heat dissipation structure 404 includes a metal heat sink as a heat dissipation channel to increase the heat dissipation capacity of the chip frame structure 400.
[0062] Optionally, based on the above technical solution, Figure 8 As shown, the second trench T2 includes a third sub-trench T03 and a fourth sub-trench T04; the third sub-trench T03 is located on the first surface of the base island 401; the fourth sub-trench T04 is connected to the third sub-trench T03, and the fourth sub-trench T04 is located on the second surface of the base island 401; the opening of the third sub-trench T03 is smaller than the opening of the fourth sub-trench T04, and the sidewall of the second trench T2 is stepped; the heat dissipation structure 404 and the sidewall of the third sub-trench T03 are provided with a first gap; the heat dissipation structure 404 and the sidewall of the fourth sub-trench T04 are provided with a second gap, and the first gap and the second gap constitute the gap between the heat dissipation structure 404 and the sidewall of the second trench T2; the heat dissipation structure 404 and the fourth sub-trench T04 are partially in contact with the bottom surface.
[0063] Specifically, when the chip frame structure 400 is used to package the chip 500, the first gap provided between the heat dissipation structure 404 and the side wall of the third sub-groove T03 and the second gap provided between the heat dissipation structure 404 and the side wall of the fourth sub-groove T04 are used to release the internal stress of the package, thereby avoiding cracking between the chip 500 and the base island 401, and further avoiding the crack from extending to between the chip 500 and the plastic encapsulation layer 600, thereby avoiding cracking between the chip 500 and the plastic encapsulation layer 600. In summary, the package internal stress reduction structure 403 in the above technical solution is used to reduce the package internal stress generated by the mismatch of thermal expansion coefficients between the chip 500 and the base island 401, thereby avoiding cracking between the chip 500 and the packaging material. And the heat dissipation structure 404 includes a metal heat sink as a heat dissipation channel to increase the heat dissipation capacity of the chip frame structure 400.
[0064] Optionally, based on the above technical solution, Figure 6 and Figure 8 As shown, a groove T3 is provided on the side of the base island 401 away from the package internal stress reduction structure 403 . The groove T3 is located on the second surface of the base island 401 , and the depth of the groove T3 is less than the thickness of the base island 401 .
[0065] Specifically, the provision of the groove T3 can increase the contact area between the base island 401 and the plastic packaging layer 600, thereby increasing the firmness of the chip packaging structure.
[0066] like Figure 3-Figure 8 As shown, an embodiment of the present invention further provides a chip packaging structure, which includes: a chip frame structure 400, the chip frame structure 400 is such as the chip frame structure 400 described in any embodiment of the present invention; a chip 500, the chip 500 is encapsulated in the chip packaging area of the first surface of the base island 401; a plastic encapsulation layer 600, the plastic encapsulation layer 600 is located on one side of the first surface of the base island 401, and the plastic encapsulation layer 600 covers the first surface of the base island 401, the chip 500, the pin 402, and the area between the base island 401 and the pin 402.
[0067] The chip packaging structure provided by the embodiment of the utility model has a package internal stress reduction structure 403 set on the base island 401, and part or all of the package internal stress reduction structure 403 is located in the chip packaging area. The package internal stress reduction structure 403 can be used to reduce the package internal stress generated by the mismatch of thermal expansion coefficients between the chip 500 and the base island 401, thereby avoiding cracks between the chip 500 and the base island 401, and further avoiding cracks from extending between the chip 500 and the plastic sealing layer 600, thereby avoiding cracks between the chip 500 and the plastic sealing layer 600. In summary, the package internal stress reduction structure 403 in the above technical solution is used to reduce the package internal stress generated by the mismatch of thermal expansion coefficients between the chip 500 and the base island 401, thereby avoiding cracks between the chip 500 and the packaging material.
[0068] For example, Figure 3 and Figure 4 The preparation method of the chip packaging structure shown is as follows:
[0069] A plurality of hollow through holes are made on the base island 401 by etching process, and the plurality of hollow through holes form a honeycomb structure. The thinned and single chip 500 is mounted on the chip frame structure 400 by using a mounting adhesive 501. The pad of the chip 500 is welded to the pin 402 by a conductive welding wire. A plastic sealing layer 600 is formed and cured. An electroplating layer is formed on the surface of the pin 402, and it is cut into single pieces and electrically connected to the printed circuit board.
[0070] For example, Figure 5 and Figure 6 The preparation method of the chip packaging structure shown is as follows:
[0071] The first groove T1 is made in the central area of the base island 401 by etching process. A silicon wafer is formed in the first groove T1 as a package internal stress reduction structure 403, which is used to reduce the package internal stress generated by the mismatch of thermal expansion coefficients between the chip 500 and the base island 401, thereby avoiding cracking between the chip 500 and the packaging material. It can also be used as a heat sink to provide a heat dissipation channel. The thinned and single-piece chip 500 is mounted on the chip frame structure 400 with a mounting glue 501. The pad of the chip 500 is welded to the pin 402 through a conductive welding wire. A plastic sealing layer 600 is formed and cured. An electroplating layer is formed on the surface of the pin 402, and it is cut into single pieces and electrically connected to the printed circuit board.
[0072] For example, Figure 7 and Figure 8 The preparation method of the chip packaging structure shown is as follows:
[0073] A second groove T2 is made in the central area of the base island 401 by etching process. The thinned and single chip 500 is mounted on the chip frame structure 400 with a mounting glue 501. The pad of the chip 500 is welded to the pin 402 by conductive welding wire. A plastic encapsulation layer 600 is formed and cured. A heat dissipation structure 404 is formed in the second groove T2, and a gap is set between the heat dissipation structure 404 and the side wall of the second groove T2, and the gap serves as a stress reduction structure 403 in the package. An electroplating layer is formed on the surface of the pin 402, and it is cut into single pieces and electrically connected to the printed circuit board.
[0074] Optionally, based on the above technical solution, a printed circuit board is further included, and the pins 402 of the chip packaging structure are electrically connected to the printed circuit board.
[0075] Specifically, the printed circuit board is provided with an external circuit required by the chip packaging structure. The pins 402 of the chip packaging structure can be electrically connected to the printed circuit board through a welding process.
[0076] It should be noted that the chip 500 in the embodiment of the present invention includes but is not limited to a gallium nitride chip.
[0077] It should be noted that the chip frame structure 400 also includes a wire bonding conductive layer 405, and the area of the wire bonding conductive layer 405 is larger than the area of the pin 402. The pads of the chip 500 are connected to the wire bonding conductive layer 405 through conductive wires, such as copper wires, which reduces the difficulty of welding the copper wires to the wire bonding conductive layer 405, thereby achieving electrical connection between the pads of the chip 500 and the pins 402. Figure 4 , Figure 6 and Figure 8 The cross-sectional structural diagram in FIG. 4 does not show the wire bonding conductive layer 405 .
[0078] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.
[0079] The above specific implementations do not constitute a limitation on the protection scope of the present utility model. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present utility model shall be included in the protection scope of the present utility model.
Claims
1. A chip frame structure, characterized in that: include: A base island, the base island comprising a first surface and a second surface arranged opposite to the first surface, and a chip is packaged in a chip packaging area of the first surface of the base island; A plurality of pins, the plurality of pins are located on at least one side of the base island, and the pins are connected to pads of the chip through conductive wires; The base island is provided with a package internal stress reduction structure, and the package internal stress reduction structure is used to reduce the package internal stress between the chip and the base island. Part or all of the package internal stress reduction structure is located in the chip packaging area.
2. The chip frame structure according to claim 1, characterized in that: The package internal stress reduction structure includes a plurality of hollow through holes, and the plurality of hollow through holes are located on the base island.
3. The chip frame structure according to claim 1, characterized in that: The thermal expansion coefficient of the stress reduction structure in the package matches the thermal expansion coefficient of the chip; The base island is provided with a first groove, the first groove is located in the central area of the base island, the depth of the first groove is equal to the thickness of the base island, and the orthographic projection of the chip packaging area on the chip frame structure is located within the orthographic projection of the first groove on the chip frame structure; The internal stress reduction structure of the package is located in the first groove and is used to support the chip.
4. The chip frame structure according to claim 3, characterized in that: The stress reduction structure in the package includes a silicon chip, and the substrate of the chip is made of silicon material.
5. The chip frame structure according to claim 3, characterized in that: The first groove includes a first sub-groove and a second sub-groove; The first sub-groove is located on the first surface of the base island; The second sub-groove is connected to the first sub-groove, and the second sub-groove is located on the second surface of the base island; The opening of the first sub-groove is larger than the opening of the second sub-groove, and the sidewall of the first groove is in a step shape.
6. The chip frame structure according to claim 1, characterized in that: The base island is provided with a second groove, the second groove is located in the central area of the base island, the depth of the second groove is equal to the thickness of the base island, and the orthographic projection of the second groove on the chip frame structure is located within the orthographic projection of the chip packaging area on the chip frame structure; The base island is also provided with a heat dissipation structure, the heat dissipation structure is located in the second groove, and a gap is provided between the heat dissipation structure and the side wall of the second groove, and the gap serves as a stress reduction structure within the package; The heat dissipation structure is connected to the chip via an adhesive layer.
7. The chip frame structure according to claim 6, characterized in that: The heat dissipation structure includes a metal heat sink.
8. The chip frame structure according to claim 6, characterized in that: The second groove includes a third sub-groove and a fourth sub-groove; The third sub-groove is located on the first surface of the base island; The fourth sub-groove is connected to the third sub-groove, and the fourth sub-groove is located on the second surface of the base island; The opening of the third sub-groove is smaller than the opening of the fourth sub-groove, and the sidewall of the second groove is in a step shape; The heat dissipation structure and the sidewall of the third sub-groove are provided with a first gap; The heat dissipation structure and the sidewall of the fourth sub-groove are provided with a second gap, and the first gap and the second gap constitute the gap between the heat dissipation structure and the sidewall of the second groove; The heat dissipation structure contacts a portion of the bottom surface of the fourth sub-trench.
9. The chip frame structure according to claim 3 or 6, characterized in that: A groove is arranged on a side of the base island away from the internal stress reduction structure of the package. The groove is located on the second surface of the base island, and the depth of the groove is less than the thickness of the base island.
10. A chip packaging structure, characterized in that: include: A chip frame structure, wherein the chip frame structure is a chip frame structure as claimed in any one of claims 1 to 9; A chip, wherein the chip is packaged in a chip packaging area on the first surface of the base island; A plastic encapsulation layer is located on one side of the first surface of the base island, and covers the first surface of the base island, the chip, the pins, and an area between the base island and the pins.