Fan-out wafer level packaging structure for realizing interconnection of MEMS (Micro Electro Mechanical System) chips

Abstract

The utility model discloses a fan-out type wafer level packaging structure for realizing interconnection of MEMS (Micro Electro Mechanical System) chips. The fan-out type wafer level packaging structure comprises an eWLB-F chip and an MEMS chip which is inversely arranged on the eWLB-F chip, the eWLB-F chip comprises a chip I, a plastic package layer and a rewiring layer I, the plastic package layer wraps the chip I and exposes a bonding area of the chip I, the rewiring layer I is located on the plastic package layer and is interconnected with the chip I, a bonding pad I and a bonding pad II are arranged on the surface of the rewiring layer I, and a welding ball I is planted on the bonding pad I; the MEMS chip comprises a second chip and a second solder ball, and the second solder ball of the flip MEMS chip and the second bonding pad of the first rewiring layer are interconnected, filled and solidified. According to the utility model, interconnection of the eWLB-F chip and the MEMS chip which are independently manufactured in advance is realized by adopting a flip-chip technology, the packaging process is simplified, the alignment precision is improved, and the underfill process is carried out, so that the connection stability of the chips is ensured, and the reliability and the performance of products are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor packaging, and more specifically to a fan-out wafer-level packaging structure capable of realizing MEMS chip interconnection. Background Art

[0002] Electronic packaging technology is a process that seals semiconductor integrated circuit chips in a protective shell to prevent physical damage and environmental factors. This technology plays a vital role in modern electronic devices because it protects the chips and improves their reliability and performance. The field of semiconductor device manufacturing refers to the process of making silicon wafers into integrated circuits with specific electrical characteristics through a series of complex process flows. Microelectromechanical System (MEMS) technology is an innovative technology that combines microelectronics technology and mechanical engineering. It can manufacture various micro-mechanical and electronic devices on a tiny scale.

[0003] In the existing technology, a common solution is to use traditional wire bonding technology to connect the chip to the packaging substrate. Another method is to use flip chip technology to directly mount the chip on the packaging substrate and achieve electrical connection through solder bumps. However, these methods can usually only handle chips of the same size. For chips of different sizes, different packaging technologies need to be used, which increases manufacturing costs and complexity. In addition, when dealing with tiny MEMS chips, existing packaging technologies may have problems such as low alignment accuracy and unstable solder bump quality, which will affect product reliability and performance. Utility Model Content

[0004] In order to solve the above problems, the utility model provides a fan-out wafer-level packaging structure for realizing MEMS chip interconnection, so that the MEMS chip is interconnected with the eWLB-F chip packaging structure, and the interconnection of chips of different sizes is realized. The tiny MEMS chip is accurately aligned and the quality of the connection is stable, thereby improving product reliability and performance.

[0005] According to one aspect of the utility model, a fan-out wafer-level packaging structure for realizing MEMS chip interconnection is provided, comprising a MEMS chip and an eWLB-F chip, wherein the MEMS chip is flip-chip mounted on the eWLB-F chip;

[0006] The eWLB-F chip comprises a chip 1, a plastic encapsulation layer and a redistribution layer 1, wherein the plastic encapsulation layer encapsulates the chip 1 and exposes the bonding area of ​​the chip 1, the redistribution layer 1 is located on the plastic encapsulation layer, the redistribution layer 1 comprises at least one dielectric layer (11), at least one metal interconnection layer (12) located in the dielectric layer (11), the metal interconnection layer of the redistribution layer 1 is interconnected with the bonding area of ​​the chip 1, and the upper surface of the redistribution layer 1 comprises a solder pad 1 and a solder pad 2, and a solder ball 1 is implanted on the solder pad 1;

[0007] The MEMS chip comprises a second chip and a second solder ball. The bonding area of ​​the second chip is interconnected with the second solder ball. The flip-chip arrangement of the MEMS chip interconnects the second solder ball with a second solder pad of the first redistribution layer.

[0008] Therefore, the eWLB-F chip and the MEMS chip are first manufactured separately to simplify the packaging process and improve production efficiency. The MEMS chip and the eWLB-F chip packaging structure are interconnected without increasing the manufacturing cost and complexity. The MEMS chip uses a flip-chip machine to ensure that the solder ball 2 of the MEMS chip is aligned with the solder pad 2 reserved on the surface of the eWLB-F chip to improve the alignment accuracy of the MEMS chip. The design of the packaging structure realizes the interconnection of two chips of different sizes.

[0009] In some embodiments, the MEMS chip further includes a second redistribution layer, which includes at least one dielectric layer and at least one metal interconnection layer in the dielectric layer, the metal interconnection layer of the second redistribution layer is interconnected with the bonding area of ​​the second chip, the surface of the second redistribution layer has a pad three, and the second solder ball is implanted on the pad three. Thus, the I / O port of the tiny MEMS chip is re-arranged through the second redistribution layer, so that the pitch of the I / O port of the MEMS chip is looser, and the connection stability between chips is improved.

[0010] In some embodiments, the maximum diameter of solder ball 2 is 70-80 μm, and the height of the top of solder ball 2 protruding from the surface of redistribution layer 2 is 60-80 μm. Thus, solder ball 2 of qualified size ensures the stability of chip connection during flip-chip soldering of MEMS chip.

[0011] In some embodiments, the thickness of the MEMS chip is 100-200 μm. Therefore, after the MEMS chip is manufactured with solder balls of qualified size, the MEMS chip can be ground to a thickness of 100-200 μm for subsequent flip-chip bonding.

[0012] In some embodiments, the gap between the flipped MEMS chip and the redistribution layer 1 is filled and cured with a filler. Thus, the gap between the pad 2 on the eWLB-F chip structure and the solder ball 2 of the MEMS chip is filled with epoxy resin filler and cured by the siphon principle through the underfill process, which can improve the stability of the chip and the performance of the product.

[0013] In some embodiments, the eWLB-F chip further includes a supporting silicon layer, which is disposed at the bottom of the plastic packaging layer. Thus, the supporting silicon layer plays a protective role and can be thinned as a whole by grinding to achieve a thickness.

[0014] Compared with the prior art, the beneficial effects of the utility model are as follows: the fan-out wafer-level packaging structure for realizing MEMS chip interconnection provided by the utility model adopts the flip-chip technology to interconnect the pre-separately manufactured eWLB-F chip and the MEMS chip, simplifying the packaging process, improving production efficiency, and realizing the interconnection of two chips of different sizes without increasing the manufacturing cost and complexity. The flip-chip technology is used to align the solder ball 2 of the MEMS chip with the solder pad 2 reserved on the surface of the eWLB-F chip, thereby improving the positioning accuracy of the MEMS chip, and after alignment, reflow soldering and underfill process are performed and solidified, thereby improving the flexibility and adaptability of the product. This process not only ensures the connection stability of the chip, but also effectively reduces the manufacturing cost and complexity, and improves the overall reliability and performance of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of a preparation process of an embodiment of a MEMS chip;

[0016] Figure 2 is a schematic diagram of a preparation process of an embodiment of an eWLB-F chip;

[0017] Figure 3 It is a schematic diagram of the packaging process of flip-chipping the MEMS chip onto the eWLB-F chip;

[0018] Figure 4 It is a structural schematic diagram of an implementation method of a fan-out wafer-level packaging structure for interconnecting MEMS chips. DETAILED DESCRIPTION

[0019] The utility model is further described below in conjunction with specific implementation methods.

[0020] like Figure 4 As shown, an embodiment of the utility model describes a fan-out wafer-level packaging structure for realizing MEMS chip interconnection, which includes a MEMS chip and an eWLB-F chip. The MEMS chip is flipped on the eWLB-F chip, and the eWLB-F chip is a resin fan-out packaging structure.

[0021] The eWLB-F chip includes a chip 1, a plastic encapsulation layer 2 and a redistribution layer 3. The plastic encapsulation layer 2 wraps the bottom and surrounding of the chip 1 and exposes the bonding area 11 of the chip 1. The redistribution layer 3 is located on the plastic encapsulation layer 2. The redistribution layer 3 includes at least one dielectric layer 31 and at least one metal interconnection layer 32 located in the dielectric layer 31. The metal interconnection layer 32 at the bottom of the redistribution layer 3 is interconnected with the bonding area 11 of the chip 1. The upper surface of the redistribution layer 3 has a pad 1 33 and a pad 2 34. The pad 1 33 is planted with a solder ball 5. In practical applications, the redistribution layer 3 can be a structure in which multiple metal interconnection layers 32 are interconnected. The eWLB-F chip also includes a supporting silicon layer 4, which is arranged at the bottom of the plastic encapsulation layer 2. The supporting silicon layer 4 plays a protective role and can be thinned as a whole by grinding to achieve a thickness.

[0022] The MEMS chip includes a second chip 6 and a second solder ball 8. The bonding area 61 of the second chip 6 is interconnected with the second solder ball 8. The MEMS chip is flip-chip mounted on the eWLB-F chip so that the second solder ball 8 is interconnected with the second pad 34 of the redistribution layer 1 3.

[0023] In the application, the MEMS chip may also include a second redistribution layer 7, which includes at least one dielectric layer 71 and at least one metal interconnection layer 72 located in the dielectric layer 71. The metal interconnection layer 72 of the second redistribution layer 7 is interconnected with the bonding area 61 of the second chip 6. The surface of the second redistribution layer 7 has a pad 3 73, and the solder ball 2 8 is implanted on the pad 3 73. The I / O port of the tiny MEMS chip is rearranged by the second redistribution layer 7, so that the pitch of the I / O port of the MEMS chip is looser, and the connection stability between chips is improved. The second redistribution layer 7 may also be a structure in which multiple metal interconnection layers 72 are interconnected.

[0024] On the MEMS chip, the maximum diameter of the solder ball 28 is 70-80 μm, the height of the top of the solder ball 28 protruding relative to the surface of the redistribution layer 27 is 60-80 μm, and the overall thickness of the MEMS chip is 100-200 μm. The solder ball 28 of the qualified size ensures the stability of the chip connection during the flip-chip welding of the MEMS chip. After the MEMS chip is made with the solder ball 28 of the qualified size, the MEMS chip can be ground to make the chip thickness reach 100-200 μm for subsequent flip-chip welding.

[0025] The gap between the flipped MEMS chip and the redistribution layer 1 3 is filled and cured with filler 9. Through the underfill process, the gap between the pad 2 34 on the eWLB-F chip structure and the solder ball 2 8 of the MEMS chip is filled with epoxy resin filler 9 and cured by the siphon principle, which can improve the stability of the chip and the performance of the product.

[0026] Combination Figures 1 to 3 , specifically describing the packaging process of the fan-out wafer-level packaging structure for implementing MEMS chip interconnection in this embodiment, the steps are as follows:

[0027] Step 1: Prepare MEMS chip: Figure 1 As shown, a PI layer, that is, a dielectric layer 71, is formed on the chip 2 6, and a pattern opening is formed to expose the bonding area 61 of the chip 2 6 ( Figure 1 1A), a metal interconnection layer 72 is formed on the dielectric layer 71, the metal interconnection layer 72 is connected to the bonding area 61 of the chip 2 6, and then the dielectric layer 71 is formed to cover the metal interconnection layer 72 ( Figure 1 1B), the metal interconnection layer 72 and the dielectric layer 71 form a redistribution layer 2 7, a pattern opening is formed on the dielectric layer 71 on the surface of the redistribution layer 2 7 to expose the metal interconnection layer 72, and a tiny pad 3 73 is formed at the opening, the pad 3 73 is interconnected with the metal interconnection layer 72, and a ball is planted on the pad 3 73 to form a solder ball 2 8 ( Figure 1 1C). The height of the solder ball 8 is 60-80 μm and the size is 70-80 μm. The MEMS chip is then ground to a thickness of 100-200 μm to meet the packaging thickness requirement. The chip is then diced and cut into individual MEMS chips to prepare for subsequent flip-chip welding.

[0028] Step 2: Prepare eWLB-F chip: Figure 2 As shown, the incoming wafer is first cut into individual pieces to form a chip 1, and then flip-chip mounted on the ABF film 100 to expand the package die area. The ABF film 100 is disposed on a carrier wafer 101 (optionally glass), as shown in FIG. Figure 2 2A; performing processes such as gluing, exposure, development, sputtering, and electroplating to form a plastic encapsulation layer 2 ( Figure 2 2B), a supporting silicon layer 4 is formed on the plastic encapsulation layer 2 ( Figure 2 2C), peel off the ABF film 100 ( Figure 2 As shown in 2D, Figure 2 As shown in FIG. 2E, RDL (i.e., redistribution layer 13) and UBM (i.e., pad 1 33, pad 2 34, and solder ball 15 implanted on pad 1 33) are formed on chip 1, and a portion of the pad area (i.e., pad 2 34) is reserved without any process for MEMS chip flip-chip. This design can effectively realize the interconnection of MEMS chips and improve the flexibility and adaptability of the product.

[0029] Step 3: Flip-chip MEMS chip: Figure 3As shown in Figure 3A, the MEMS chip with a bump (i.e., solder ball 2 8) grown thereon is flipped onto the reserved area of ​​the eWLB-F chip packaging structure, i.e., the reserved solder pad 2 34. The flip-chip machine is used to ensure that the solder ball 2 8 of the MEMS chip is aligned with the solder pad 2 34 on the eWLB-F chip. Then, reflow soldering is performed to firmly connect the MEMS chip to the eWLB-F chip.

[0030] Step 4: Clean the package structure: Scrub the completed flip-chip package structure to ensure the connection quality and stability of the solder balls.

[0031] Step 5: Bottom filling: After cleaning, the underfill process is performed to fill the gap between the pad 24 of the eWLB-F chip and the solder ball 28 of the MEMS chip with epoxy resin through the siphon principle and solidify it. The filler 9 should cover the solder ball 28 and the lower part of the MEMS chip, such as Figure 3 As shown in Figure 3B, this can not only improve the stability of the chip, but also improve the performance of the product.

[0032] Step 6: Thinning and slicing: Thin the whole to about 300μm through grinding, and then cut it into countless independent packages after film bonding to complete the overall packaging process, such as Figure 4 shown.

[0033] The fan-out wafer-level packaging structure for interconnecting MEMS chips provided by the utility model uses flip-chip technology to interconnect the pre-fabricated eWLB-F chip and the MEMS chip, simplifying the packaging process, improving production efficiency, and realizing the interconnection of two chips of different sizes without increasing manufacturing cost and complexity. The solder ball 28 of the MEMS chip is aligned with the solder pad 234 reserved on the surface of the eWLB-F chip by using flip-chip technology, improving the alignment accuracy of the MEMS chip, and performing reflow soldering and underfill process and curing after alignment, thereby improving the flexibility and adaptability of the product. This process can not only ensure the connection stability of the chip, but also effectively reduce the manufacturing cost and complexity, and improve the overall reliability and performance of the product.

[0034] The above are only some embodiments of the present invention. It should be pointed out that for ordinary technicians in this field, other modifications and improvements can be made without departing from the creative concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A fan-out wafer-level packaging structure for realizing MEMS chip interconnection, comprising a MEMS chip and an eWLB-F chip, characterized in that: The MEMS chip is flip-mounted on the eWLB-F chip; The eWLB-F chip comprises a chip (1), a plastic encapsulation layer (2) and a redistribution layer (3), wherein the plastic encapsulation layer (2) encapsulates the chip (1) and exposes the bonding area of ​​the chip (1), the redistribution layer (3) is located on the plastic encapsulation layer (2), the redistribution layer (3) comprises at least one dielectric layer and at least one metal interconnection layer located in the dielectric layer, the metal interconnection layer of the redistribution layer (3) is interconnected with the bonding area of ​​the chip (1), the upper surface of the redistribution layer (3) comprises a solder pad (33) and a solder pad (34), and a solder ball (5) is implanted on the solder pad (33); The MEMS chip comprises a second chip (6) and a second solder ball (8), the bonding area of ​​the second chip (6) is interconnected with the second solder ball (8), and the flip-chip arrangement of the MEMS chip enables the second solder ball (8) to be interconnected with a second solder pad (34) of a first redistribution layer (3).

2. The fan-out wafer-level packaging structure for realizing MEMS chip interconnection according to claim 1, characterized in that: The MEMS chip further comprises a second redistribution layer (7), wherein the second redistribution layer (7) comprises at least one dielectric layer and at least one metal interconnection layer located in the dielectric layer, wherein the metal interconnection layer of the second redistribution layer (7) is interconnected with the bonding area of ​​the second chip (6), and the surface of the second redistribution layer (7) comprises a third solder pad (73), and the second solder ball (8) is implanted on the third solder pad (73).

3. The fan-out wafer-level packaging structure for realizing MEMS chip interconnection according to claim 2, characterized in that: The maximum diameter of the solder ball 2 (8) is 70-80 μm, and the height of the top of the solder ball 2 (8) protruding relative to the surface of the redistribution layer 2 (7) is 60-80 μm.

4. The fan-out wafer-level packaging structure for realizing MEMS chip interconnection according to claim 3, characterized in that: The thickness of the MEMS chip is 100-200 μm.

5. The fan-out wafer-level packaging structure for realizing MEMS chip interconnection according to any one of claims 1 to 4, characterized in that: The space between the flipped MEMS chip and the redistribution layer 1 (3) is filled and cured with a filler (9).

6. The fan-out wafer-level packaging structure for realizing MEMS chip interconnection according to claim 5, characterized in that: The eWLB-F chip further comprises a supporting silicon layer (4), wherein the supporting silicon layer (4) is arranged at the bottom of the plastic sealing layer (2).

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