Silicon wafer coating carrier and vacuum coating equipment

Abstract

The utility model belongs to the technical field of solar cell manufacturing, and particularly discloses a silicon wafer coating carrier which is provided with a sinking groove, the groove bottom of the sinking groove is provided with a placing area for placing a silicon wafer, and the groove wall of the sinking groove is convexly provided with a first limiting piece for limiting the side edge of the silicon wafer along the direction pointing to the silicon wafer. The thickness size of the first limiting piece in the thickness direction of the silicon wafer coating carrier is h, the length size of the first limiting piece protruding out of the groove wall in the direction that the groove wall points to the placing area is L, theta = arctan (h / L), the minimum incident angle of a gas group emitted by the emission source at the edge of the sinking groove is theta ', and theta is smaller than or equal to theta'. The edge of the silicon wafer is supported by the first limiting piece to leave the groove wall of the sinking groove for a certain distance, gas groups emitted by the emission source bypass the groove wall of the sinking groove to reach the edge of the silicon wafer, the shielding phenomenon of the groove wall on the gas groups is reduced, the film-coated surface of the silicon wafer is uniformly deposited to form a film, and the film-coated quality is better. The utility model further provides vacuum coating equipment which comprises the silicon wafer coating carrier.

Description

Technical Field

[0001] The utility model relates to the technical field of solar cell manufacturing, in particular to a silicon wafer coating carrier and vacuum coating equipment. Background Art

[0002] In the thin film production process of solar cells, vacuum silicon wafer coating equipment is used to coat silicon wafers with thin films, such as CAT-CVD equipment (hot wire chemical vapor deposition equipment), PECVD equipment (plasma chemical vapor deposition equipment), etc. The reaction principle of CAT-CVD equipment is that the process gas is cracked under the high temperature and catalytic action of the hot wire and then deposited on the surface of the silicon wafer, thereby obtaining the required process film on the surface of the silicon wafer.

[0003] During the coating process, a tray is usually used to carry silicon wafers, and then the tray is placed in an atmosphere of process gas for coating reaction. A sink is generally provided on the tray to place the silicon wafer. However, during the coating process, since most gas groups move in a linear manner, the wall of the sink will block the gas groups, resulting in the formation of shadow areas at the edge of the silicon wafer where the gas groups cannot reach, which is not conducive to the deposition of films at the edge of the silicon wafer. Finally, the film on the surface of the silicon wafer is thick in the middle and thin around the edges, and the coating uniformity is poor. Utility Model Content

[0004] The purpose of the utility model is to provide a silicon wafer coating carrier and a vacuum coating device, which can support and limit the edge of the silicon wafer so that the edge of the silicon wafer is away from the wall of the sinking tank for a certain distance, thereby alleviating the shielding phenomenon of the wall of the sinking tank to the gas groups, which is beneficial to improving the uniformity of the film deposition on the surface of the silicon wafer and improving the coating quality.

[0005] To achieve this purpose, the utility model adopts the following technical solutions:

[0006] On the one hand, the utility model provides a silicon wafer coating carrier, which can be used to support a silicon wafer so that gas radicals emitted by an emission source are deposited on the silicon wafer.

[0007] Optionally, the silicon wafer coating carrier is applied to a vacuum coating device, the vacuum coating device has an emission source, the silicon wafer coating carrier is used to support the silicon wafer, the gas radicals emitted by the emission source are deposited on the silicon wafer, the silicon wafer coating carrier is provided with a sink, the sink has a bottom and a wall, the bottom of the sink is provided with at least one placement area, each placement area is used to place a silicon wafer. A plurality of first stoppers are convexly provided on the groove wall in the direction pointing to the silicon wafer, the plurality of first stoppers are arranged at intervals along the extension direction of the groove wall, and the end of each first stopper facing the placement area can be used to limit the side of the silicon wafer, thereby the position of the silicon wafer in the placement area can be limited by the groove bottom, the groove wall and the first stopper, ensuring that the silicon wafer is well supported by the silicon wafer coating carrier and the edge of the silicon wafer can be away from the groove wall of the sink, and then the gas radicals emitted by the emission source can be evenly deposited on the side of the silicon wafer exposed outside the sink, alleviating the phenomenon of the groove wall of the sink blocking the gas radicals. Among them, the side of the silicon wafer exposed to the outside is the coated side of the silicon wafer, and the side of the silicon wafer in contact with the bottom of the groove is the non-coated side.

[0008] Furthermore, the utility model defines: the thickness dimension of the first limiter along the thickness direction of the silicon wafer coating carrier is h, h>0, and the thickness dimension h of the first limiter is equal to the groove depth of the sink. The length dimension of the first limiter protruding from the groove wall along the direction of the groove wall pointing to the placement area is L, L>0, and the minimum incident angle of the gas radical emitted by the emission source at the edge of the sink is θ'. Wherein, θ=arctan(h / L), θ≤θ'. By making the angle θ corresponding to the thickness h and length L of the first limiter greater than the incident angle θ' of the gas radical emitted by the emission source, it is ensured that the gas radical can bypass the edge of the sink and smoothly reach the surface of the silicon wafer exposed outside the sink (i.e., the coating surface), and the groove wall of the sink is avoided as much as possible to block the gas radical, so as to ensure that the coating surface of the silicon wafer is in relatively uniform contact with the gas radical, thereby improving the uniformity of silicon wafer deposition and film formation.

[0009] Optionally, the bottom of the sink of the silicon wafer coating carrier in the utility model is provided with at least two placement areas, each placement area is used to carry a silicon wafer, thereby increasing the wafer carrying capacity of the silicon wafer coating carrier, which is beneficial to improving the coating efficiency of the silicon wafer and accelerating the production process.

[0010] In addition, a second limiting member is provided between any two adjacent placement areas of the silicon wafer coating carrier. The second limiting member is protruding from the bottom of the groove, and the two ends of the second limiting member respectively point to the two adjacent placement areas. The two ends of the second limiting member can respectively limit the adjacent edges of the two adjacent silicon wafers, thereby ensuring that a certain distance is maintained between the adjacent edges of the two adjacent silicon wafers, which is convenient for the gas group to contact the edge of the silicon wafer, so that the coating is evenly deposited everywhere on the coating surface of the silicon wafer.

[0011] Optionally, a third limiting member is protrudingly provided at the connection between two adjacent groove walls of the sink groove of the silicon wafer coating carrier in the utility model, and a first limiting surface is provided on the side of the third limiting member facing the placement area. The first limiting surface can abut against the corners of the silicon wafer, thereby limiting the corners of the silicon wafer, so that the silicon wafer can be placed at a preset position in the corresponding placement area, ensuring that the silicon wafer is accurately positioned in the sink groove, and then the coating surface of the silicon wafer can be evenly contacted with the gas group.

[0012] Optionally, in some schemes, the placement areas may be provided with 2N+2, where N is a positive integer, and all the placement areas are arranged in a matrix. In this case, at least one fourth position-limiting member may be convexly provided on the bottom of the sink, and a fourth position-limiting member may be provided at the center position of any four adjacent placement areas arranged in a matrix. The fourth position-limiting member is provided with a second position-limiting surface on one side facing any placement area, that is, each fourth position-limiting member is provided with four second position-limiting surfaces, and each second position-limiting surface points to one of the corners of the silicon wafer in the corresponding placement area. Thus, the four adjacent corners of the four adjacent silicon wafers can be limited respectively by the four second position-limiting surfaces on the fourth position-limiting member, so that the four silicon wafers can be placed in the preset positions in the corresponding four placement areas, ensuring that the four adjacent silicon wafers are accurately positioned in the corresponding placement, and then the coating surface of each silicon wafer can be evenly contacted with the gas group to ensure uniform coating.

[0013] Optionally, the silicon wafer coating carrier includes a fixing part, and the third limit part and the fourth limit part are provided with mounting holes, and each mounting hole is correspondingly provided with a fixing part. After the silicon wafer is placed in the placement area of ​​the sink, the fixing part can be set in the corresponding mounting hole, and the silicon wafer is fixed in the placement area of ​​the sink by the fixing part abutting against the coating surface of the silicon wafer, so as to prevent the silicon wafer from falling out of the placement area during the coating process.

[0014] Optionally, the bottom of the groove of the silicon wafer coating carrier in the utility model is provided with a hollow portion, and the hollow portion penetrates the two opposite surfaces of the silicon wafer coating carrier. On the one hand, the provision of the hollow portion can reduce the weight of the silicon wafer coating carrier and reduce the material cost; on the other hand, the hollow portion can expose the non-coated surface of the silicon wafer in the placement area, so as to facilitate heating or cooling of the non-coated surface side of the silicon wafer, so that the silicon wafer can be at the optimal temperature for the coating process, thereby improving the coating deposition quality of the silicon wafer.

[0015] Beneficial effect: The back of the silicon wafer coating carrier is provided with a heating or cooling device, and the non-coated surface of the silicon wafer is exposed by setting a hollow portion.

[0016] Optionally, in the utility model, the first limiter is set to be a long strip, and the thickness dimension h of the first limiter ranges from 0.3mm to 0.5mm. The width dimension of the first limiter along the extension direction of the groove wall is b, and the width dimension b of the first limiter is greater than 0mm and less than 3mm. The first limiter adopts the above-mentioned thickness dimension and width dimension to avoid the first limiter from blocking the edge of the silicon wafer as much as possible, thereby improving the uniformity of the coating.

[0017] Optionally, the silicon wafer coating carrier further includes a hook, and at least one side of the silicon wafer coating carrier is provided with a hanging hole, the hook is installed in the hanging hole, and the hook is used to vertically hang the silicon wafer coating carrier. By providing the hanging hole and the hook, it is convenient to vertically hang the silicon wafer coating carrier, and then the silicon wafer arranged on the silicon wafer coating carrier can abut against the first limiting member located on the opposite side of the hanging hole, and the first limiting member located on the opposite side of the hanging hole plays a role of limiting support for the silicon wafer. At this time, the silicon wafer is in a vertical state, and the gas radicals of the emission source are emitted from one side of the silicon wafer coating carrier to the silicon wafer, which is convenient for the coating process.

[0018] Optionally, the material of the silicon wafer coating carrier in the utility model is stainless steel, hard aluminum or graphite, thereby ensuring that the silicon wafer coating carrier has sufficient mechanical strength and high temperature resistance, and can enable the coating process to proceed smoothly.

[0019] On the other hand, the utility model provides a vacuum coating device, the vacuum coating device comprising:

[0020] A process body, wherein the process body is provided with a process chamber; and

[0021] The silicon wafer coating carrier in any of the above schemes can carry a silicon wafer, and the silicon wafer coating carrier is located in a process chamber. An emission source and a hot wire are provided in the process chamber, and the emission source is located on one side of the silicon wafer coating carrier. The emission source emits gas radicals to the silicon wafer on the silicon wafer coating carrier, and the gas radicals are decomposed under the high temperature and catalytic action of the hot wire and then deposited on the surface of the silicon wafer, thereby obtaining the desired process film on the surface of the silicon wafer.

[0022] By adopting the above-mentioned silicon wafer coating carrier, most of the gas groups can contact the coating surface of the silicon wafer during the coating process, the groove wall of the sedimentation groove basically does not block the gas groups, and it is not easy to form a shadow area that the gas groups cannot reach at the edge of the silicon wafer. The edge of the silicon wafer can also be deposited into a film, and finally the deposition uniformity and consistency of the coating surface of the silicon wafer are better.

[0023] The beneficial effects of the utility model are:

[0024] The utility model provides a silicon wafer coating carrier, which is provided with a sink, the sink having a bottom and a wall, the bottom of the sink being provided with at least one placement area, each placement area being used to place a silicon wafer. A first stopper is protrudingly provided on the wall of the sink in the direction pointing to the silicon wafer, and the first stopper can limit the side of the silicon wafer in the placement area to ensure that the edge of the silicon wafer can leave the wall of the sink for a certain distance. Specifically, it is defined as follows: the thickness dimension of the first stopper along the thickness direction of the silicon wafer coating carrier is h, the length dimension of the first stopper protruding from the wall of the sink in the direction pointing to the placement area is L, θ=arctan(h / L), the minimum incident angle of the gas radical emitted by the emission source at the edge of the sink is θ', by ensuring θ≤θ', the gas radical emitted by the emission source can bypass the edge of the sink and smoothly reach the edge position of the silicon wafer, and the shielding phenomenon of the wall of the sink to the gas radical is minimized, so that the coating surface of the silicon wafer can be uniformly deposited into a film, and the coating quality is better.

[0025] The utility model also provides a vacuum coating device, including a process body and the above-mentioned silicon wafer coating carrier. The process body is provided with a process chamber, and the silicon wafer coating carrier is located in the process chamber, and the silicon wafer coating carrier can carry multiple silicon wafers. By adopting the above-mentioned silicon wafer coating carrier, during the coating process of the silicon wafer, most of the gas groups can contact the coating surface of the silicon wafer, the groove wall of the sinking groove basically does not block the gas groups, and the edge of the silicon wafer is not easy to form a shadow area that the gas groups cannot reach, and the edge of the silicon wafer can also be deposited into a film, and finally the deposition uniformity and consistency of the coating surface of the silicon wafer are better. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a structural schematic diagram of a pallet in the prior art;

[0027] Figure 2 It is a top view of a silicon wafer coating carrier (without silicon wafer installed) in one embodiment of the utility model;

[0028] Figure 3 yes Figure 2 A magnified image of area A;

[0029] Figure 4 yes Figure 2 Sectional view of the middle BB section;

[0030] Figure 5 It is a top view of a silicon wafer coating carrier (after silicon wafers are installed) in one embodiment of the utility model;

[0031] Figure 6 yes Figure 5 Enlarged view of the middle C area;

[0032] Figure 7It is an isometric view of a silicon wafer coating carrier in one embodiment of the utility model;

[0033] Figure 8 yes Figure 7 Enlarged view of area D in the middle;

[0034] Fig. 9 It is a structural schematic diagram of a vacuum coating device in one embodiment of the utility model.

[0035] In the figure:

[0036] 10', silicon wafer; 20', tray; 21', sink;

[0037] 10. Silicon wafer; 20. Fixing part; 30. Hook; 100. Silicon wafer coating carrier; 110. Sink; 1101. Sink bottom; 1111. Placement area; 1102. Sink wall; 111. First limiter; 112. Second limiter; 113. Third limiter; 1131. First limiter surface; 1132. Mounting hole; 114. Fourth limiter; 1141. Second limiter surface; 120. Hollow part; 130. Lifting hole; 200. Process body; 210. Process chamber. DETAILED DESCRIPTION

[0038] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only the parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0039] In the description of the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", and "fixed" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] In the present utility model, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0041] In the description of this embodiment, the terms "upper", "lower", "left", "right" and other directions or positional relationships are based on the directions or positional relationships shown in the drawings, and are only for the convenience of description and simplified operation, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation of the present invention. In addition, the terms "first" and "second" are only used to distinguish in the description and have no special meaning.

[0042] like Figure 1 As shown, during the coating process, a tray 20' is usually used to carry the silicon wafer 10', and then the tray 20' is placed in the atmosphere of the process gas for coating reaction. The tray 20' is generally provided with a sink 21' to place the silicon wafer 10'. However, during the coating process, since most gas groups move in a linear manner, the wall of the sink 21' will block the gas groups, resulting in the formation of a shadow area at the edge of the silicon wafer 10' where the gas groups cannot reach, which is not conducive to the deposition of the film at the edge of the silicon wafer 10'. Finally, the deposited film on the surface of the silicon wafer 10' is thick in the middle and thin around the edges, and the uniformity is poor.

[0043] To this end, the present embodiment provides a silicon wafer coating carrier 100, which is applied to a vacuum coating device. The vacuum coating device has an emission source. The silicon wafer coating carrier 100 is used to support the silicon wafer, and the gas radicals emitted by the emission source are deposited on the silicon wafer. The silicon wafer coating carrier 100 can support and limit the edge of the silicon wafer 10, so that the edge of the silicon wafer 10 is away from the groove wall 1102 of the sink 110 for a distance, thereby alleviating the shielding phenomenon of the groove wall 1102 of the sink 110 on the gas radicals, and the gas radicals emitted by the emission source can be deposited more evenly at the edge and middle position of the silicon wafer 10, and the coating quality is better.

[0044] Specifically, Figure 2-Figure 4As shown, the silicon wafer coating carrier 100 is provided with a sink 110 , and the sink 110 has a bottom 1101 and a wall 1102 . The bottom 1101 is provided with at least one placement area 1111 , and each placement area 1111 is used to place a silicon wafer 10 . A plurality of first stoppers 111 are protrudingly provided on the groove wall 1102 in the direction pointing to the silicon wafer 10. The plurality of first stoppers 111 are arranged at intervals along the extension direction of the groove wall 1102. The end of each first stopper 111 facing the placement area 1111 can be used to stop the side of the silicon wafer 10. Thus, the position of the silicon wafer 10 in the placement area 1111 can be stopped by the groove bottom 1101, the groove wall 1102 and the first stoppers 111, ensuring that the silicon wafer 10 is well supported by the silicon wafer coating carrier 100 and the edge of the silicon wafer 10 can be away from the groove wall 1102 of the sink 110 for a certain distance. Then, the gas radicals emitted by the emission source can be uniformly deposited on the side of the silicon wafer 10 exposed outside the sink 110, alleviating the shielding phenomenon of the gas radicals by the groove wall 1102 of the sink 110. Among them, the side exposed outside is the coating surface of the silicon wafer 10, and the side of the groove bottom 1101 in contact with the silicon wafer 10 is the non-coating surface.

[0045] It should be noted that at least one placement area 1111 is set on the bottom 1101 of the groove. For example, the bottom 1101 of the groove can only have one placement area 1111 for carrying a silicon wafer 10; the bottom 1101 of the groove can also have two placement areas 1111 for carrying two silicon wafers 10, and a second limiting member 112 can be set between adjacent placement areas 1111 to limit the silicon wafer 10; similarly, the bottom 1101 of the groove can also have three placement areas 1111, or four placement areas 1111, etc. The number of placement areas 1111 set on the bottom 1101 of the groove can be determined according to actual needs.

[0046] Further, see Figure 4In this embodiment, it is defined that: the thickness dimension of the first stopper 111 along the thickness direction of the silicon wafer coating carrier 100 is h, and the length dimension of the first stopper 111 protruding from the groove wall 1102 along the direction of the groove wall 1102 pointing to the placement area 1111 is L, h and L are both greater than 0, and the thickness dimension h of the first stopper 111 is equal to the groove depth of the sink 110. The angle corresponding to the thickness h and the length L of the first stopper 111 is θ, θ=arctan(h / L). Assume that the minimum incident angle of the gas radical emitted by the emission source at the edge of the sink 110 is θ', θ'>0°. When θ≤θ', the gas radicals emitted by the emission source have a minimum incident angle θ' at the edge of the sinking groove 110, and the gas radicals can bypass the edge of the sinking groove 110 and smoothly reach the surface of the silicon wafer 10 exposed outside the sinking groove 110 (i.e., the coating surface), thereby basically avoiding the trough wall 1102 of the sinking groove 110 from blocking the gas radicals, and the edge of the silicon wafer 10 can also smoothly contact the gas radicals, thereby ensuring that the film deposition in the middle and edge positions of the coating surface of the silicon wafer 10 is relatively uniform, which is beneficial to improving the uniformity of the deposition of the film on the silicon wafer 10.

[0047] Optionally, the first stopper 111 can be set to be a long strip, with its length direction set in the direction pointing to the silicon wafer 10, one side where the width is located is connected to the groove wall 1102 of the sink 110, and the other side where the width is located is used to abut against the side of the silicon wafer 10, thereby minimizing the contact area between the first stopper 111 and the silicon wafer 10, alleviating the first stopper 111 from blocking the edge of the silicon wafer 10, thereby reducing the area of ​​the area that the gas group cannot reach to the total area of ​​the coating surface of the silicon wafer 10 (less than 0.1%, almost negligible), and improving the uniformity of the coating of the silicon wafer 10. Exemplarily, the value range of the thickness dimension h of the first stopper 111 is 0.3mm-0.5mm. For example, the thickness dimension h of the first stopper 111 can be set to 0.3mm, 0.4mm, 0.5mm, etc., which are not listed here one by one. The width dimension of the first stopper 111 along the extension direction of the groove wall 1102 is b, and the width dimension b of the first stopper 111 is greater than 0 mm and less than 3 mm. For example, the width dimension b of the first stopper 111 can be set to 2 mm, 2.3 mm, 2.5 mm, 2.9 mm, etc., which are not listed here one by one. The first stopper 111 adopts the above-mentioned thickness dimension and width dimension to avoid the first stopper 111 from blocking the edge of the silicon wafer 10 as much as possible, thereby improving the uniformity of the coating.

[0048] In some embodiments, if θ' is 30° and h is 0.3 mm, L is greater than 0.52 mm. For example, L can be 0.6 mm, 0.7 mm, 0.8 mm, 1 mm, etc.

[0049] In some embodiments, if θ' is 45° and h is 0.4 mm, L is greater than 0.4 mm. For example, L may be 0.5 mm, 0.6 mm, 0.7 mm, 1 mm, etc.

[0050] In some embodiments, if θ' is 60° and h is 0.5 mm, L is greater than 0.29 mm. For example, L can be 0.3 mm, 0.4 mm, 0.5 mm, 1 mm, etc.

[0051] It should be noted that the minimum incident angle θ′ of the gas radicals emitted by the emission source at the edge of the sink 110 can be changed by adjusting the direction of the emission source of the vacuum coating equipment.

[0052] Continue to see Figure 2 and Figure 3 In this embodiment, the bottom 1101 of the sink 110 of the silicon wafer coating carrier 100 is provided with at least two placement areas 1111, and each placement area 1111 is used to carry one silicon wafer 10. For example, the bottom 1101 of the sink 110 can be provided with two placement areas 1111, four placement areas 1111, six placement areas 1111, and so on. Each placement area 1111 can be used to carry one silicon wafer 10, thereby greatly improving the wafer carrying capacity of the silicon wafer coating carrier 100, so that when performing a coating process, multiple silicon wafers 10 can be processed at the same time, which is conducive to improving the coating efficiency of the silicon wafer 10 and speeding up the production process.

[0053] In order to make the two silicon wafers 10 in two adjacent placement areas 1111 spaced apart by a certain distance and avoid mutual shielding between the adjacent silicon wafers 10, which would result in the inability of gas radicals to deposit, a second stopper 112 is provided between any two adjacent placement areas 1111 of the silicon wafer coating carrier 100 in this embodiment. The second stopper 112 is protruding from the groove bottom 1101, and the two ends of the second stopper 112 point to the two adjacent placement areas 1111, respectively. Figure 5 and Figure 6 The two ends of the second limiting member 112 can respectively limit the adjacent edges of two adjacent silicon wafers 10, thereby ensuring that the adjacent edges of the two adjacent silicon wafers 10 are spaced a certain distance apart, making it easier for the gas groups to contact the edges of the silicon wafers 10, so that the coating is evenly deposited everywhere on the coating surface of the silicon wafer 10.

[0054] Optionally, the second limiting member 112 in the present embodiment can also be set to be in the shape of a long strip, which is opposite to the first limiting member 111. The length direction of the second limiting member 112 is also set in the direction pointing to the silicon wafer 10, and the two side edges where the width is located can respectively abut against the side edges of a silicon wafer 10. Thus, the first limiting member 111 and the second limiting member 112 cooperate to limit the two relative side edges of the same silicon wafer 10, thereby ensuring that the silicon wafer 10 is accurately positioned in the placement area 1111, and avoiding the blocking of the edge of the silicon wafer 10 by the groove wall 1102 as much as possible, which helps to make the film deposition at various positions on the coating surface of the silicon wafer 10 more uniform.

[0055] Continue to see Figure 3 In this embodiment, a third stopper 113 is convexly provided at the connection of two adjacent groove walls 1102 of the sink 110 of the silicon wafer coating carrier 100. The third stopper 113 is provided with a first stopper surface 1131 on the side facing the placement area 1111. The first stopper surface 1131 can abut against the corner of the silicon wafer 10, thereby limiting the corner of the silicon wafer 10, so that the silicon wafer 10 can be placed at a preset position in the corresponding placement area 1111, ensuring that the silicon wafer 10 is accurately positioned in the sink 110, and then the coating surface of the silicon wafer 10 can be uniformly contacted with the gas radical. Exemplarily, the third stopper 113 can be set to a square shape, and the first stopper surface 1131 is provided on the corner of the side facing the silicon wafer 10. The first limiting surface 1131 can be an inclined plane or a curved surface, which can limit the corners of the silicon wafer 10, thereby further ensuring the accurate positioning of the silicon wafer 10. In addition, the first limiting surface 1131 is in point contact with the corners of the silicon wafer 10, and the contact area is very small, and the influence on the coating can be ignored.

[0056] Further, in some embodiments, in order to further increase the wafer loading capacity of the silicon wafer coating carrier 100, the placement areas 1111 may be provided with 2N+2, N is a positive integer, N may be 1, 2, 3, 4, 5, 6, etc., then the number of the placement areas 1111 may be 4, 6, 8, 10, 12, 14, etc. All the placement areas 1111 are arranged in a matrix. At this time, the bottom 1101 of the sink 110 may be provided with at least one fourth position-limiting member 114, and a fourth position-limiting member 114 is provided at the center position of any of the four adjacent placement areas 1111 arranged in a matrix. The fourth position-limiting member 114 is provided with a second position-limiting surface 1141 on one side facing any placement area 1111, that is, each fourth position-limiting member 114 is provided with four second position-limiting surfaces 1141, and each second position-limiting surface 1141 points to one of the corners of the silicon wafer 10 in the corresponding placement area 1111. Therefore, the four second limiting surfaces 1141 on the fourth limiting member 114 can respectively limit the four adjacent corners of the four adjacent silicon wafers 10, so that the four silicon wafers 10 can be placed at the preset positions in the corresponding four placement areas 1111, ensuring that the four adjacent silicon wafers 10 are accurately positioned in the corresponding placement, and then the coating surface of each silicon wafer 10 can be evenly contacted with the gas group to ensure uniform coating.

[0057] Exemplarily, the fourth limiting member 114 in the present embodiment can be set to a square shape, and a second limiting surface 1141 is respectively provided at its four corners, and each second limiting surface 1141 points to a silicon wafer 10 and is used to limit the corner of a silicon wafer 10. In other words, the fourth limiting member 114 can simultaneously limit the four adjacent corners of the four silicon wafers 10 arranged circumferentially, so as to ensure that the position of the silicon wafer 10 in the placement area 1111 is accurate. Furthermore, the second limiting surface 1141 can be an inclined plane or an arc surface, and the inclined plane or arc surface is in point contact with the corners of the silicon wafer 10, and its contact area is very small, so as to avoid the fourth limiting member 114 blocking the corners of the silicon wafer 10 as much as possible, which helps to improve the uniformity of the deposition of the film at the four corners on the coating surface of the silicon wafer 10.

[0058] Optionally, a guide surface may be provided on the side of the groove wall 1102 of the sink 110 close to the silicon wafer 10 being loaded into the sink 110. The guide surface may be provided as an inclined surface inclined relative to the groove wall 1102, and the inclined surface is inclined in a direction away from the placement area 1111. The provision of the guide surface may play a certain guiding role when the silicon wafer 10 is loaded into the sink 110, and facilitates the silicon wafer 10 to be loaded into the placement area 1111 of the sink 110. Of course, in some embodiments, the guide surface may be a curved surface.

[0059] See also Figure 5-Figure 8In this embodiment, the silicon wafer coating carrier 100 includes a plurality of fixing members 20. The third limiting member 113 and the fourth limiting member 114 are provided with mounting holes 1132, and each mounting hole 1132 is provided with a fixing member 20. After the silicon wafer 10 is placed in the placement area 1111 of the sink 110, the fixing member 20 can be set in the corresponding mounting hole 1132, and the silicon wafer 10 is fixed in the placement area 1111 of the sink 110 by the fixing member 20 abutting against the coating surface of the silicon wafer 10, so as to prevent the silicon wafer 10 from falling out of the placement area 1111 during the coating process. Optionally, the fixing member 20 can be selected as a card point, one side of the card point can be detachably inserted into the mounting hole 1132, and the other side of the card point can be used to fix the silicon wafer 10 to prevent the silicon wafer 10 from falling out of the placement area 1111.

[0060] Optionally, in this embodiment, the bottom 1101 of the groove of the silicon wafer coating carrier 100 is provided with a hollow portion 120, and the hollow portion 120 penetrates through the two opposite surfaces of the silicon wafer coating carrier 100, and each placement area 1111 corresponds to a hollow portion 120. On the one hand, the provision of the hollow portion 120 can reduce the weight of the silicon wafer coating carrier 100 and reduce the material cost; on the other hand, the hollow portion 120 can expose the non-coated surface of the silicon wafer 10 in the placement area 1111, so as to facilitate the provision of a heating component or a cooling component on the back of the silicon wafer coating carrier 100, and the non-coated surface side of the silicon wafer 10 is heated or cooled by the heating component or the cooling component, so that the silicon wafer 10 can be at the optimal temperature for the coating process, thereby improving the coating deposition quality of the silicon wafer 10.

[0061] Furthermore, the silicon wafer coating carrier 100 further includes a hook 30, and at least one side of the silicon wafer coating carrier 100 is provided with a hanging hole 130, and the hook 30 is installed in the hanging hole 130. When the coating process is performed, the silicon wafer coating carrier 100 can be vertically suspended by the hook 30, and at this time, the silicon wafer 10 set on the silicon wafer coating carrier 100 will fall to the side away from the hanging hole 130 due to gravity until it abuts against the first stopper 111 located on the opposite side of the hanging hole 130, and the first stopper 111 located on the opposite side of the hanging hole 130 plays a role of limiting support for the silicon wafer 10, and at this time, the position of the silicon wafer 10 is fixed and in a vertical state, and the gas radicals of the emission source are emitted from one side of the silicon wafer coating carrier 100 to the silicon wafer 10, which is convenient for the coating process.

[0062] Optionally, in order to ensure that the silicon wafer coating carrier 100 has sufficient mechanical strength and high temperature resistance, the material of the silicon wafer coating carrier 100 in this embodiment can be stainless steel, hard aluminum or graphite. This ensures that the coating process proceeds smoothly. Of course, in other embodiments, the silicon wafer coating carrier 100 can also be made of other materials with high mechanical strength and high temperature resistance.

[0063] This embodiment also provides a vacuum coating device, see Fig. 9 The vacuum coating equipment includes a process body 200 and the above-mentioned silicon wafer coating carrier 100. The process body 200 is provided with a process chamber 210, and the silicon wafer coating carrier 100 is located in the process chamber 210. The silicon wafer coating carrier 100 can carry multiple silicon wafers 10. An emission source and a hot wire are arranged in the process chamber 210. The emission source is located on one side of the silicon wafer coating carrier 100. The emission source is used to emit gas radicals to the coating surface of the silicon wafer 10 on the silicon wafer coating carrier 100, and the hot wire is used to catalyze the gas radicals at high temperature to chemically react with the silicon wafer 10. Specifically, the gas radicals are cracked under the high temperature and catalytic action of the hot wire and then deposited on the surface of the silicon wafer 10, thereby depositing a film on the coating surface of the silicon wafer 10, and the desired process film is obtained on the coating surface of the silicon wafer 10. By adopting the above-mentioned silicon wafer coating carrier 100, during the coating process of the silicon wafer 10, most of the gas groups can contact the coating surface of the silicon wafer 10, the groove wall 1102 of the sedimentation groove 110 basically does not block the gas groups, and it is not easy to form a shadow area that the gas groups cannot reach at the edge of the silicon wafer 10. The edge of the silicon wafer 10 can also be deposited into a film, and finally the deposition uniformity and consistency of the coating surface of the silicon wafer 10 are better.

[0064] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the implementation methods of the present invention. For those skilled in the art, various obvious changes, readjustments and substitutions can be made without departing from the scope of protection of the present invention. It is not necessary and impossible to list all implementation methods here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention shall be included in the scope of protection of the claims of the present invention.

Claims

1. A silicon wafer coating carrier, applied to a vacuum coating device, wherein the vacuum coating device has an emission source, the silicon wafer coating carrier (100) is used to support a silicon wafer (10), and the gas radicals emitted by the emission source are deposited on the silicon wafer (10), characterized in that: The silicon wafer coating carrier (100) is provided with a sink (110), the sink (110) having a sink bottom (1101) and a sink wall (1102), the sink bottom (1101) being provided with at least one placement area (1111), the placement area (1111) being used to place the silicon wafer (10), the sink wall (1102) being provided with a plurality of first limiting members (111) protrudingly, the plurality of first limiting members (111) being arranged at intervals, and the end of the first limiting member (111) facing the placement area (1111) being used to limit the side edge of the silicon wafer (10); Definition: The thickness dimension of the first limiter (111) along the thickness direction of the silicon wafer coating carrier (100) is h, the length dimension of the first limiter (111) protruding from the groove wall (1102) along the direction from the groove wall (1102) to the placement area (1111) is L, and the minimum incident angle of the gas radical emitted by the emission source at the edge of the sink groove (110) is θ', wherein θ=arctan(h / L), θ≤θ'.

2. The silicon wafer coating carrier according to claim 1, characterized in that: The groove bottom (1101) is provided with at least two placement areas (1111), each of the placement areas (1111) is used to carry one of the silicon wafers (10), and a second limiting member (112) is provided between any two adjacent placement areas (1111), the second limiting member (112) is protruding from the groove bottom (1101), and the two ends of the second limiting member (112) are respectively used to limit the edges of the two adjacent silicon wafers (10).

3. The silicon wafer coating carrier according to claim 2, characterized in that: A third limiting member (113) is protrudingly provided at the connection point between two adjacent groove walls (1102), and a first limiting surface (1131) is provided on the side of the third limiting member (113) facing the placement area (1111), and the first limiting surface (1131) is used to limit the corners of the silicon wafer (10).

4. The silicon wafer coating carrier according to claim 3, characterized in that: The placement areas (1111) are provided with 2N+2, N being a positive integer, and all the placement areas (1111) are arranged in a matrix. The groove bottom (1101) is provided with at least one fourth limiting member (114) protrudingly, and the center position of any four adjacent placement areas (1111) arranged in a matrix is ​​provided with a fourth limiting member (114), and the fourth limiting member (114) is provided with a second limiting surface (1141) on one side facing any one of the placement areas (1111), and the second limiting surface (1141) is used to limit the corners of the silicon wafer (10).

5. The silicon wafer coating carrier according to claim 4, characterized in that: The silicon wafer coating carrier (100) comprises a fixing member (20), the third limiting member (113) and the fourth limiting member (114) are both provided with mounting holes (1132), the fixing member (20) is arranged in the mounting hole (1132), and the fixing member (20) is used to abut against the coating surface of the silicon wafer (10) to prevent the silicon wafer (10) from falling out of the placement area (1111).

6. The silicon wafer coating carrier according to claim 1, characterized in that: The groove bottom (1101) is provided with a hollow portion (120), the hollow portion (120) penetrates two opposite surfaces of the silicon wafer coating carrier (100), and the hollow portion (120) is used to expose the non-coated surface of the silicon wafer (10) in the placement area (1111).

7. The silicon wafer coating carrier according to claim 1, characterized in that: The thickness dimension h of the first limiting member (111) has a value range of 0.3 mm to 0.5 mm; And / or, the width dimension b of the first limiting member (111) along the extension direction of the groove wall (1102) is greater than 0 mm and less than 3 mm.

8. The silicon wafer coating carrier according to claim 1, characterized in that: The silicon wafer coating carrier (100) further comprises a hook (30); at least one side of the silicon wafer coating carrier (100) is provided with a hanging hole (130); the hook (30) is installed in the hanging hole (130); and the hook (30) is used to vertically hang the silicon wafer coating carrier (100).

9. The silicon wafer coating carrier according to claim 1, characterized in that: The material of the silicon wafer coating carrier (100) is stainless steel, hard aluminum or graphite.

10. A vacuum coating device, characterized in that: The vacuum coating equipment comprises: A process body (200), wherein the process body (200) is provided with a process chamber (210); and The silicon wafer coating carrier (100) according to any one of claims 1 to 9, wherein the silicon wafer coating carrier (100) carries a silicon wafer (10), and the silicon wafer coating carrier (100) is located in the process chamber (210).

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