Identification circuit and radio frequency chip for clock line and data line of MIPI (Mobile Industry Processor Interface)

Abstract

The utility model relates to the technical field of radio frequency, and discloses an identification circuit for a clock line and a data line of an MIPI (Mobile Industry Processor Interface) and a radio frequency chip, the circuit comprises an output switching unit, a detection unit and a decoding unit, in actual use, the circuit detects SSC signals through the detection unit and outputs selection signals to control the connection relation between the data input end and the clock input end and between the data output end and the clock output end, so that correct output of clocks and data is achieved, in addition, the selection signals are input into the decoding unit, and the decoding efficiency is improved. The decoding unit sets the ID information of the decoding unit through the selection signal, so that the function of changing the ID information of the slave device by detecting the SSC signal is realized, and compared with the prior art, the device only detects the SSC signal, adopts single acquisition processing, and occupies a small chip area.

Description

Technical Field

[0001] The utility model relates to the technical field of radio frequency, and in particular to an identification circuit and a radio frequency chip for a clock line and a data line of a MIPI interface. Background Art

[0002] In the field of radio frequency, the MIPI protocol is often used to achieve communication between master and slave devices. The schematic diagram of an existing MIPI RFFE system is as follows: Figure 1 As shown, in Figure 1 In the embodiment, a master device (RFIC#1) can mount fifteen slave devices, namely slave device (FEM#1) to slave device (FEM#15). The slave devices communicate with the master device through the RFFE bus. Each slave device coupled to the RFFE bus can be identified by an identification signal such as USID (Unique Slave ID, slave device identifier), PID (PRODUCTID, product identifier) ​​or MID (MANUFACTURER_ID, manufacturer identifier).

[0003] The RFFE bus uses two signal lines for communication, as shown in the schematic diagram. Figure 2 As shown in the figure, the two signal lines are the clock signal line (SCLK) and the data line (SDATA). Figure 2 In the data line, each frame of data starts with an SSC (Sequence Start Condition) signal, and the clock line does not transmit a clock signal at this time. After the SSC signal, the command frame is transmitted immediately. The first 4 bits of the command frame are SA signals, which are used to match the identification information of the slave device. If a slave device matches the SA signal, it knows that the command frame is an operation initiated by the master device for itself.

[0004] In actual use, when the USID, PID, and MID of two slave devices are the same, the MIPI RFFE master device cannot distinguish between the two slave devices. Figure 1Taking the two MIPI RFFE slave devices (slave device #1 and slave device #2) shown as an example, when the identity information of the two devices is exactly the same, the SCLK of slave device #1 is first connected to the SCLK of the master device, the SDATA is connected to the SDATA of the master device, and the SCLK of slave device #2 is connected to the SDATA of the master device, and the SDATA is connected to the SCLK of the master device; then each slave device detects the SSC signal in the received signal to sense whether its own SCLK and SDATA are interchanged, and then reprograms its own identity feature information to distinguish two identical MIPI RFFE slave devices in the MIPI RFFE system.

[0005] Most existing slave devices use Figure 3 The circuit shown detects the SSC signal in the received signal, where Figure 3 The circuit shown includes two parallel first acquisition circuits and second acquisition circuits. The first acquisition circuit and the second acquisition circuit process the signals on the clock line and the data line in parallel to determine whether the clock line and the data line are interchanged. However, this method of setting two acquisition circuits for parallel detection has the disadvantages of large circuit area and low cost performance. Utility Model Content

[0006] In view of the shortcomings of the background technology, the utility model provides an identification circuit and a radio frequency chip for the clock line and data line of the MIPI interface. The technical problem to be solved is that in the MIPI system, when the ID information of two slave devices is the same, the circuit for detecting the SSC signal has a large area defect.

[0007] In order to solve the above technical problems, the utility model provides the following technical solutions: a recognition circuit for a clock line and a data line of a MIPI interface, comprising an output switching unit, a detection unit and a decoding unit, wherein the output switching unit comprises a clock input terminal, a data input terminal, a clock output terminal and a data output terminal; the detection unit is electrically connected to the clock input terminal and the data input terminal, and is used to detect SSC signals in the clock input terminal and the data input terminal, and input selection signals to the output switching unit and the decoding unit respectively;

[0008] The output switching unit controls the clock input terminal and the data input terminal, one end of which the clock signal is input, to be electrically connected to the clock output terminal, and controls the clock input terminal and the data input terminal, one end of which the data signal is input, to be electrically connected to the data output terminal in response to the selection signal;

[0009] The decoding unit is electrically connected to the clock output terminal and the data output terminal, and sets its own ID information in response to the selection signal.

[0010] In a certain embodiment, the output switching unit includes a first switch unit, a second switch unit, a third switch unit and a fourth switch unit;

[0011] The clock input end is electrically connected to the input end of the first switch unit and the input end of the third switch unit respectively, and the data input end is electrically connected to the input end of the second switch unit and the fourth switch unit respectively;

[0012] The output end of the first switch unit and the output end of the second switch unit are electrically connected to the clock output end, and the output end of the third switch unit and the output end of the fourth switch unit are electrically connected to the data output end;

[0013] The selection signal is input to the control terminals of the first to fourth switch units to control the on and off of the first to fourth switch units.

[0014] In a certain embodiment, the detection unit outputs a first selection signal and a second selection signal, the first selection signal and the second selection signal are two opposite signals, the first selection signal is input to the control end of the first switch unit and the control end of the fourth switch unit, and the second selection signal is input to the control end of the second switch unit and the control end of the third switch unit.

[0015] In some implementation manner, the first switch unit and the fourth switch unit are turned on when the first selection signal is at a high level, and are turned off when the first selection signal is at a low level;

[0016] The second switch unit and the third switch unit are turned on when the second selection signal is at a high level, and are turned off when the second selection signal is at a low level.

[0017] In some implementations, the detection unit includes a D flip-flop D1, a D flip-flop D2, a D flip-flop D3, a D flip-flop D4, an AND gate AND1, an AND gate AND2, a NOR gate NOR1, and a NOR gate NOR2;

[0018] The D input terminal of the D flip-flop D1 and the D input terminal of the D flip-flop D2 are used to input the power supply VIO, the clock input terminal is electrically connected to the clock terminal of the D flip-flop D1, the data input terminal is electrically connected to the clock terminal of the D flip-flop D2, the Q output terminal of the D flip-flop D1 is electrically connected to the clock terminal of the D flip-flop D3, and the Q output terminal of the D flip-flop D2 is electrically connected to the clock terminal of the D flip-flop D4;

[0019] The Q output terminal of the D flip-flop D3 is electrically connected to the first input terminal of the AND gate AND1 and the first input terminal of the NOR gate NOR2 respectively, and the Q output terminal of the D flip-flop D4 is electrically connected to the first input terminal of the AND gate AND2 and the first input terminal of the NOR gate NOR1 respectively;

[0020] The Q non-output terminal of the D flip-flop D3 is electrically connected to the second input terminal of the AND gate AND2, the output terminal of the AND gate AND2 is electrically connected to the second input terminal of the NOR gate NOR1 for outputting the first selection signal, and the output terminal of the NOR gate NOR1 is electrically connected to the D input terminal of the D flip-flop D3;

[0021] The Q non-output terminal of the D flip-flop D4 is electrically connected to the second input terminal of the AND gate AND1, the output terminal of the AND gate AND1 is electrically connected to the second input terminal of the NOR gate NOR2 for outputting the second selection signal, and the output terminal of the NOR gate NOR2 is electrically connected to the Q input terminal of the D flip-flop D4;

[0022] The reset terminal of the D flip-flop D1 is electrically connected to the reset terminals of the D flip-flop D2 , the D flip-flop D3 , and the D flip-flop D4 , respectively.

[0023] In some implementation manner, the clock input terminal is electrically connected to the input terminal of the first switch unit and the input terminal of the third switch unit through an input buffer Q1.

[0024] In some implementations, the data input terminal is electrically connected to the input terminal of the second switch unit and the input terminal of the fourth switch unit through an input buffer Q2.

[0025] In a certain embodiment, the data read output end of the decoding unit is electrically connected to the input end of the output buffer Q3 and the input end of the output buffer Q4 respectively, the output end of the output buffer Q3 is electrically connected to the clock input end, and the output end of the output buffer Q4 is electrically connected to the data input end.

[0026] In a certain embodiment, the utility model also includes an OR gate OR1 and an OR gate OR2, the first input end of the OR gate OR1 is used to input a first selection signal, the first input end of the OR gate OR2 is used to input a second selection signal, the second input end of the OR gate OR1 and the second input end of the OR gate OR2 are electrically connected to the decoding unit for receiving a data read enable signal, the output end of the OR gate OR1 is electrically connected to the control end of the output buffer Q3, and the output end of the OR gate OR2 is electrically connected to the control end of the output buffer Q4.

[0027] In addition, the utility model also provides a radio frequency chip, on which the above-mentioned identification circuit for the clock line and the data line of the MIPI interface is provided.

[0028] Compared with the prior art, the utility model has the following beneficial effects: when it is necessary to detect which input terminal of the clock input terminal and the data input terminal inputs the data signal, the utility model detects the SSC signal through the detection unit, and outputs a selection signal to control the connection relationship between the data input terminal and the clock input terminal and the data output terminal and the clock output terminal, so as to achieve the correct output of the clock and data. In addition, the selection signal is input to the decoding unit, and the decoding unit sets its own ID information through the selection signal, so as to achieve the function of changing the ID information of the slave device by detecting the SSC signal. Compared with the prior art, since it only detects the SSC signal, it is a single acquisition process and occupies a small chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A structural diagram of an existing MIPI RFFE system;

[0030] Figure 2 is a schematic diagram of the RFFE bus;

[0031] Figure 3 The present invention is a circuit diagram for detecting SSC signals;

[0032] Figure 4 It is a schematic diagram of the structure of the circuit of the utility model;

[0033] Figure 5 A schematic diagram of another structure of the circuit of the utility model;

[0034] Figure 6 The utility model is a circuit diagram of a detection unit of the circuit. DETAILED DESCRIPTION

[0035] Now the utility model is further described in detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the utility model in a schematic manner, and therefore only show the components related to the utility model.

[0036] Embodiment 1

[0037] like Figure 4 As shown, a recognition circuit for a clock line and a data line of a MIPI interface includes an output switching unit 1, a detection unit 2 and a decoding unit 3, wherein the output switching unit 1 includes a clock input terminal SCLK, a data input terminal SDATA, a clock output terminal SCLK_OUT and a data output terminal SDATA_OUT; the detection unit 2 is electrically connected to the clock input terminal SCLK and the data input terminal SDATA, and is used to detect SSC signals in the clock input terminal SCLK and the data input terminal SDATA, and input selection signals to the output switching unit 1 and the decoding unit 3 respectively;

[0038] The output switching unit 1 controls the clock input terminal SCLK and the data input terminal SDATA to electrically connect one end of the clock signal input to the clock output terminal SCLK_OUT, and controls the clock input terminal SCLK and the data input terminal SDATA to electrically connect one end of the data signal input to the data output terminal SDATA_OUT in response to the selection signal;

[0039] The decoding unit 3 is electrically connected to the clock output terminal SCLK_OUT and the data output terminal SDATA_OUT, and sets its own ID information in response to the selection signal.

[0040] In actual use, the utility model detects the rising edge of the SSC signal through the detection unit 1, and outputs a selection signal to control the connection relationship between the data input terminal SDATA and the clock input terminal SCLK and the data output terminal SDATA_OUT and the clock output terminal SCLK_OUT, so as to achieve the correct output of the clock and data. In addition, the selection signal is input to the decoding unit 3, and the decoding unit 3 sets its own ID information through the selection signal, so as to realize the function of changing the ID information of the slave device by detecting the SSC signal. Compared with the prior art, since it only detects the SSC signal, it is a single acquisition process and occupies a small chip area.

[0041] See also Figure 5 In this embodiment, the output switching unit 1 includes a first switch unit 11, a second switch unit 12, a third switch unit 13 and a fourth switch unit 14;

[0042] The clock input terminal SCLK is electrically connected to the input terminal of the first switch unit 11 and the input terminal of the third switch unit 13, respectively, and the data input terminal SDATA is electrically connected to the input terminal of the second switch unit 12 and the input terminal of the fourth switch unit 14, respectively;

[0043] The output end of the first switch unit 11 and the output end of the second switch unit 12 are electrically connected to the clock output end SCLK_OUT, and the output end of the third switch unit 13 and the output end of the fourth switch unit 14 are electrically connected to the data output end SDATA_OUT;

[0044] The selection signal is input to the control end of the first to fourth switch units 14 to control the on and off of the first to fourth switch units.

[0045] Specifically, in this embodiment, the selection signal output by the detection unit 2 includes a first selection signal SEL and a second selection signal SELB, the first selection signal SEL and the second selection signal SELB are two opposite signals, the first selection signal SEL is input to the control end of the first switch unit 11 and the control end of the fourth switch unit 14, and the second selection signal SELB is input to the control end of the second switch unit 12 and the control end of the third switch unit 13.

[0046] For the first to fourth switch units 14, the first switch unit 11 and the fourth switch unit 14 are turned on when the first selection signal SEL is at a high level, and are turned off when it is at a low level;

[0047] The second switch unit 12 and the third switch unit 13 are turned on when the second selection signal SELB is at a high level, and are turned off when it is at a low level.

[0048] In actual use, the first to fourth switch units 14 can select corresponding electronic switches according to actual needs.

[0049] In addition, Figure 5 In the embodiment, the clock input terminal SCLK is electrically connected to the input terminal of the first switch unit 11 and the input terminal of the third switch unit 13 through the input buffer Q1;

[0050] The data input terminal SDATA is electrically connected to the input terminal of the second switch unit 12 and the input terminal of the fourth switch unit 14 through the input buffer Q2.

[0051] In addition, Figure 5 In the embodiment, the data read output terminal SDATA_READ_OUT of the decoding unit 3 is electrically connected to the input terminal of the output buffer Q3 and the input terminal of the output buffer Q4 respectively, the output terminal of the output buffer Q3 is electrically connected to the clock input terminal SCLK, and the output terminal of the output buffer Q4 is electrically connected to the data input terminal SDATA.

[0052] exist Figure 5 In the utility model, the present invention also includes an OR gate OR1 and an OR gate OR2, the first input end of the OR gate OR1 is used to input the first selection signal SEL, the first input end of the OR gate OR2 is used to input the second selection signal SELB, the second input end of the OR gate OR1 and the second input end of the OR gate OR2 are electrically connected to the decoding unit 3, for receiving the data read enable signal SDATA_READ_OK, the output end of the OR gate OR1 is electrically connected to the control end of the output buffer Q3, and the output end of the OR gate OR2 is electrically connected to the control end of the output buffer Q4.

[0053] for Figure 5 In the circuit shown, when the first selection signal SEL and the second selection signal SELB are high and low level signals respectively, the clock input terminal SCLK is connected to the clock output terminal SCLK_OUT, and the data input terminal SDATA is connected to the data output terminal SDATA_OUT; when the first selection signal SEL and the second selection signal SELB are low and high level signals respectively, the clock input terminal SCLK is connected to the data output terminal SDATA_OUT, and the data input terminal SDATA is connected to the clock output terminal SCLK_OUT.

[0054] when Figure 5 When the circuit shown performs a write operation, the data read enable signal SDATA_READ_OK is in a low level state. When a read operation command is performed, the data read enable signal SDATA_READ_OK is in a high level state. At this time, the high level data read enable signal SDATA_READ_OK is input to the OR gate OR1 and the OR gate OR2 to perform an OR operation with the first selection signal SEL and the second selection signal SELB, thereby controlling the output buffer Q3 and the output buffer Q4 to output information to the outside.

[0055] Reference Figure 6 In this embodiment, the detection unit 2 includes a D flip-flop D1, a D flip-flop D2, a D flip-flop D3, a D flip-flop D4, an AND gate AND1, an AND gate AND2, a NOR gate NOR1 and a NOR gate NOR2;

[0056] The D input terminal of the D flip-flop D1 and the D input terminal of the D flip-flop D2 are used to input the power supply VIO, the clock input terminal SCLK is electrically connected to the clock terminal of the D flip-flop D1, the data input terminal SDATA is electrically connected to the clock terminal of the D flip-flop D2, the Q output terminal of the D flip-flop D1 is electrically connected to the clock terminal of the D flip-flop D3, and the Q output terminal of the D flip-flop D2 is electrically connected to the clock terminal of the D flip-flop D4;

[0057] The Q output terminal of the D flip-flop D3 is electrically connected to the first input terminal of the AND gate AND1 and the first input terminal of the NOR gate NOR2 respectively, and the Q output terminal of the D flip-flop D4 is electrically connected to the first input terminal of the AND gate AND2 and the first input terminal of the NOR gate NOR1 respectively;

[0058] The Q non-output terminal of the D flip-flop D3 is electrically connected to the second input terminal of the AND gate AND2, the output terminal of the AND gate AND2 is electrically connected to the second input terminal of the NOR gate NOR1 for outputting the first selection signal SEL, and the output terminal of the NOR gate NOR1 is electrically connected to the D input terminal of the D flip-flop D3;

[0059] The Q non-output terminal of the D flip-flop D4 is electrically connected to the second input terminal of the AND gate AND1, the output terminal of the AND gate AND1 is electrically connected to the second input terminal of the NOR gate NOR2 for outputting the second selection signal SELB, and the output terminal of the NOR gate NOR2 is electrically connected to the Q input terminal of the D flip-flop D4;

[0060] The reset terminal of the D flip-flop D1 is electrically connected to the reset terminals of the D flip-flop D2 , the D flip-flop D3 , and the D flip-flop D4 , respectively.

[0061] for Figure 6In the circuit shown, when the power supply VIO is powered on, the reset end of the D flip-flop D1, the reset end of the D flip-flop D2, the reset end of the D flip-flop D3 and the reset end of the D flip-flop D4 will input a reset signal, so that the first selection signal SEL and the second selection signal SELB are both in a low level state;

[0062] When the power supply VIO is powered on and stabilized, if the clock input terminal SCLK and the data input terminal SDATA receive a MIPI instruction, at this time, if the clock input terminal SCLK generates a high level before the data input terminal SDATA, that is, a rising edge is detected, it is immediately determined that the clock input terminal SCLK actually inputs a data signal in the MIPI protocol, and the other input terminal inputs a clock signal in the MIPI protocol. At this time, the first selection signal SEL is a low-level signal, and the second selection signal SELB is a high-level signal; vice versa, if the data input terminal SDATA generates a high level before the clock input terminal SCLK, that is, a rising edge is detected, it is immediately determined that the data input terminal SDATA actually inputs a data signal in the MIPI protocol. At this time, the first selection signal SEL is a high-level signal, and the second selection signal SELB is a low-level signal; vice versa, if the data input terminal SDATA generates a high level before the clock input terminal SCLK, that is, a rising edge is detected, it is immediately determined that the data input terminal SDATA actually inputs a data signal in the MIPI protocol. At this time, the first selection signal SEL is a high-level signal, and the second selection signal SELB is a low-level signal;

[0063] The first selection signal SEL and the second selection signal SELB are used to control the on and off of the corresponding switch unit.

[0064] Embodiment 2

[0065] This embodiment further provides a radio frequency chip, on which is provided an identification circuit for a clock line and a data line of a MIPI interface in the first embodiment.

[0066] The above is based on the enlightenment of this utility model. Through the above description, relevant staff can make various changes and modifications without deviating from the technical idea of ​​this utility model. The technical scope of this utility model is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A circuit for identifying a clock line and a data line of a MIPI interface, characterized in that: The invention comprises an output switching unit, a detection unit and a decoding unit, wherein the output switching unit comprises a clock input terminal, a data input terminal, a clock output terminal and a data output terminal; the detection unit is electrically connected to the clock input terminal and the data input terminal, and is used to detect the SSC signal input to the clock input terminal and the data input terminal, and input the selection signal to the output switching unit and the decoding unit respectively; The output switching unit controls the clock input terminal and the data input terminal, one end of which the clock signal is input, to be electrically connected to the clock output terminal, and controls the clock input terminal and the data input terminal, one end of which the data signal is input, to be electrically connected to the data output terminal in response to the selection signal; The decoding unit is electrically connected to the clock output terminal and the data output terminal, and sets its own ID information in response to the selection signal.

2. The identification circuit for a clock line and a data line of a MIPI interface according to claim 1, characterized in that: The output switching unit includes a first switch unit, a second switch unit, a third switch unit and a fourth switch unit; The clock input end is electrically connected to the input end of the first switch unit and the input end of the third switch unit respectively, and the data input end is electrically connected to the input end of the second switch unit and the fourth switch unit respectively; The output end of the first switch unit and the output end of the second switch unit are electrically connected to the clock output end, and the output end of the third switch unit and the output end of the fourth switch unit are electrically connected to the data output end; The selection signal is input to the control terminals of the first to fourth switch units to control the on and off of the first to fourth switch units.

3. According to the identification circuit of the clock line and data line of the MIPI interface according to claim 2, the detection unit outputs a first selection signal and a second selection signal, the first selection signal and the second selection signal are two opposite signals, the first selection signal is input to the control end of the first switch unit and the control end of the fourth switch unit, and the second selection signal is input to the control end of the second switch unit and the control end of the third switch unit.

4. According to the identification circuit of the clock line and the data line of the MIPI interface of claim 3, the first switch unit and the fourth switch unit are turned on when the first selection signal is at a high level, and are turned off when the first selection signal is at a low level; The second switch unit and the third switch unit are turned on when the second selection signal is at a high level, and are turned off when the second selection signal is at a low level.

5. According to the identification circuit of the clock line and the data line of the MIPI interface of claim 3, the detection unit comprises a D flip-flop D1, a D flip-flop D2, a D flip-flop D3, a D flip-flop D4, an AND gate AND1, an AND gate AND2, a NOR gate NOR1 and a NOR gate NOR2; The D input terminal of the D flip-flop D1 and the D input terminal of the D flip-flop D2 are used to input the power supply VIO, the clock input terminal is electrically connected to the clock terminal of the D flip-flop D1, the data input terminal is electrically connected to the clock terminal of the D flip-flop D2, the Q output terminal of the D flip-flop D1 is electrically connected to the clock terminal of the D flip-flop D3, and the Q output terminal of the D flip-flop D2 is electrically connected to the clock terminal of the D flip-flop D4; The Q output terminal of the D flip-flop D3 is electrically connected to the first input terminal of the AND gate AND1 and the first input terminal of the NOR gate NOR2 respectively, and the Q output terminal of the D flip-flop D4 is electrically connected to the first input terminal of the AND gate AND2 and the first input terminal of the NOR gate NOR1 respectively; The Q non-output terminal of the D flip-flop D3 is electrically connected to the second input terminal of the AND gate AND2, the output terminal of the AND gate AND2 is electrically connected to the second input terminal of the NOR gate NOR1 for outputting the first selection signal, and the output terminal of the NOR gate NOR1 is electrically connected to the D input terminal of the D flip-flop D3; The Q non-output terminal of the D flip-flop D4 is electrically connected to the second input terminal of the AND gate AND1, the output terminal of the AND gate AND1 is electrically connected to the second input terminal of the NOR gate NOR2 for outputting the second selection signal, and the output terminal of the NOR gate NOR2 is electrically connected to the Q input terminal of the D flip-flop D4; The reset terminal of the D flip-flop D1 is electrically connected to the reset terminals of the D flip-flop D2 , the D flip-flop D3 , and the D flip-flop D4 , respectively.

6. According to the identification circuit of the clock line and the data line of the MIPI interface of claim 5, the clock input end is electrically connected to the input end of the first switch unit and the input end of the third switch unit through the input buffer Q1.

7. According to the identification circuit of the clock line and the data line of the MIPI interface of claim 6, the data input end is electrically connected to the input end of the second switch unit and the input end of the fourth switch unit through the input buffer Q2.

8. According to the identification circuit of the clock line and data line of the MIPI interface according to claim 7, the data reading output end of the decoding unit is electrically connected to the input end of the output buffer Q3 and the input end of the output buffer Q4, respectively, the output end of the output buffer Q3 is electrically connected to the clock input end, and the output end of the output buffer Q4 is electrically connected to the data input end.

9. A clock line and data line identification circuit for a MIPI interface according to claim 8, further comprising an OR gate OR1 and an OR gate OR2, wherein the first input end of the OR gate OR1 is used to input a first selection signal, the first input end of the OR gate OR2 is used to input a second selection signal, the second input end of the OR gate OR1 and the second input end of the OR gate OR2 are electrically connected to the decoding unit for receiving a data read enable signal, the output end of the OR gate OR1 is electrically connected to the control end of the output buffer Q3, and the output end of the OR gate OR2 is electrically connected to the control end of the output buffer Q4.

10. A radio frequency chip, characterized in that: The radio frequency chip is provided with an identification circuit for a clock line and a data line of a MIPI interface as described in any one of claims 1 to 9.

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