Laser diode capable of buffering stress
By introducing a buffer layer structure into the active region of the laser diode to buffer stress, the problem of lattice misalignment defect caused by stress release is solved, the performance and reliability of the laser diode are improved, and the thickness limitation of the substrate structure is improved.
Patent Information
- Application Number
- CN202420991188.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-09
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2034-05-09
AI Technical Summary
Existing laser diodes are prone to lattice misalignment defects when stress is released, which affects their working efficiency and reliability. The thickness of the substrate structure is limited, making it difficult to contain large stresses.
The first buffer layer and the second buffer layer are introduced into the active region of the laser diode, which are located between the quantum well layer and the first quantum energy barrier layer, the quantum well layer and the second quantum energy barrier layer respectively, to buffer the stress and reduce the stress Possibility of spontaneous release.
It effectively avoids the occurrence of lattice misalignment defects, improves the working efficiency and component reliability of the laser diode, improves the thickness limit of the substrate structure, and increases the number of quantum well units.
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Figure CN222191421U_ABST
Abstract
Description
Technical Field
[0001] A laser diode, especially a stress-buffered laser diode. Background Art
[0002] In the field of semiconductor laser technology, a laser diode has a P-type semiconductor, an N-type semiconductor, and an active region. The active region is located between the P-type semiconductor and the N-type semiconductor, and when the electrons in the active region combine with holes, energy is released in the form of photons. The generated photons can be further resonated and beamed into laser light through the design of a resonator.
[0003] See also Figure 6 As shown, an active region 110 of a conventional laser diode 100 needs to have at least one quantum well structure. Figure 6 In the example shown, the active region 110 is the most basic structure with a single quantum well, that is, the active region 110 includes a quantum well layer 104, and the quantum well layer 104 is sandwiched by a first quantum barrier layer 103 and a second quantum barrier layer 105. Further, the N-type semiconductor sandwiching the active region 110 includes an N-type cladding layer 102, and the N-type cladding layer 102 is stacked between a substrate 101 and the first quantum barrier layer 103. The P-type semiconductor sandwiching the active region 110 includes a P-type cladding layer 106 and a P-type contact layer 107, and the P-type cladding layer 106 is stacked between the P-type contact layer 107 and the second quantum barrier layer 105. Figure 6 In the structure shown, the P-type contact layer 107 is the top layer, and the substrate 101 is the bottom layer.
[0004] When epitaxy growth occurs, Figure 6When the conventional laser diode 100 is shown, the prior art tends to impart stress (strain) to the structure of the active region 110, so as to generate a compression (compress) or a stretch (tensile) on the lattice order structure, thereby changing the energy band (energy band) and adjusting the light-emitting characteristics of the laser diode. When the lattice order of the quantum well layer 104 in the active region 110 is compressed, the lattice order of the first quantum barrier layer 103 and the second quantum barrier layer 105 in the active region 110 is stretched. When the lattice order of the quantum well layer 104 in the active region 110 is stretched, the lattice order of the first quantum barrier layer 103 and the second quantum barrier layer 105 in the active region 110 is compressed. It should be clarified here that it is slightly different from the cognition in some existing teaching materials. The stress (strain) described here refers to the force (force) of applying pressure (stress) to the structure to cause the structure to produce strain (strain). In order to facilitate the definition of this force, the stress (strain) will be described in this way throughout the following.
[0005] The stress between the quantum well layer 104 and the first quantum barrier layer 103 or the second quantum barrier layer 105 is related to the difference between the lattice constant of the quantum well layer 104 and the lattice constant of the first quantum barrier layer 103 or the second quantum barrier layer 105. In detail, the stress can be defined by the following formula:
[0006] f strain =(a f -a sub ) / a sub
[0007] where f strain is stress, a f is the lattice constant of the film, a sub is the lattice constant of the substrate. Figure 6 , all structures carried on the substrate 101 are classified as the above-mentioned thin film. And, when a f Greater than a sub When a f Less than a sub When a f Equal to a sub When the film and substrate are subjected to stress, they are considered to be stress-free, that is, they are in a lattice matched state.
[0008] However, in two cases, the stress between the film and the substrate will be released spontaneously. f and a sub The difference is too large, and the other situation is that the thickness of the film is too large, causing the stress to be released. A critical value of the film thickness is a critical thickness, and this critical thickness is defined by the following formula:
[0009]
[0010] where h c is the critical thickness, b is the Burger vector, v is the Poisson's ratio, and θ and λ are the angles formed by the dislocation and the slip plane. strain The larger the h c In other words, in order to prevent the stress contained in the conventional laser diode 100 from being released, the thickness of the structure carried on the substrate 101 of the conventional laser diode 100 is limited to a certain extent and cannot exceed the critical thickness, so that the thickness of the active region 110 is also limited.
[0011] See also Figure 7 As shown, when the thickness of the structure carried on the substrate 101 is greater than the critical thickness and causes stress release, the conventional laser diode 100 will generate a plurality of misfit defects 201 on the lattice arrangement of its top-view surface 200. The top-view surface 200 is photographed by a high-resolution optical microscope, and the misfit defects 201 will negatively affect the working performance and component reliability of the laser diode. In order to avoid the generation of the misfit defects 201, the active region 110 of the conventional laser diode 100 needs to be improved in structure to facilitate the ability to contain a larger maximum stress in the active region 110 and reduce the possibility of spontaneous release of the stress contained in the active region 110. Utility Model Content
[0012] The utility model provides a laser diode capable of buffering stress, which can improve the structure of the conventional laser diode so that the active region of the laser diode can contain greater stress, thereby reducing the possibility of spontaneous release of the stress contained in the active region.
[0013] The laser diode capable of buffering stress of the utility model comprises:
[0014] a substrate layer;
[0015] A first semiconductor coating layer is disposed on the substrate layer and has a first semiconductor polarity;
[0016] An active region is disposed on the first semiconductor cladding layer; wherein the active region further comprises:
[0017] A first quantum barrier layer is disposed on the first semiconductor cladding layer;
[0018] At least one quantum well unit is disposed on the first quantum barrier layer; wherein each of the quantum well units comprises:
[0019] a first buffer layer disposed on the first quantum barrier layer;
[0020] A quantum well layer is disposed on the first buffer layer;
[0021] a second buffer layer disposed on the quantum well layer;
[0022] a second quantum barrier layer, disposed on the second buffer layer;
[0023] A second semiconductor cladding layer, disposed on the active region, having a second semiconductor polarity; wherein the first semiconductor polarity is different from the second semiconductor polarity;
[0024] A contact layer is disposed on the second semiconductor cladding layer and has the second semiconductor polarity.
[0025] In one embodiment, the active region of the utility model has only one quantum well unit, so the active region has the quantum well layer disposed between the first quantum barrier layer and the second quantum barrier layer. Crucially, the first buffer layer disposed between the quantum well layer and the first quantum barrier layer can help buffer the stress between the quantum well layer and the first quantum barrier layer. Similarly, the second buffer layer disposed between the quantum well layer and the second quantum barrier layer can help buffer the stress between the quantum well layer and the second quantum barrier layer. And, in general, the stress buffered by the first buffer layer and the second buffer layer respectively can help buffer the stress contained between the substrate layer and the structure carried by the substrate layer. Therefore, by providing the first buffer layer and the second buffer layer, the utility model can help reduce the possibility of spontaneous release of contained stress, thereby avoiding the generation of dislocation defects.
[0026] In another embodiment, the active region of the utility model has a plurality of quantum well units, for example, N quantum well units, and N is a positive integer greater than 1. Thus, N first buffer layers, N quantum well layers, N second buffer layers, and N second quantum barrier layers are stacked between the first quantum barrier layer and the second semiconductor cladding layer. Similarly, in each quantum well unit, the first buffer layer still has the function of buffering the stress between the quantum well layer and the first quantum barrier layer, and the second buffer layer still has the function of buffering the stress between the quantum well layer and the second quantum barrier layer. Moreover, in general, the stress buffered by each first buffer layer and each second buffer layer can help buffer the stress contained between the substrate layer and the structure carried by the substrate layer. Therefore, by setting the first buffer layer and the second buffer layer, the utility model helps reduce the possibility of spontaneous release of contained stress, that is, increases the value of the critical thickness. Thus, as the critical thickness increases, the number of quantum well units in the active region can be further increased and spontaneous stress release is less likely to occur.
[0027] In summary, regardless of whether the active region of the present invention has a single quantum well or multiple quantum well structure, the first buffer layer and the second buffer layer added to the active region of the present invention can buffer the stress contained between different stacked structures, thereby reducing the possibility of spontaneous release of stress contained in the active region, that is, reducing the possibility of misfit defects caused by stress release. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 It is a cross-sectional schematic diagram of a laser diode capable of buffering stress according to an embodiment of the present invention.
[0029] Figure 2 It is a cross-sectional schematic diagram of a quantum well unit of a laser diode capable of buffering stress according to the utility model.
[0030] Figure 3 The top view of the surface of the stress-buffering laser diode of the utility model is observed with a high-resolution optical microscope.
[0031] Figure 4 It is a cross-sectional schematic diagram of multiple quantum well units of a laser diode capable of buffering stress according to the utility model.
[0032] Figure 5 FIG. 4 is a cross-sectional diagram of another embodiment of a laser diode capable of buffering stress according to the utility model.
[0033] Figure 6is a schematic cross-sectional view of a conventional laser diode.
[0034] Figure 7 This is a top-down view of the surface of a conventional laser diode observed using a high-resolution optical microscope.
[0035] Main component symbols:
[0036] 1: Laser diodes that can buffer stress
[0037] 2: Substrate layer
[0038] 3: First semiconductor coating layer
[0039] 4: Active Zone
[0040] 5: Second semiconductor coating layer
[0041] 6: Contact layer
[0042] 10: Looking down at the surface
[0043] 41: First quantum well unit
[0044] 4N: Nth quantum well unit
[0045] 100: Conventional laser diode
[0046] 101:Substrate
[0047] 102: N-type cladding
[0048] 103: First quantum barrier layer
[0049] 104: Quantum Well Layer
[0050] 105: Second quantum barrier layer
[0051] 106: P-type cladding
[0052] 107: P-type contact layer
[0053] 110: Active Zone
[0054] 200: Looking down at the surface
[0055] 400: First quantum barrier layer
[0056] 410: Quantum Well Layer
[0057] 411: first buffer layer
[0058] 411A: first bottom surface
[0059] 411B: first upper surface
[0060] 412: Second buffer layer
[0061] 412A: Second bottom surface
[0062] 412B: Second upper surface
[0063] 413: Second quantum barrier layer
[0064] 4N0: Quantum Well Layer
[0065] 4N1: First buffer layer
[0066] 4N2: Second buffer layer
[0067] 4N3: Second quantum barrier layer DETAILED DESCRIPTION
[0068] See also Figure 1 and Figure 2 As shown, the utility model provides a stress buffering laser diode 1. The stress buffering laser diode 1 comprises a substrate layer 2, a first semiconductor cladding layer 3, an active region 4, a second semiconductor cladding layer 5 and a contact layer 6.
[0069] The first semiconductor cladding layer 3 is disposed on the substrate layer 2, and the first semiconductor cladding layer 3 has a first semiconductor polarity. The active region 4 is stacked between the first semiconductor cladding layer 3 and the second semiconductor cladding layer 5. In other words, the active region 4 is disposed on the first semiconductor cladding layer 3, and the second semiconductor cladding layer 5 is disposed on the active region 4. The second semiconductor cladding layer 5 has a second semiconductor polarity opposite to the first semiconductor polarity, and the contact layer 6 is disposed on the second semiconductor cladding layer 5, and the contact layer 6 also has the same second semiconductor polarity as the second semiconductor cladding layer 5.
[0070] The so-called semiconductor polarity refers to an N-type semiconductor or a P-type semiconductor. Therefore, in one embodiment, the first semiconductor polarity is an N-type semiconductor, that is, the first semiconductor cladding layer 3 is an N-type semiconductor layer (n-type semiconductor layer), and the second semiconductor polarity is a P-type semiconductor, that is, the second semiconductor cladding layer 5 and the contact layer 6 are respectively P-type semiconductor layers (p-type semiconductor layer). In another embodiment, the above semiconductor polarities are opposite in configuration, that is, the first semiconductor polarity is a P-type semiconductor, that is, the first semiconductor cladding layer 3 is a P-type semiconductor layer, and the second semiconductor polarity is an N-type semiconductor, that is, the second semiconductor cladding layer 5 and the contact layer 6 are respectively N-type semiconductor layers.
[0071] Furthermore, the active region 4 stacked between the first semiconductor cladding layer 3 and the second semiconductor cladding layer 5 further has a first quantum barrier layer 400 and at least one quantum well unit. In this embodiment, the at least one quantum well unit is only a single quantum well unit, such as a first quantum well unit 41. In other embodiments, the at least one quantum well unit is a plurality of quantum well units, and the quantum well units are stacked with each other.
[0072] The first quantum barrier layer 400 is disposed on the first semiconductor cladding layer 3 , the at least one quantum well unit is disposed between the first quantum barrier layer 400 and the second semiconductor cladding layer 5 , and the structure of each quantum well unit is the same as that of the first quantum well unit 41 .
[0073] In this embodiment, the first quantum well unit 41 has a quantum well layer 410, a first buffer layer 411, a second buffer layer 412 and a second quantum barrier layer 413. The first buffer layer 411 is disposed between the quantum well layer 410 and the first quantum barrier layer 400, the second quantum barrier layer 413 is disposed between the quantum well layer 410 and the second semiconductor cladding layer 5, and the second buffer layer 412 is further disposed between the quantum well layer 410 and the second quantum barrier layer 413. In other words, the first buffer layer 411 is disposed on the first quantum barrier layer 400, the quantum well layer 410 is disposed on the first buffer layer 411, the second buffer layer 412 is disposed on the quantum well layer 410, and the second quantum barrier layer 413 is disposed on the second buffer layer 412.
[0074] In this embodiment, the stress-buffering laser diode 1 is a single quantum well structure. Figure 1 In the structure shown, the contact layer 6 is the top layer, and the substrate layer 2 is the bottom layer. From the bottom layer to the top layer, the structure is sequentially stacked with the substrate layer 2, the first semiconductor cladding layer 3, the first quantum barrier layer 400 in the active region 4, the first buffer layer 411 of the first quantum well unit 41 in the active region 4, the quantum well layer 410, the second buffer layer 412, the second quantum barrier layer 413, the second semiconductor cladding layer 5 and the contact layer 6. When a current flows through the substrate layer 2 and the contact layer 6, the active region 4 will generate a plurality of photons, and these photons can be further resonated and bundled into laser beams through the design of a resonator.
[0075] The key to the present invention is that the first buffer layer 411 disposed between the quantum well layer 410 and the first quantum barrier layer 400 can help buffer the stress between the quantum well layer 410 and the first quantum barrier layer 400. In addition, the second buffer layer 412 disposed between the quantum well layer 410 and the second quantum barrier layer 413 can help buffer the stress between the quantum well layer 410 and the second quantum barrier layer 413. Therefore, in general, the stress buffered by the first buffer layer 411 and the second buffer layer 412 can help buffer the stress contained between the substrate layer 2 and the structure carried by the substrate layer 2. Therefore, by providing the first buffer layer 411 and the second buffer layer 412, the present invention can help reduce the possibility of spontaneous release of the contained stress, thereby avoiding the generation of misfit defects. Regarding the principle of reducing the possibility of spontaneous release of contained stress in the present invention, please refer to the formula and technical background provided in the previous technical paragraph.
[0076] Preferably, the stacked structure of the first quantum barrier layer 400, the first buffer layer 411 and the quantum well layer 410 is symmetric with the stacked structure of the second quantum barrier layer 413, the second buffer layer 412 and the quantum well layer 410. For example, the stacked structure of the first quantum barrier layer 400, the first buffer layer 411 and the quantum well layer 410 has a thickness ratio of 7:4:5, and the stacked structure of the second quantum barrier layer 413, the second buffer layer 412 and the quantum well layer 410 also has a thickness ratio of 7:4:5. In other words, in this embodiment, the thickness of the first quantum barrier layer 400 and the second quantum barrier layer 413 is respectively greater than the thickness of the quantum well layer 410, while the thickness of the first buffer layer 411 and the second buffer layer 412 is respectively less than the thickness of the quantum well layer 410.
[0077] Preferably, the first buffer layer 411 and the second buffer layer 412 each have a buffer layer thickness, and the buffer layer thickness is between The photons generated by the active region 4 each have an emission wavelength, and the emission wavelength is between 1200nm and 2000nm. The laser beam after focusing has a wavelength between 1200nm and 2000nm.
[0078] Please also read Figure 3 As shown, through observation of a top view surface 10 of the stress buffering laser diode 1 of the utility model with a high-resolution optical microscope, it can be seen that the top view surface 10 of the stress buffering laser diode 1 of the utility model no longer shows the Figure 7The top view surface 200 of a conventional laser diode shows a plurality of dislocation defects 201. The stress-buffering laser diode 1 that no longer has the dislocation defects 201 can have better laser working performance and component reliability, so that the stress-buffering laser diode 1 of the utility model improves the conventional laser diode in many aspects. The avoidance and improvement of the dislocation defects 201 is the function of the first buffer layer 411 and the second buffer layer 412 added in the utility model to buffer stress.
[0079] In addition, if Figure 1 As shown, the first buffer layer 411 has a first bottom surface 411A facing the first semiconductor cladding layer 3 and a first upper surface 411B facing the second semiconductor cladding layer 5. The second buffer layer 412 has a second bottom surface 412A facing the first semiconductor cladding layer 3 and a second upper surface 412B facing the second semiconductor cladding layer 5. The first bottom surface 411A, the first upper surface 411B, the second bottom surface 412A and the second upper surface 412B are respectively surfaces that are deformed by stress during the epitaxial growth stage.
[0080] For example, the stress-buffering laser diode 1 of the present invention is epitaxially grown from the bottom substrate layer 2 to the top contact layer 6 layer by layer. During this process, in order to ensure that there is no excessive stress between the bottom substrate layer 2 and any upper structure it carries, the present invention has the following different arrangements.
[0081] In one embodiment, when the first quantum barrier layer 400 and the second quantum barrier layer 413 are arranged to have compressive strain relative to the substrate layer 2, and the quantum well layer 410 is arranged to have tensile strain relative to the substrate layer 2, the first bottom surface 411A of the first buffer layer 411 and the second upper surface 412B of the second buffer layer 412 are arranged to have compressive stress relative to the substrate layer 2, and the first upper surface 411B of the first buffer layer 411 and the second bottom surface 412A of the second buffer layer 412 are arranged to have tensile stress relative to the substrate layer 2.
[0082] When the first quantum barrier layer 400 and the second quantum barrier layer 413 are arranged to have tensile stress relative to the substrate layer 2, and the quantum well layer 410 is arranged to have compressive stress relative to the substrate layer 2, the first bottom surface 411A of the first buffer layer 411 and the second upper surface 412B of the second buffer layer 412 are arranged to have tensile stress relative to the substrate layer 2, and the first upper surface 411B of the first buffer layer 411 and the second bottom surface 412A of the second buffer layer 412 are arranged to have compressive stress relative to the substrate layer 2.
[0083] Thus, the stress between the first quantum barrier layer 400 and the first buffer layer 411 will cancel each other out due to the different properties of the tensile and compressive stresses, and the stress properties between the first buffer layer 411 and the quantum well layer 410 are also different and cancel each other out. The stress between the second quantum barrier layer 413 and the second buffer layer 412 will cancel each other out due to the different properties of the tensile and compressive stresses, and the stress properties between the second buffer layer 412 and the quantum well layer 410 are also different and cancel each other out. Thus, almost no accumulated stress will be generated in the active region 4 as a whole, so the accumulated stress between the active region 4 and the substrate layer 2 can be buffered or eliminated, thereby avoiding the excessive stress between the active region 4 and the substrate layer 2 and releasing the stress.
[0084] In another embodiment, when the first quantum barrier layer 400 and the second quantum barrier layer 413 are both arranged to have compressive stress relative to the substrate layer 2, and the quantum well layer 410 has tensile stress relative to the substrate layer 2, a graded stress of stress change is arranged as follows for buffering. For example, the first bottom surface 411A of the first buffer layer 411 has tensile stress relative to the substrate layer 2, the first upper surface 411B of the first buffer layer 411 has compressive stress relative to the substrate layer 2, and a first stress change graded layer is provided between the first bottom surface 411A and the first upper surface 411B. The second upper surface 412B of the second buffer layer 412 has tensile stress relative to the substrate layer 2, the second bottom surface 412A of the second buffer layer 412 has compressive stress relative to the substrate layer 2, and a second stress change graded layer is provided between the second bottom surface 412A and the second upper surface 412B. The first stress change gradient and the second stress change gradient have opposite change directions.
[0085] When the first quantum barrier layer 400 and the second quantum barrier layer 413 are arranged to have tensile stress relative to the substrate layer 2, and the quantum well layer 410 has compressive stress relative to the substrate layer 2, the gradient of stress change is arranged as follows for buffering. For example, the first bottom surface 411A of the first buffer layer 411 has compressive stress relative to the substrate layer 2, the first upper surface 411B of the first buffer layer 411 has tensile stress relative to the substrate layer 2, and the second stress change gradient is provided between the first bottom surface 411A and the first upper surface 411B. The second upper surface 412B of the second buffer layer 412 has compressive stress relative to the substrate layer 2, the second bottom surface 412A of the second buffer layer 412 has tensile stress relative to the substrate layer 2, and the first stress change gradient is provided between the second bottom surface 412A and the second upper surface 412B.
[0086] In this way, the stress between the first quantum barrier layer 400 and the quantum well layer 410 can be gradually buffered. The stress between the second quantum barrier layer 413 and the quantum well layer 410 can also be gradually buffered. In this way, the accumulated stress generated in the active region 4 as a whole and the substrate layer 2 can be buffered, thereby reducing the possibility of excessive stress between the active region 4 and the substrate layer 2 and releasing the stress.
[0087] Of course, there is another embodiment, that is, the laser diode 1 that can buffer stress originally has a structural design without adding stress. In this case, relative to the substrate layer 2, the first quantum barrier layer 400, the second quantum barrier layer 413 and the quantum well layer 410 are all lattice matched and do not have stress. In this way, there is naturally no need to worry about the problem and possibility of releasing stress due to excessive stress between the active region 4 and the substrate layer 2.
[0088] Preferably, the substrate layer 2, the first semiconductor cladding layer 3 and the second semiconductor cladding layer 5 are indium phosphide layers (InP layers) doped with different semiconductor types. For example, the first semiconductor cladding layer 3 is an n-type indium phosphide cladding layer (n-InP cladding layer), and the second semiconductor cladding layer 5 is a p-type indium phosphide cladding layer (p-InP cladding layer). The contact layer 6 is an indium gallium arsenide contact (InGaAs contact), and for another example, the contact layer 6 is doped to become a p-type indium gallium arsenide contact (p-InGaAs contact). The first quantum barrier layer 400, the quantum well layer 410, the first buffer layer 411, the second buffer layer 412 and the second quantum barrier layer 413 are alloy semiconductor layers.
[0089] Specifically, any layer among the first quantum barrier layer 400, the quantum well layer 410, the first buffer layer 411, the second buffer layer 412 and the second quantum barrier layer 413 can be any combination of an indium galliumarsenide layer (InGaAs layer), an indium gallium arsenide phosphide layer (InGaAsP layer) or an aluminum gallium indium arsenide layer (InAlGaAs layer).
[0090] In another embodiment, the first buffer layer 411 and the second buffer layer 412 may also be relatively simple semiconductor layers. For example, the first buffer layer 411 and the second buffer layer 412 are respectively the indium phosphide layer.
[0091] See also Figure 4 and Figure 5As shown, in another embodiment, the at least one quantum well unit in the active region 4 is a plurality of quantum well units, that is, the active region 4 has a multiple quantum well structure. The quantum well units include the aforementioned first quantum well unit 41 and an Nth quantum well unit 4N, that is, N quantum well units are included, wherein N represents a positive integer greater than 1. In one embodiment, the Nth quantum well unit 4N is structurally the same as the first quantum well unit 41. That is, the Nth quantum well unit 4N includes a quantum well layer 4N0, a first buffer layer 4N1, a second buffer layer 4N2, and a second quantum barrier layer 4N3, and the quantum well layer 4N0 is stacked between the first buffer layer 4N1 and the second buffer layer 4N2, and the second quantum barrier layer 4N3 is disposed on the side of the second buffer layer 4N2 facing away from the quantum well layer 4N0. However, the side of the second quantum barrier layer 4N3 facing away from the quantum well layer 4N0 directly contacts the second semiconductor cladding layer 5, and the side of the first buffer layer 4N1 facing away from the quantum well layer 4N0 contacts the second quantum barrier layer of another quantum well unit. As for the first quantum well unit 41, the side of the second quantum barrier layer 413 of the first quantum well unit 41 facing away from the quantum well layer 410 contacts the first buffer layer of another quantum well unit, and the side of the first buffer layer 411 of the first quantum well unit 41 facing away from the quantum well layer 410 directly contacts the first quantum barrier layer 400. In other words, for the Nth quantum well unit 4N, the first buffer layer 4N1 of the Nth quantum well unit 4N is still relatively indirectly arranged on the first quantum barrier layer 400, and the quantum well layer 4N0 is arranged on the first buffer layer 4N1, the second buffer layer 4N2 is arranged on the quantum well layer 4N0, and the second quantum barrier layer 4N3 is arranged on the second buffer layer 4N2.
[0092] Because the Nth quantum well unit 4N is identical to the first quantum well unit 41 in structure, the Nth quantum well unit 4N has the same function of buffering or offsetting stress as the first quantum well unit 41. Therefore, even if the active region 4 is provided with a multi-quantum well structure and has a larger thickness, the problem and possibility of releasing stress due to excessive stress between the active region 4 and the substrate layer 2 can be avoided or reduced. This is because, according to the formula of critical thickness listed in the previous technical paragraph, the present invention reduces the generation of stress by buffering the first buffer layer and the second buffer layer provided in each quantum well unit, so the lower stress increases the value of the critical thickness, so that the substrate layer 2 can carry a thicker structure, which increases the thickness of the structure that can be arranged in the active region 4, and increases the number of quantum well units that can be added in the active region 4. That is to say, in the embodiment where the active region 4 has a multiple quantum well structure, the utility model can further demonstrate its advantages, so that the active region 4 can be more safely provided with multiple quantum well units than the prior art and it is less likely to cause the stress between the active region 4 and the substrate layer 2 to be spontaneously released.
Claims
1. A laser diode capable of buffering stress, characterized in that: include: a substrate layer; A first semiconductor coating layer is disposed on the substrate layer and has a first semiconductor polarity; An active region is disposed on the first semiconductor cladding layer; wherein the active region further comprises: A first quantum barrier layer is disposed on the first semiconductor cladding layer; At least one quantum well unit is disposed on the first quantum barrier layer; wherein each of the quantum well units comprises: a first buffer layer disposed on the first quantum barrier layer; A quantum well layer is disposed on the first buffer layer; a second buffer layer disposed on the quantum well layer; a second quantum barrier layer, disposed on the second buffer layer; A second semiconductor cladding layer, disposed on the active region, having a second semiconductor polarity; wherein the first semiconductor polarity is different from the second semiconductor polarity; A contact layer is disposed on the second semiconductor cladding layer and has the second semiconductor polarity.
2. The stress-bufferable laser diode according to claim 1, wherein: The at least one quantum well unit is a plurality of quantum well units, and the quantum well units are stacked and disposed between the first quantum barrier layer and the second semiconductor cladding layer.
3. The stress-bufferable laser diode according to claim 1, wherein: The first semiconductor cladding layer is a p-type semiconductor layer, and the second semiconductor cladding layer and the contact layer are n-type semiconductor layers.
4. The stress-bufferable laser diode according to claim 1, wherein: The first semiconductor cladding layer is an n-type semiconductor layer, and the second semiconductor cladding layer and the contact layer are p-type semiconductor layers.
5. The stress-bufferable laser diode according to claim 4, characterized in that: The substrate layer is an indium phosphide layer (InP layer), the first semiconductor cladding layer is an N-type indium phosphide cladding layer (n-InP cladding layer), the second semiconductor cladding layer is a P-type indium phosphide cladding layer (p-InP cladding layer), and the contact layer is a P-type indium gallium arsenide electrode pad (p-type indium gallium arsenide contact; p-InGaAs contact).
6. The stress-bufferable laser diode according to claim 1, wherein: The first buffer layer and the second buffer layer of the at least one quantum well unit each have a buffer layer thickness, and the buffer layer thickness is between 1 angstrom to 20 angstroms.
7. The stress-bufferable laser diode according to claim 1, wherein: When a current flows through the substrate layer and the contact layer, a photon generated in the active region has an emission wavelength, and the emission wavelength is between 1200nm and 2000nm.
8. The stress-bufferable laser diode according to claim 1, wherein: The first buffer layer of the at least one quantum well unit has a first bottom surface facing the first semiconductor cladding layer and a first upper surface facing the second semiconductor cladding layer; The second buffer layer of the at least one quantum well unit has a second bottom surface facing the first semiconductor cladding layer and a second upper surface facing the second semiconductor cladding layer; The first bottom surface, the first upper surface, the second bottom surface and the second upper surface are respectively surfaces that are deformed by stress during the epitaxial growth stage.
9. The stress-bufferable laser diode according to claim 8, wherein: The first quantum barrier layer and the second quantum barrier layer of the at least one quantum well unit both have compressive stress relative to the substrate layer, and the quantum well layer of the at least one quantum well unit has tensile stress relative to the substrate layer, the first bottom surface of the first buffer layer and the second upper surface of the second buffer layer both have compressive stress relative to the substrate layer, and the first upper surface of the first buffer layer and the second bottom surface of the second buffer layer both have tensile stress relative to the substrate layer.
10. The stress-bufferable laser diode according to claim 8, wherein: The first quantum barrier layer and the second quantum barrier layer of the at least one quantum well unit both have tensile strain relative to the substrate layer, and the quantum well layer of the at least one quantum well unit has compressive strain relative to the substrate layer, the first bottom surface of the first buffer layer and the second upper surface of the second buffer layer both have tensile stress relative to the substrate layer, and the first upper surface of the first buffer layer and the second bottom surface of the second buffer layer both have compressive stress relative to the substrate layer.
11. The stress-bufferable laser diode according to claim 8, wherein: The first quantum barrier layer and the second quantum barrier layer of the at least one quantum well unit both have compressive strain relative to the substrate layer, and the quantum well layer of the at least one quantum well unit has tensile strain relative to the substrate layer; The first bottom surface of the first buffer layer has a tensile stress relative to the substrate layer, the first upper surface of the first buffer layer has a compressive stress relative to the substrate layer, and a first stress change gradient is provided between the first bottom surface and the first upper surface; The second upper surface of the second buffer layer has a tensile stress relative to the substrate layer, the second bottom surface of the second buffer layer has a compressive stress relative to the substrate layer, and a second stress change gradient is provided between the second bottom surface and the second upper surface.
12. The stress-bufferable laser diode according to claim 8, wherein: The first quantum barrier layer and the second quantum barrier layer of the at least one quantum well unit both have tensile strain relative to the substrate layer, and the quantum well layer of the at least one quantum well unit has compressive strain relative to the substrate layer; The first bottom surface of the first buffer layer has a compressive stress relative to the substrate layer, the first upper surface of the first buffer layer has a tensile stress relative to the substrate layer, and a second stress change gradient is provided between the first bottom surface and the first upper surface; The second upper surface of the second buffer layer has compressive stress relative to the substrate layer, the second bottom surface of the second buffer layer has tensile stress relative to the substrate layer, and a first stress change gradient is provided between the second bottom surface and the second upper surface.
13. The stress-bufferable laser diode according to claim 8, wherein: Relative to the substrate layer, the first quantum barrier layer, the second quantum barrier layer of the at least one quantum well unit, and the quantum well layer are all lattice matched.
14. The stress-bufferable laser diode according to claim 1, wherein: The first quantum barrier layer and the quantum well layer of the at least one quantum well unit, the first buffer layer, the second buffer layer and the second quantum barrier layer are respectively an alloy semiconductor layer.
15. The stress-bufferable laser diode according to claim 14, wherein: At least one of the alloy semiconductor layers is an indium gallium arsenide layer (InGaAs layer), an indium gallium arsenide phosphide layer (InGaAsPlayer) or an aluminum gallium indium arsenide layer (AlGaInAs layer).
16. The stress-bufferable laser diode according to claim 1, wherein: The first buffer layer and the second buffer layer are respectively an indium phosphide layer (InP layer).
17. The stress-bufferable laser diode according to claim 1, wherein: In the at least one quantum well unit, the thickness of the first buffer layer and the thickness of the second buffer layer are respectively smaller than the thickness of the quantum well layer.