Circuit board

Abstract

A circuit board is provided. The circuit board includes a plurality of insulating layers, at least one conductive layer disposed between the plurality of insulating layers, a connection pad disposed under the at least one conductive layer, a signal line disposed under the at least one conductive layer and electrically connected to the connection pad; and a protective layer disposed under the at least one conductive layer and having a lower surface positioned in the same plane as a lower surface of the connection pad.

Description

Technical Field

[0001] The present application relates generally to circuit boards, and more particularly to circuit boards and display devices including the same. Background Art

[0002] As information technology develops, the importance of display devices as a communication medium between users and information is becoming prominent. Accordingly, the use of display devices such as liquid crystal display devices, organic light emitting display devices, plasma display devices, and the like is increasing.

[0003] Meanwhile, the display device includes a display panel and a circuit board, wherein the display panel may include a pad area where pad electrodes for receiving various signals, voltages, and the like from the outside are arranged. The circuit board may be connected to the pad area to provide various signals and voltages required to drive the display panel to the display panel. Utility Model Content

[0004] Embodiments provide a circuit board capable of reducing compression defects.

[0005] An embodiment provides a display device including a circuit board.

[0006] A circuit board according to an embodiment of the present application includes a plurality of insulating layers, at least one conductive layer arranged between the plurality of insulating layers, connecting pads arranged under the at least one conductive layer, signal lines arranged under the at least one conductive layer and electrically connected to the connecting pads, and a protective layer arranged under the at least one conductive layer and having a lower surface positioned in the same plane as a lower surface of the connecting pads.

[0007] In an implementation, the thickness of the protection layer may be equal to the thickness of the connection pad.

[0008] In an implementation, the at least one conductive layer may include a first conductive layer disposed on the connection pad and the signal line and a second conductive layer disposed on the first conductive layer.

[0009] In an embodiment, the plurality of insulating layers may include a first insulating layer arranged between a first conductive layer and a connecting pad, wherein the connecting pad may be connected to the first conductive layer via at least one first contact hole penetrating the first insulating layer, and wherein the signal line may be connected to the first conductive layer via at least one second contact hole penetrating the first insulating layer.

[0010] In an implementation, the first conductive layer may include a plurality of conductive patterns each extending in a first direction and spaced apart from each other in a second direction crossing the first direction, wherein the second conductive layer may have a plate shape.

[0011] In an implementation, the connection pad and the signal line may be spaced apart from each other in the first direction, wherein each of the plurality of conductive patterns may overlap the connection pad and the signal line in a plan view.

[0012] In an implementation, each of the first contact hole and the second contact hole may have a polygonal cross-sectional shape.

[0013] In an implementation, the at least one conductive layer may include a first conductive layer disposed on the connection pad and the signal line, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer.

[0014] In an embodiment, the multiple insulating layers may include a first insulating layer arranged between the first conductive layer and the connecting pad and a second insulating layer arranged on the first insulating layer, wherein the connecting pad may be connected to the first conductive layer via at least one first contact hole penetrating the first insulating layer, the signal line may be connected to the first conductive layer via at least one second contact hole penetrating the first insulating layer, and the second conductive layer may be connected to the first conductive layer via at least one third contact hole and at least one fourth contact hole penetrating the second insulating layer.

[0015] In an implementation, each of the first and second conductive layers may include a plurality of conductive patterns each extending in a first direction and spaced apart from each other in a second direction crossing the first direction, wherein the third conductive layer may have a plate shape.

[0016] In an embodiment, the signal line may be arranged on the protection layer, and the signal line may be integrated with the connection pad.

[0017] In an implementation, a thickness of a portion of the signal line overlapping the protection layer may be smaller than a thickness of the connection pad.

[0018] In an implementation, the protective layer may include a solder resist.

[0019] In an implementation, each of the connection pad, the signal line, and the conductive layer may include copper (Cu).

[0020] A display device according to an embodiment of the present application includes a substrate, a pad electrode and a circuit board, the substrate including a display area in which a plurality of pixels are arranged and a pad area spaced apart from one side of the display area, the pad electrode being arranged in the pad area on the substrate, the circuit board including a plurality of insulating layers, at least one conductive layer arranged between the plurality of insulating layers, a connecting pad arranged under the at least one conductive layer and connected to the pad electrode through an adhesive layer, a signal line arranged under the at least one conductive layer and electrically connected to the connecting pad, and a protective layer, the protective layer being arranged under the at least one conductive layer, overlapping with at least a portion of the pad area and having a lower surface positioned in the same plane as a lower surface of the connecting pad.

[0021] In an implementation, the thickness of the protection layer may be equal to the thickness of the connection pad.

[0022] In an implementation, the at least one conductive layer may include a first conductive layer disposed on the connection pad and the signal line and a second conductive layer disposed on the first conductive layer.

[0023] In an embodiment, the multiple insulating layers may include a first insulating layer arranged between the first conductive layer and the connecting pad, wherein the connecting pad may be connected to the first conductive layer via at least one first contact hole penetrating the first insulating layer, and the signal line may be connected to the first conductive layer via at least one second contact hole penetrating the first insulating layer.

[0024] In an embodiment, the first conductive layer may include a plurality of conductive patterns each extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, the second conductive layer may have a plate shape, the connecting pads and the signal lines may be spaced apart from each other in the first direction, and each of the plurality of conductive patterns may overlap with the connecting pads and the signal lines in a plan view.

[0025] In an embodiment, the signal line may be disposed on the protection layer and may be integrated with the connection pad, and wherein a thickness of a portion of the signal line overlapping the protection layer may be smaller than a thickness of the connection pad.

[0026] According to an embodiment, a circuit board may include at least one conductive layer, a connecting pad arranged under the at least one conductive layer, a signal line arranged under the at least one conductive layer and electrically connected to the connecting pad, and a protective layer arranged under the at least one conductive layer and having a lower surface positioned in the same plane as the lower surface of the connecting pad.

[0027] When the circuit board is coupled to the pad electrode arranged in the pad area on the substrate of the display panel, the protective layer of the circuit board may partially overlap the pad area. Accordingly, compression defects caused by lifting between the circuit board and the display panel can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 is a plan view of a display device according to an embodiment.

[0030] Figure 2 is a diagram showing a method for Figure 1 A schematic diagram of the circuit of one pixel of a display device.

[0031] Figure 3 According to the implementation method Figure 1 An enlarged plan view of area A.

[0032] Figure 4 According to the implementation method Figure 3 A cross-sectional view taken along line II' of region A.

[0033] Figure 5 It is shown that according to the embodiment Figure 4 A cross-sectional view of an example of the shape of each of the first contact hole and the second contact hole.

[0034] Figure 6 It is shown that according to the embodiment Figure 4 A cross-sectional view of an example of the shape of each of the first contact hole and the second contact hole.

[0035] Figure 7 It is shown that according to the embodiment Figure 4 A cross-sectional view of an example of the shape of each of the first contact hole and the second contact hole.

[0036] Figure 8 It is shown that according to the embodiment Figure 4 A cross-sectional view of an example of the shape of each of the first contact hole and the second contact hole.

[0037] Fig. 9 According to the implementation method Figure 4 An enlarged cross-sectional view of area B.

[0038] Fig.10 According to another embodiment Figure 1 An enlarged plan view of area A.

[0039] Fig.11 is a diagram showing the Fig.10 A sectional view of a section taken along line II-II'.

[0040] Fig.12 is a diagram showing a method according to another embodiment of the present invention. Fig.10 A sectional view of a section taken along line II-II'.

[0041] Fig.13 According to another embodiment Figure 1 An enlarged plan view of area A.

[0042] Fig.14 is a diagram showing the Fig.13 A cross-sectional view of a section taken along line III-III'.

[0043] Fig.15 is a diagram showing a method according to another embodiment of the present invention. Fig.13A cross-sectional view of a section taken along line III-III'.

[0044] Fig.16 According to another embodiment Figure 1 An enlarged plan view of area A.

[0045] Fig.17 is a diagram showing the Fig.16 A cross-sectional view of a section taken along line IV-IV'.

[0046] Fig.18 is a diagram showing a method according to another embodiment of the present invention. Fig.16 A cross-sectional view of a section taken along line IV-IV'.

[0047] Fig.19 The present invention includes Figure 1 A block diagram of an electronic device of a display device.

[0048] Fig. 20 FIG. 1 is a diagram showing a television set according to an embodiment. Fig.19 A perspective view of an electronic device.

[0049] Fig.21 is a diagram showing a smart phone according to another embodiment Fig.19 A perspective view of an electronic device. DETAILED DESCRIPTION

[0050] Hereinafter, a circuit board and a display device including a circuit board according to an embodiment of the present application will be explained in detail with reference to the accompanying drawings showing various embodiments. In the accompanying drawings, the same reference numerals are used for the same components, and redundant descriptions of the same components will be omitted. In addition, however, the present application can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present application will be fully conveyed to those skilled in the art.

[0051] It will be understood that when an element (or region, layer, portion and / or the like) is referred to as being associated with another (such as being "on," "connected to" or "coupled to" another element), it can be directly arranged on, directly connected or coupled to the other element, or intervening elements may be arranged therebetween.

[0052] Similar reference numerals or symbols always refer to similar elements. In the accompanying drawings, the thickness, proportion and size of the elements are exaggerated for the effective description of the technical content. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0053] The term "and / or" includes all combinations of one or more that can be defined by the associated configurations.

[0054] It will be understood that, although the terms first, second, etc. can be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, area, layer or part from another element, component, area, layer or part. Therefore, the first element, first component, first area, first layer or first part discussed below can be referred to as the second element, second component, second area, second layer or second part, without departing from the scope of the concept of the present application. Similarly, the second element, second component, second area, second layer or second part can be referred to as the first element, first component, first area, first layer or first part. Unless the context clearly indicates otherwise, the singular form "a", "an" and "the" as used herein are also intended to include plural forms.

[0055] Also, terms such as “below,” “on lower side,” “above,” “on upper side,” and / or the like may be used to describe the relationship of elements shown in the drawings. These terms have relative concepts and are described based on directions indicated in the drawings.

[0056] It will also be understood that when the terms "comprise", "include" and / or "have" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, components and / or clusters thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or clusters thereof. As used herein, "disposed directly on" may mean that there are no additional layers, films, regions, plates and / or the like between a part such as a layer, film, region, plate and / or the like and another part. For example, "disposed directly on" may mean that two layers or two components are arranged without using an additional component such as a bonding component therebetween.

[0057] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0058] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this application belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense.

[0059] Figure 1 is a plan view showing a display device according to an embodiment of the present application.

[0060] Reference Figure 1 , the display device 100 according to the embodiment may include a substrate SUB, a driving integrated circuit DIC, and a circuit board CB.

[0061] In an embodiment, the substrate SUB may include a display area DA and a non-display area NDA. The display area DA may be an area capable of displaying an image by generating light or adjusting transmittance of light provided from an external light source. The non-display area NDA may be an area where an image is not displayed.

[0062] In an embodiment, a plurality of pixels PX may be arranged in the display area DA. The plurality of pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2 crossing the first direction DR1. Each of the plurality of pixels PX may emit light. Since each of the plurality of pixels PX emits light, the display area DA may display an image.

[0063] In an embodiment, lines connected to the plurality of pixels PX may also be arranged in the display area DA. For example, the lines may include data signal lines, gate signal lines, and / or power lines.

[0064] In an embodiment, the non-display area NDA may be positioned around the display area DA. For example, the non-display area NDA may surround at least a portion of the display area DA. A driver may be arranged in the non-display area NDA. The driver may provide a signal and / or a voltage to the plurality of pixels PX. For example, the driver may include a gate driver, a light emitting driver, a power voltage generator, a timing controller, and the like.

[0065] In an embodiment, the non-display area NDA may include a pad area PA. The pad area PA may be spaced apart from one side of the display area DA in a direction opposite to the first direction DR1. For example, the pad area PA may have a shape extending in the second direction DR2.

[0066] In an embodiment, each of the driving integrated circuits DIC may be arranged in the pad area PA on the substrate SUB. The driving integrated circuits DIC may be arranged to be spaced apart from each other in the second direction DR2. Each of the driving integrated circuits DIC may convert a digital data signal among the driving signals into an analog data signal and provide the converted analog data signal to a plurality of pixels PX. For example, each of the driving integrated circuits DIC may be a data driver.

[0067] In an embodiment, the circuit board CB may be arranged in the pad area PA on the substrate SUB. Specifically, the circuit board CB may partially overlap the pad area PA. One end of the circuit board CB may be electrically connected to a pad electrode (e.g., Figure 4 The second pad electrode PE2 of the circuit board CB is provided, and the other end of the circuit board CB can be electrically connected to an external device. That is, the circuit board CB can be directly connected to the pad electrode. Accordingly, the dead zone of the display device 100 can be reduced. In addition, the manufacturing process of the display device 100 can be simplified. In addition, the manufacturing cost of the display device 100 can be reduced.

[0068] In an embodiment, an external device may generate a driving signal and a driving voltage to display an image on the display area DA. The driving signal, driving voltage, and the like generated from the external device may be provided to a plurality of driving integrated circuits DIC and a plurality of pixels PX through a circuit board CB and pad electrodes. In an embodiment, the circuit board CB may be a printed circuit board (PCB). A detailed description of components of the circuit board CB will be described later.

[0069] In this specification, a plane may be defined by a first direction DR1 and a second direction DR2 crossing the first direction DR1.

[0070] Figure 2 It is shown that according to the embodiment Figure 1 A schematic circuit diagram of one pixel of a display device.

[0071] Reference Figure 2 , each of the plurality of pixels PX of the display device 100 according to the embodiment may include first, second and third transistors T1, T2 and T3, a storage capacitor CST and a light emitting element LED.

[0072] In an embodiment, the first transistor T1 may include a source electrode, a drain electrode, and a gate electrode. The first transistor T1 may adjust a current flowing from the driving voltage line ELVDL supplied with the driving voltage to the light emitting element LED according to a voltage difference between the gate electrode and the source electrode.

[0073] In an embodiment, for example, the first transistor T1 may be a driving transistor for driving the light emitting element LED. A gate electrode of the first transistor T1 may be connected to the first node N1. A source electrode of the first transistor T1 may be connected to a first electrode of the light emitting element LED. A drain electrode of the first transistor T1 may be connected to a driving voltage line ELVDL to which a driving voltage is applied.

[0074] In an embodiment, the second transistor T2 may include a source electrode, a drain electrode, and a gate electrode. The second transistor T2 may be turned on by a gate signal of a gate signal line GSL to connect the data line DTL to the gate electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the gate signal line GSL. The source electrode of the second transistor T2 may be connected to the first node N1. The drain electrode of the second transistor T2 may be connected to the data line DTL.

[0075] In an embodiment, the third transistor T3 may include a source electrode, a drain electrode, and a gate electrode. The third transistor T3 may be turned on by a sensing signal of the sensing signal line SSL to connect the initialization voltage line VIL to one end of the light emitting element LED. The gate electrode of the third transistor T3 may be connected to the sensing signal line SSL. The source electrode of the third transistor T3 may be connected to the second node N2. The drain electrode of the third transistor T3 may be connected to the initialization voltage line VIL to which the initialization voltage is applied.

[0076] However, in an embodiment, the source electrode and the drain electrode of each of the first transistor T1, the second transistor T2, and the third transistor T3 are not limited thereto, and vice versa. In addition, each of the first transistor T1, the second transistor T2, and the third transistor T3 may be formed as a thin film transistor.

[0077] In an embodiment, the storage capacitor CST may include a first electrode and a second electrode. The first electrode of the storage capacitor CST may be connected to the first node N1. The second electrode of the storage capacitor CST may be connected to the second node N2. The storage capacitor CST may store a difference voltage between the gate voltage and the source voltage of the first transistor T1.

[0078] In an embodiment, the light emitting element LED may emit light according to the current supplied by the first transistor T1. The light emitting element LED may be an organic light emitting diode including a first electrode (e.g., an anode electrode), an organic light emitting layer, and a second electrode (e.g., a cathode electrode). However, the embodiment is not limited thereto. The first electrode of the light emitting element LED may be connected to the source electrode of the first transistor T1, and the second electrode of the light emitting element LED may be connected to a common voltage line ELVSL to which a common voltage lower than a driving voltage is applied.

[0079] However, in Figure 2In the embodiment, an embodiment in which each pixel PX includes three transistors and one storage capacitor has been described, but the embodiments of the present application are not limited thereto.

[0080] Figure 3 According to the implementation method Figure 1 An enlarged plan view of area A. Figure 4 According to the implementation method Figure 3 A cross-sectional view taken along line II'.

[0081] Reference Figure 1 , Figure 3 and Figure 4 , the display device 100 according to the embodiment may further include a display part DSP, an encapsulation layer ENC, a first pad electrode PE1, a second pad electrode PE2, a first adhesive layer AL1, and a second adhesive layer AL2.

[0082] In an embodiment, the substrate SUB, the display part DSP, and the encapsulation layer ENC may constitute the display panel DP. The display part DSP may be disposed on the substrate SUB, and the encapsulation layer ENC may surround the display part DSP. A detailed description of components of the display panel DP will be described later.

[0083] In an embodiment, the substrate SUB may include a transparent material or an opaque material. The substrate SUB may be made of a transparent resin substrate. In an embodiment, an example of a transparent resin substrate that can be used as the substrate SUB may be a polyimide substrate. In this case, the polyimide substrate may include a first polyimide layer, a barrier film layer, a second polyimide layer, and / or the like. In another embodiment, the substrate SUB may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, an F-doped quartz substrate, an alkali-lime glass substrate, an alkali-free glass substrate, and the like. These may be used alone or in combination with each other.

[0084] In an embodiment, the first pad electrode PE1 may be arranged in the pad area PA on the substrate SUB. The first pad electrode PE1 may be configured in plurality. In the present embodiment, the first pad electrodes PE1 may be spaced apart from each other in the second direction DR2. The first pad electrode PE1 may include an input pad and an output pad. The input pad may output an input signal, and the output pad may receive an output signal. For example, the first pad electrode PE1 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and / or the like. These may be used alone or in combination with each other.

[0085] In an embodiment, the driving integrated circuit DIC may be arranged on the first pad electrode PE1. Specifically, the driving integrated circuit DIC may be coupled to the first pad electrode PE1 through the first adhesive layer AL1. Accordingly, the driving integrated circuit DIC may be electrically connected to the first pad electrode PE1. For example, the first adhesive layer AL1 may include an anisotropic conductive film. The driving integrated circuit DIC may generate an output signal based on an input signal and output the output signal to an output pad.

[0086] In an embodiment, the second pad electrode PE2 may be arranged in the pad area PA on the substrate SUB. The second pad electrode PE2 may be configured in plurality. In this embodiment, the second pad electrodes PE2 may be spaced apart from each other in the second direction DR2. A portion of the second pad electrode PE2 may be connected to the first pad electrode PE1 by a line, and the remaining portion of the second pad electrode PE2 may be connected to a plurality of pixels (e.g., Figure 1 For example, in an embodiment, the second pad electrode PE2 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and / or the like. These may be used alone or in combination with each other.

[0087] In an embodiment, the circuit board CB may be arranged on the second pad electrode PE2. The circuit board CB may partially overlap the pad area PA. Specifically, the circuit board CB may be coupled to the second pad electrode PE2 through the second adhesive layer AL2. Accordingly, the circuit board CB may be electrically connected to the second pad electrode PE2. For example, the second adhesive layer AL2 may include an anisotropic conductive film.

[0088] In an embodiment, the circuit board CB may include connection pads EP, signal lines SL, a plurality of insulating layers, at least one conductive layer, and first, second, and third protection layers PL1, PL2, and PL3.

[0089] In an embodiment, a plurality of insulating layers may be arranged on the connection pad EP. In an embodiment, the plurality of insulating layers may include a first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3, a fourth insulating layer IL4, and a fifth insulating layer IL5 sequentially arranged on the connection pad EP. However, the embodiments of the present application are not limited thereto, and the number of the plurality of insulating layers may be variously changed.

[0090] In an embodiment, for example, each of the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, the fourth insulating layer IL4, and the fifth insulating layer IL5 may include an inorganic insulating material and / or an organic insulating material, which may be used alone or in combination with each other.

[0091] In an embodiment, the conductive layer may be arranged on the connection pad EP. Specifically, the conductive layer may be arranged between a plurality of insulating layers. In an embodiment, the conductive layer may include a first conductive layer CL1, a second conductive layer CL2, a third conductive layer CL3, a fourth conductive layer CL4, and a fifth conductive layer CL5 arranged sequentially. However, the embodiments of the present application are not limited thereto, and the number of the conductive layers may be variously changed.

[0092] In an embodiment, for example, each of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5 may include copper (Cu). However, the embodiments of the present application are not limited thereto, and each of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5 may include various conductive materials.

[0093] In an embodiment, the connection pad EP may be arranged under the conductive layer. As described above, the circuit board CB may be coupled to the second pad electrode PE2 through the second adhesive layer AL2. Specifically, the connection pad EP of the circuit board CB may be coupled to the second pad electrode PE2 through the second adhesive layer AL2.

[0094] In an embodiment, the signal line SL may be arranged under the conductive layer. In an embodiment, the connection pad EP may be connected to the first conductive layer CL1 through at least one first contact hole CNT1 penetrating the first insulating layer IL1, and the signal line SL may be connected to the first conductive layer CL1 through at least one second contact hole CNT2 penetrating the first insulating layer IL1. Accordingly, the signal line SL may be electrically connected to the connection pad EP through the first conductive layer CL1.

[0095] In an embodiment, each of the connection pads EP and the signal lines SL may be configured in plural. In this case, each of the connection pads EP and the signal lines SL may be spaced apart from each other in the second direction DR2. In addition, the connection pads EP and the signal lines SL may be spaced apart from each other in the first direction DR1.

[0096] In an embodiment, for example, each of the connection pad EP and the signal line SL may include copper (Cu). That is, the connection pad EP and the signal line SL may include the same conductive material as the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5. However, the embodiments of the present application are not limited thereto, and each of the connection pad EP and the signal line SL may include various conductive materials.

[0097] In an embodiment, for example, copper (Cu) may be filled in the first contact hole CNT1 and the second contact hole CNT2. However, the embodiment of the present application is not limited thereto, and other conductive materials may be filled in the first contact hole CNT1 and the second contact hole CNT2.

[0098] In an embodiment, for example, the number of the first contact holes CNT1 may be three, and the number of the second contact hole CNT2 may be one. However, the embodiment of the present application is not limited thereto, and the number of each of the first contact hole CNT1 and the second contact hole CNT2 may be variously changed.

[0099] In an embodiment, since the signal line SL is electrically connected to the connection pad EP through the first conductive layer CL1, the first conductive layer CL1 together with the signal line SL and the connection pad EP may be used as a line to which various signals and voltages are applied. In addition, each of the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5 may constitute a metal ground layer.

[0100] In an embodiment, the first conductive layer CL1 may include a plurality of conductive patterns each extending in a first direction DR1 and spaced apart from each other in a second direction DR2 crossing the first direction DR1. In this embodiment, each of the conductive patterns may overlap the connection pad EP and the signal line SL in a plan view.

[0101] In an embodiment, each of the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5 may have a plate shape. That is, each of the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5 may not include a plurality of conductive patterns.

[0102] In an embodiment, the first protective layer PL1 and the second protective layer PL2 may be arranged below the first insulating layer IL1. In addition, the third protective layer PL3 may be arranged on the fifth conductive layer CL5. Specifically, the first protective layer PL1 may be arranged between the connection pad EP and the signal line SL, and the second protective layer PL2 may be arranged below the first protective layer PL1 and the signal line SL. The first protective layer PL1, the second protective layer PL2, and the third protective layer PL3 may protect the metal layer of the circuit board CB. For example, each of the first protective layer PL1, the second protective layer PL2, and the third protective layer PL3 may include a solder resist. Alternatively, the second protective layer PL2 may be integrated with the first protective layer PL1.

[0103] In an embodiment, when the circuit board CB is connected to the second pad electrode PE2, the first protective layer PL1 of the circuit board CB may overlap at least a portion of the pad area PA. In addition, the lower surface of the first protective layer PL1 may be positioned in the same plane as the lower surface of the connection pad EP. In addition, the thickness TH1 of the connection pad EP in the third direction DR3 may be the same as the thickness TH2 of the first protective layer PL1 in the third direction DR3. That is, no step may be formed between the first protective layer PL1 and the connection pad EP. Accordingly, the compression defect caused by the lifting between the circuit board CB and the display panel DP can be reduced.

[0104] Here, the third direction DR3 may be a direction perpendicular to a plane defined by the first direction DR1 and the second direction DR2.

[0105] Figure 5 , Figure 6 , Figure 7 and Figure 8 It is shown that according to the embodiment Figure 4 A cross-sectional view of an example of the shape of each of the first contact hole and the second contact hole.

[0106] In an embodiment, reference is made to Figure 5 , Figure 6 , Figure 7 and Figure 8 , each of the first contact hole CNT1 and the second contact hole CNT2 may have a polygonal cross-sectional shape.

[0107] like Figure 5 As shown in , in an embodiment, each of the first contact hole CNT1 and the second contact hole CNT2 may have an inverted trapezoidal cross-sectional shape.

[0108] like Figure 6 As shown in , in an embodiment, each of the first contact hole CNT1 and the second contact hole CNT2 may have a trapezoidal cross-sectional shape.

[0109] like Figure 7 As shown in , in an embodiment, each of the first contact hole CNT1 and the second contact hole CNT2 may have a hexagonal cross-sectional shape.

[0110] like Figure 8 As shown in , in an embodiment, each of the first contact hole CNT1 and the second contact hole CNT2 may have a square cross-sectional shape with a side surface recessed toward the center.

[0111] However, the embodiments of the present application are not limited thereto, and each of the first contact hole CNT1 and the second contact hole CNT2 may have various polygonal cross-sectional shapes. In addition, the cross-sectional shapes of the first contact hole CNT1 and the second contact hole CNT2 are not necessarily the same.

[0112] Fig. 9 According to the implementation method Figure 4 An enlarged cross-sectional view of area B.

[0113] For example, Fig. 9 yes Figure 4 FIG. 1 is an enlarged cross-sectional view of a portion of the display panel DP.

[0114] In the embodiments and with reference to Fig. 9 , the display panel DP may include a substrate SUB, a display portion DSP and an encapsulation layer ENC.

[0115] Here, in an embodiment, the display part DSP may include a buffer layer BUF, a transistor TR, a gate insulating layer GI, an interlayer insulating layer ILD, a via insulating layer VIA, a pixel defining layer PDL, and a light emitting element LED. The transistor TR may include an active pattern ACT, a gate electrode GAT, a source electrode SE, and a drain electrode DE, and the light emitting element LED may include an anode electrode ADE, a light emitting layer EL, and a cathode electrode CTE.

[0116] In an embodiment, a buffer layer BUF may be arranged on a substrate SUB. The buffer layer BUF may prevent metal atoms and / or impurities from diffusing from the substrate SUB into the transistor TR. In addition, when the surface of the substrate SUB is uneven, the buffer layer BUF may improve the flatness of the surface of the substrate SUB. For example, the buffer layer BUF may include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, and / or the like. These may be used alone or in combination with each other.

[0117] In an embodiment, the active pattern ACT may be arranged on the buffer layer BUF. The active pattern ACT may include a metal oxide semiconductor, an inorganic semiconductor (eg, amorphous silicon, polycrystalline silicon) and / or an organic semiconductor. The active pattern ACT may include a source region, a drain region, and a channel region positioned between the source region and the drain region.

[0118] In an embodiment, the metal oxide semiconductor may include a binary compound (AB) including indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), and / or the like. x ), ternary compounds (AB x C y ), quaternary compounds (AB x C y Dz ) and / or the like. In an embodiment, for example, the metal oxide semiconductor may include zinc oxide (ZnO x ), gallium oxide (GaO x ), tin oxide (SnO x ), indium oxide (InO x ), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), and / or the like. These may be used alone or in combination with one another.

[0119] In an embodiment, the gate insulating layer GI may be disposed on the buffer layer BUF. The gate insulating layer GI may fully cover the active pattern ACT and may have a substantially flat upper surface without generating steps around the active pattern ACT. Alternatively, the gate insulating layer GI may cover the active pattern ACT and may be disposed along the contour of the active pattern ACT with a uniform thickness. For example, the gate insulating layer GI may include a material such as silicon oxide (SiO x ), silicon nitride (SiN x ), Silicon Carbide (SiC x ), silicon oxynitride (SiO x N y ), silicon carbide oxide (SiO x C y ) and / or the like. These may be used alone or in combination with each other.

[0120] In an embodiment, the gate electrode GAT may be arranged on the gate insulating layer GI. The gate electrode GAT may overlap with the channel region of the active pattern ACT. The gate electrode GAT may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and / or the like. Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), and / or the like. Examples of conductive metal oxides may include indium tin oxide, indium zinc oxide, and / or the like. In addition, examples of metal nitrides may include aluminum nitride (AlN x ), tungsten nitride (WN x ), chromium nitride (CrN x ) and / or the like. These may be used alone or in combination with each other.

[0121] In an embodiment, the interlayer insulating layer ILD may be arranged on the gate insulating layer GI. The interlayer insulating layer ILD may fully cover the gate electrode GAT and may have a substantially flat upper surface without generating steps around the gate electrode GAT. Alternatively, the interlayer insulating layer ILD may cover the gate electrode GAT and may be arranged along the contour of the gate electrode GAT with a uniform thickness. In an embodiment, for example, the interlayer insulating layer ILD may include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide and / or the like. These may be used alone or in combination with each other.

[0122] In an embodiment, the source electrode SE and the drain electrode DE may be arranged on the interlayer insulating layer ILD. The source electrode SE may be connected to the source region of the active pattern ACT through a first contact hole penetrating the gate insulating layer GI and the first portion of the interlayer insulating layer ILD. The drain electrode DE may be connected to the drain region of the active pattern ACT through a second contact hole penetrating the gate insulating layer GI and the second portion of the interlayer insulating layer ILD. For example, each of the source electrode SE and the drain electrode DE may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and / or the like. These may be used alone or in combination with each other.

[0123] Accordingly, in an embodiment, a transistor TR including an active pattern ACT, a gate electrode GAT, a source electrode SE, and a drain electrode DE may be disposed in the display area DA on the substrate SUB.

[0124] In an embodiment, the via insulating layer VIA may be arranged on the interlayer insulating layer ILD. The via insulating layer VIA may fully cover the source electrode SE and the drain electrode DE. The via insulating layer VIA may include an inorganic material and / or an organic material. For example, the via insulating layer VIA may include a phenol resin, a polyacrylate resin, a polyimide resin, a polyamide resin, a siloxane resin, an epoxy resin, and / or the like. These may be used alone or in combination with each other.

[0125] In an embodiment, the anode electrode ADE may be arranged on the through-hole insulating layer VIA. The anode electrode ADE may be connected to the drain electrode DE of the transistor TR through a contact hole penetrating the through-hole insulating layer VIA. In an embodiment, for example, the anode electrode ADE may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material and / or the like. These may be used alone or in combination with each other. In an embodiment, the anode electrode ADE may have a stacked structure including ITO / Ag / ITO.

[0126] In an embodiment, the pixel defining layer PDL may be arranged on the through hole insulating layer VIA. The pixel defining layer PDL may cover the edge of the anode electrode ADE. The pixel defining layer PDL may include an organic material and / or an inorganic material. For example, the pixel defining layer PDL may include an organic material such as an epoxy resin, a silicone resin and / or the like. These may be used alone or in combination with each other. In another embodiment, the pixel defining layer PDL may include an organic material and / or an inorganic material including a light blocking material such as a black pigment, a black dye and / or the like.

[0127] In an implementation, the light emitting layer EL may be disposed on the anode electrode ADE. The light emitting layer EL may include an organic material that emits light of a predetermined color. For example, the light emitting layer EL may include an organic material that emits red light, green light, or blue light.

[0128] In an embodiment, the cathode electrode CTE may be arranged on the light emitting layer EL and the pixel defining layer PDL. For example, the cathode electrode CTE may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material and / or the like. These may be used alone or in combination with each other.

[0129] Accordingly, in an embodiment, a light emitting element LED including the anode electrode ADE, the light emitting layer EL, and the cathode electrode CTE may be arranged in the display area DA on the substrate SUB.

[0130] In an embodiment, the encapsulation layer ENC may be arranged on the cathode electrode CTE. The encapsulation layer ENC may prevent impurities, moisture, air and / or the like from penetrating into the light emitting element LED from the outside. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer. For example, the inorganic layer may include silicon oxide, silicon nitride, silicon oxynitride and / or the like. These may be used alone or in combination with each other. The organic layer may include a polymer curing material such as polyacrylate and / or the like.

[0131] Fig.10 According to the implementation method Figure 1 An enlarged plan view of another example of area A. Fig.11 is a diagram showing the Fig.10 A cross-sectional view of an example of a cross-section taken along line II-II'. Fig.12 is a diagram showing the Fig.10 A cross-sectional view of another example of a cross section taken along line II-II'.

[0132] In the following, the references will be omitted or simplified. Figure 3 and Figure 4 The description of the display device 100 described above is repeated.

[0133] Reference Figure 1 , Fig.10 , Fig.11 and Fig.12 , the display device 100 according to the embodiment may include a substrate SUB, a display part DSP, an encapsulation layer ENC, a driving integrated circuit DIC, a circuit board CB1, a first pad electrode PE1, a second pad electrode PE2, a first adhesive layer AL1, and a second adhesive layer AL2.

[0134] In an embodiment, the circuit board CB1 may include connection pads EP, signal lines SL, a plurality of insulating layers, at least one conductive layer, and first, second, and third protection layers PL1, PL2, and PL3.

[0135] In an embodiment, the plurality of insulating layers may include a first insulating layer IL1 , a second insulating layer IL2 , a third insulating layer IL3 , a fourth insulating layer IL4 , and a fifth insulating layer IL5 sequentially disposed on the connection pad EP.

[0136] In an embodiment, the conductive layer may include a first conductive layer CL1, a second conductive layer CL2, a third conductive layer CL3, a fourth conductive layer CL4, and a fifth conductive layer CL5 arranged sequentially. For example, each of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5 may include copper (Cu).

[0137] In an implementation, the connection pad EP may be disposed under the conductive layer. The connection pad EP of the circuit board CB1 may be coupled to the second pad electrode PE2 through the second adhesive layer AL2.

[0138] In an embodiment, the signal line SL may be arranged under the conductive layer. In an embodiment, the connection pad EP may be connected to the first conductive layer CL1 through at least one first contact hole CNT1 penetrating the first insulating layer IL1, and the signal line SL may be connected to the first conductive layer CL1 through at least one second contact hole CNT2 penetrating the first insulating layer IL1. In addition, the first conductive layer CL1 may be connected to the second conductive layer CL2 through at least one third contact hole CNT3 and at least one fourth contact hole CNT4 penetrating the second insulating layer IL2. Accordingly, the signal line SL may be electrically connected to the connection pad EP through the first conductive layer CL1 and the second conductive layer CL2.

[0139] In an embodiment, since the signal line SL is electrically connected to the connection pad EP through the first conductive layer CL1 and the second conductive layer CL2, the first conductive layer CL1 and the second conductive layer CL2 together with the signal line SL and the connection pad EP may be used as a line to which various signals and voltages are applied. In addition, each of the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5 may constitute a metal ground layer.

[0140] In an embodiment, each of the first and second conductive layers CL1 and CL2 may include a plurality of conductive patterns each extending in a first direction DR1 and spaced apart from each other in a second direction DR2 crossing the first direction DR1. In an embodiment, each of the conductive patterns may overlap the connection pad EP and the signal line SL in a plan view.

[0141] In an embodiment, each of the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5 may have a plate shape. That is, each of the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5 may not include a plurality of conductive patterns.

[0142] In an embodiment, each of the connection pads EP and the signal lines SL may be configured in plural. In an embodiment, each of the connection pads EP and the signal lines SL may be arranged to be spaced apart from each other in the second direction DR2. In addition, the connection pads EP and the signal lines SL may be spaced apart from each other in the first direction DR1.

[0143] In an embodiment, for example, each of the connection pad EP and the signal line SL may include copper (Cu). That is, the connection pad EP and the signal line SL may include the same conductive material as the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5.

[0144] In an embodiment, for example, copper (Cu) may be filled in the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4. However, the embodiment of the present application is not limited thereto, and other conductive materials may be filled in the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4.

[0145] In an embodiment, each of the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4 may have a polygonal cross-sectional shape. For example, each of the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4 may have an inverted trapezoidal cross-sectional shape, a trapezoidal cross-sectional shape, a hexagonal cross-sectional shape, or a square cross-sectional shape with a side surface recessed toward the center.

[0146] In an embodiment, for example, the number of each of the first contact hole CNT1 and the third contact hole CNT3 may be three, and the number of each of the second contact hole CNT2 and the fourth contact hole CNT4 may be one. However, the embodiment of the present application is not limited thereto, and the number of each of the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4 may be variously changed.

[0147] In an embodiment, the positions of the third contact hole CNT3 and the fourth contact hole CNT4 may be changed in various ways. Fig.11 As shown in , the third contact hole CNT3 may overlap with the first contact hole CNT1 in a plan view, and the fourth contact hole CNT4 may overlap with the second contact hole CNT2 in a plan view. Fig.12 As shown in , the third contact hole CNT3 may not overlap with the first contact hole CNT1 in a plan view.

[0148] In an embodiment, the first protective layer PL1 and the second protective layer PL2 may be arranged below the first insulating layer IL1. In addition, the third protective layer PL3 may be arranged on the fifth conductive layer CL5. Specifically, the first protective layer PL1 may be arranged between the connection pad EP and the signal line SL, and the second protective layer PL2 may be arranged below the first protective layer PL1 and the signal line SL. In an embodiment, for example, each of the first protective layer PL1, the second protective layer PL2, and the third protective layer PL3 may include a solder resist. Alternatively, the second protective layer PL2 may be integrated with the first protective layer PL1.

[0149] In an embodiment, when the circuit board CB1 is connected to the second pad electrode PE2, the first protective layer PL1 of the circuit board CB1 may overlap at least a portion of the pad area PA. In addition, the lower surface of the first protective layer PL1 may be positioned in the same plane as the lower surface of the connection pad EP. In addition, the thickness TH1 of the connection pad EP in the third direction DR3 may be the same as the thickness TH2 of the first protective layer PL1 in the third direction DR3. That is, no step may be formed between the first protective layer PL1 and the connection pad EP. Accordingly, the compression defect caused by the lifting between the circuit board CB1 and the display panel DP can be reduced.

[0150] Fig.13 According to the implementation method Figure 1 An enlarged plan view of another example of area A. Fig.14 is a diagram showing the Fig.13 A cross-sectional view of an example of a cross-section taken along line III-III'.

[0151] Fig.15 is a diagram showing the Fig.13 A cross-sectional view of another example of a cross section taken along line III-III'.

[0152] In the following, the references will be omitted or simplified. Figure 3 and Figure 4 The description of the display device 100 described above is repeated.

[0153] Reference Figure 1 , Fig.13 , Fig.14 and Fig.15 , the display device 100 according to the embodiment may include a substrate SUB, a display part DSP, an encapsulation layer ENC, a driving integrated circuit DIC, a circuit board CB2, a first pad electrode PE1, a second pad electrode PE2, a first adhesive layer AL1, and a second adhesive layer AL2.

[0154] In an embodiment, the circuit board CB2 may include connection pads EP, signal lines SL, a plurality of insulating layers, at least one conductive layer, and first, second, and third protection layers PL1, PL2, and PL3.

[0155] In an embodiment, the plurality of insulating layers may include a first insulating layer IL1 , a second insulating layer IL2 , a third insulating layer IL3 , a fourth insulating layer IL4 , and a fifth insulating layer IL5 sequentially disposed on the connection pad EP.

[0156] In an embodiment, the conductive layer may include a first conductive layer CL1, a second conductive layer CL2, a third conductive layer CL3, a fourth conductive layer CL4, and a fifth conductive layer CL5 arranged sequentially. For example, each of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5 may include copper (Cu).

[0157] In an implementation, the connection pads EP may be disposed under the conductive layer. The connection pads EP of the circuit board CB2 may be coupled to the second pad electrode PE2 through the second adhesive layer AL2.

[0158] In an embodiment, the signal line SL may be arranged under the conductive layer. In an embodiment, the connection pad EP may be connected to the first conductive layer CL1 through at least one first contact hole CNT1 penetrating the first insulating layer IL1, and the signal line SL may be connected to the first conductive layer CL1 through at least one second contact hole CNT2 penetrating the first insulating layer IL1. In addition, the first conductive layer CL1 may be connected to the second conductive layer CL2 through at least one third contact hole CNT3 and at least one fourth contact hole CNT4 penetrating the second insulating layer IL2. In addition, the second conductive layer CL2 may be connected to the third conductive layer CL3 through at least one fifth contact hole CNT5 and at least one sixth contact hole CNT6 penetrating the third insulating layer IL3. Accordingly, the signal line SL may be electrically connected to the connection pad EP through the first conductive layer CL1, the second conductive layer CL2, and the third conductive layer CL3.

[0159] In an embodiment, since the signal line SL is electrically connected to the connection pad EP through the first conductive layer CL1, the second conductive layer CL2, and the third conductive layer CL3, the first conductive layer CL1, the second conductive layer CL2, and the third conductive layer CL3 together with the signal line SL and the connection pad EP may be used as a line to which various signals and voltages are applied. In addition, each of the fourth conductive layer CL4 and the fifth conductive layer CL5 may constitute a metal ground layer.

[0160] In an embodiment, each of the first conductive layer CL1, the second conductive layer CL2, and the third conductive layer CL3 may include a plurality of conductive patterns each extending in a first direction DR1 and spaced apart from each other in a second direction DR2 crossing the first direction DR1. In this case, each of the conductive patterns may overlap the connection pad EP and the signal line SL in a plan view.

[0161] In an embodiment, each of the fourth conductive layer CL4 and the fifth conductive layer CL5 may have a plate shape. That is, each of the fourth conductive layer CL4 and the fifth conductive layer CL5 may not include a plurality of conductive patterns.

[0162] In an embodiment, each of the fourth conductive layer CL4 and the fifth conductive layer CL5 may have a plate shape. That is, each of the fourth conductive layer CL4 and the fifth conductive layer CL5 may not include a plurality of conductive patterns.

[0163] In an embodiment, each of the connection pads EP and the signal lines SL may be configured in plural. In an embodiment, each of the connection pads EP and the signal lines SL may be arranged to be spaced apart from each other in the second direction DR2. In addition, the connection pads EP and the signal lines SL may be spaced apart from each other in the first direction DR1.

[0164] In an embodiment, for example, each of the connection pad EP and the signal line SL may include copper (Cu). That is, the connection pad EP and the signal line SL may include the same conductive material as the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5.

[0165] In an embodiment, for example, copper (Cu) may be filled in the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, the fourth contact hole CNT4, the fifth contact hole CNT5, and the sixth contact hole CNT6. However, the embodiments of the present application are not limited thereto, and other conductive materials may be filled in the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, the fourth contact hole CNT4, the fifth contact hole CNT5, and the sixth contact hole CNT6.

[0166] In an embodiment, each of the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, the fourth contact hole CNT4, the fifth contact hole CNT5, and the sixth contact hole CNT6 may have a polygonal cross-sectional shape. For example, each of the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, the fourth contact hole CNT4, the fifth contact hole CNT5, and the sixth contact hole CNT6 may have an inverted trapezoidal cross-sectional shape, a trapezoidal cross-sectional shape, a hexagonal cross-sectional shape, or a square cross-sectional shape with a side surface recessed toward the center.

[0167] In an embodiment, for example, the number of each of the first contact hole CNT1, the third contact hole CNT3, and the fifth contact hole CNT5 may be three, and the number of each of the second contact hole CNT2, the fourth contact hole CNT4, and the sixth contact hole CNT6 may be one. However, the embodiment of the present application is not limited thereto, and the number of each of the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, the fourth contact hole CNT4, the fifth contact hole CNT5, and the sixth contact hole CNT6 may be variously changed.

[0168] In an embodiment, the positions of the third contact hole CNT3, the fourth contact hole CNT4, the fifth contact hole CNT5, and the sixth contact hole CNT6 may be variously changed. Fig.14 As shown in , the third contact hole CNT3 and the fifth contact hole CNT5 may overlap with the first contact hole CNT1 in a plan view, and the fourth contact hole CNT4 and the sixth contact hole CNT6 may overlap with the second contact hole CNT2 in a plan view. Alternatively, as Fig.15 As shown in , the third contact hole CNT3 and the fifth contact hole CNT5 may not overlap with the first contact hole CNT1 in a plan view.

[0169] In an embodiment, the first protective layer PL1 and the second protective layer PL2 may be arranged below the first insulating layer IL1. In addition, the third protective layer PL3 may be arranged on the fifth conductive layer CL5. Specifically, the first protective layer PL1 may be arranged between the connection pad EP and the signal line SL, and the second protective layer PL2 may be arranged below the first protective layer PL1 and the signal line SL. For example, each of the first protective layer PL1, the second protective layer PL2, and the third protective layer PL3 may include a solder resist. Alternatively, the second protective layer PL2 may be integrated with the first protective layer PL1.

[0170] In an embodiment, when the circuit board CB2 is connected to the second pad electrode PE2, the first protective layer PL1 of the circuit board CB2 may overlap at least a portion of the pad area PA. In addition, the lower surface of the first protective layer PL1 may be positioned in the same plane as the lower surface of the connection pad EP. In addition, the thickness TH1 of the connection pad EP in the third direction DR3 may be the same as the thickness TH2 of the first protective layer PL1 in the third direction DR3. That is, no step may be formed between the first protective layer PL1 and the connection pad EP. Accordingly, the compression defect caused by the lifting between the circuit board CB2 and the display panel DP can be reduced.

[0171] However, despite the reference Figure 3 , Figure 4 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 and Fig.15 In the embodiment, the electrical connection of the connection pad EP and the signal line SL through one, two or three conductive layers has been described as an example, but the embodiment of the present application is not limited thereto. In the embodiment, for example, the connection pad EP and the signal line SL may be electrically connected through four or more conductive layers.

[0172] Fig.16 According to the implementation method Figure 1 An enlarged plan view of another example of area A. Fig.17 is a diagram showing the Fig.16 A cross-sectional view of an example of a cross-section taken along line IV-IV'.

[0173] Fig.18 is a diagram showing the Fig.16 A cross-sectional view of another example of a cross section taken along line IV-IV'.

[0174] In the following, the references will be omitted or simplified. Figure 3 and Figure 4 The description of the display device 100 described above is repeated.

[0175] Reference Figure 1 , Fig.16 , Fig.17 and Fig.18 , the display device 100 according to the embodiment may include a substrate SUB, a display part DSP, an encapsulation layer ENC, a driving integrated circuit DIC, a circuit board CB3, a first pad electrode PE1, a second pad electrode PE2, a first adhesive layer AL1, and a second adhesive layer AL2.

[0176] In an embodiment, a plurality of insulating layers may be disposed on the connection pad EP. In an embodiment, the plurality of insulating layers may include first, second, third, fourth, and fifth insulating layers IL1, IL2, IL3, IL4, and IL5 sequentially disposed on the connection pad EP.

[0177] In an embodiment, the conductive layer may be arranged on the connection pad EP. In an embodiment, the conductive layer may include a first conductive layer CL1, a second conductive layer CL2, a third conductive layer CL3, a fourth conductive layer CL4, and a fifth conductive layer CL5 arranged sequentially. For example, each of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5 may include copper (Cu).

[0178] In an implementation, the connection pads EP may be disposed under the conductive layer. The connection pads EP of the circuit board CB3 may be coupled to the second pad electrode PE2 through the second adhesive layer AL2.

[0179] In an embodiment, the signal line SL may be arranged under the conductive layer. The signal line SL may not overlap with the connection pad EP in a plan view. In an embodiment, the connection pad EP may be integrated with the signal line SL. Accordingly, the signal line SL may be electrically connected to the connection pad EP.

[0180] In an embodiment, the signal line SL and the connection pad EP may serve as a line to which various signals and voltages are applied. In addition, each of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5 may constitute a metal ground layer.

[0181] In an embodiment, each of the connection pads EP and the signal lines SL may be configured in plural. In an embodiment, each of the connection pads EP and the signal lines SL may be arranged to be spaced apart from each other in the second direction DR2.

[0182] In an embodiment, for example, each of the connection pad EP and the signal line SL may include copper (Cu). That is, the connection pad EP and the signal line SL may include the same conductive material as the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5.

[0183] In an embodiment, each of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5 may have a plate shape. That is, each of the first conductive layer CL1, the second conductive layer CL2, the third conductive layer CL3, the fourth conductive layer CL4, and the fifth conductive layer CL5 may not include a plurality of conductive patterns.

[0184] like Fig.17 As shown in FIG. 1 , in an embodiment, the protection layer PL may be disposed under the signal line SL. For example, the protection layer PL may include a solder resist.

[0185] In an embodiment, when the circuit board CB3 is connected to the second pad electrode PE2, the protective layer PL of the circuit board CB3 may overlap at least a portion of the pad area PA. In addition, the lower surface of the protective layer PL may be positioned in the same plane as the lower surface of the connecting pad EP. In addition, the thickness TH4 of the signal line SL in the third direction DR3 may be less than the thickness TH3 of the connecting pad EP in the third direction DR3. That is, no step may be formed between the protective layer PL and the connecting pad EP. Accordingly, the compression defect caused by the lifting between the circuit board CB3 and the display panel DP can be reduced.

[0186] like Fig.18 As shown in , in another embodiment, the first protection layer PL1 and the second protection layer PL2 may be disposed under the signal line SL. Specifically, the second protection layer PL2 may be disposed under the first protection layer PL1. For example, each of the first protection layer PL1 and the second protection layer PL2 may include a solder resist.

[0187] In another embodiment, when the circuit board CB3 is connected to the second pad electrode PE2, the first protective layer PL1 of the circuit board CB3 may overlap with at least a portion of the pad area PA. In addition, the lower surface of the first protective layer PL1 may be positioned in the same plane as the lower surface of the connecting pad EP. In addition, the thickness TH4' of the portion of the signal line SL overlapping with the first protective layer PL1 in the third direction DR3 may be less than the thickness TH3' of the connecting pad EP in the third direction DR3. That is, no step may be formed between the first protective layer PL1 and the connecting pad EP. Accordingly, the compression defect caused by the lifting between the circuit board CB3 and the display panel DP can be reduced.

[0188] Fig.19 The present invention includes Figure 1 A block diagram of an electronic device of a display device.

[0189] Fig. 20 It is shown that according to the embodiment Fig.19 A perspective view of an example in which the electronic device is implemented as a television set.

[0190] Fig.21 It is shown that according to the embodiment Fig.19 A perspective view of an example in which the electronic device is implemented as a smart phone.

[0191] Reference Fig.19 , Fig. 20 and Fig.21 In an embodiment, the electronic device 200 may include a processor 210, a memory device 220, a storage device 230, an input / output (I / O) device 240, a power supply 250, and a display device 260. In an embodiment, the display device 260 may correspond to the reference Figures 1 to 18 The electronic device 200 may also include several ports capable of communicating with a video card, a sound card, a memory card, a USB device, and / or the like.

[0192] In an embodiment, if Fig. 20 As shown in , the electronic device 200 may be implemented as a television. Fig.21 As shown in , the electronic device 200 may be implemented as a smart phone. However, the electronic device 200 is not limited thereto, and for example, the electronic device 200 may be implemented as a mobile phone, a video phone, a smart tablet, a smart watch, a tablet PC, a vehicle navigation device, a computer monitor, a laptop computer, a head mounted display (HMD), and / or the like.

[0193] In an embodiment, the processor 210 may perform certain calculations or tasks. In an embodiment, the processor 210 may be a microprocessor, a central processing unit (CPU), an application processor (AP), and / or the like. The processor 210 may be connected to other components via an address bus, a control bus, a data bus, and / or the like. The processor 210 may also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0194] In an embodiment, the memory device 220 may store data required for the operation of the electronic device 200. For example, the memory device 220 may include a non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, and / or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device, and / or the like.

[0195] In implementations, storage device 230 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, and / or the like.

[0196] In implementations, the input / output devices 240 may include input devices such as a keyboard, keypad, touch pad, touch screen, mouse, and / or the like and output devices such as a speaker, printer, and / or the like.

[0197] In an embodiment, the power supply 250 may supply power required for the operation of the electronic device 200. The display device 260 may be connected to other components through a bus and / or other communication links. In an embodiment, the display device 260 may be included in the input / output device 240.

[0198] The present application can be applied to various display devices. In an embodiment, for example, the present application can be applied to various display devices, such as display devices for vehicles, ships and aircraft, portable communication devices, display devices for exhibitions or information dissemination, medical display devices and / or the like.

[0199] The foregoing is an explanation of the embodiments and will not be construed as limiting them. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications are possible in the embodiments without departing substantially from the teachings and advantages of the present application. Accordingly, all such modifications are intended to be included within the scope of the present application. Therefore, it will be understood that the foregoing is an explanation of various embodiments and will not be construed as being limited to the specific embodiments disclosed, and it will be understood that modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. In addition, embodiments or portions of embodiments may be combined in whole or in part without departing from the scope of the present application.

Claims

1. A circuit board, It is characterized in that include: Multiple insulation layers; at least one conductive layer, the at least one conductive layer being disposed between the plurality of insulating layers; a connection pad, the connection pad being arranged below the at least one conductive layer; a signal line disposed below the at least one conductive layer and electrically connected to the connection pad; as well as A protective layer is disposed below the at least one conductive layer and has a lower surface positioned in the same plane as a lower surface of the connection pad.

2. The circuit board according to claim 1, It is characterized in that The thickness of the protection layer is equal to the thickness of the connection pad.

3. The circuit board according to claim 1, It is characterized in that The at least one conductive layer comprises: a first conductive layer disposed on the connection pad and the signal line; and A second conductive layer is disposed on the first conductive layer.

4. The circuit board as claimed in claim 3, It is characterized in that The plurality of insulating layers include a first insulating layer disposed between the first conductive layer and the connection pad, The connection pad is connected to the first conductive layer through at least one first contact hole penetrating the first insulating layer, and The signal line is connected to the first conductive layer through at least one second contact hole penetrating the first insulating layer.

5. The circuit board as claimed in claim 4, It is characterized in that The first conductive layer includes a plurality of conductive patterns each extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, and Wherein, the second conductive layer has a plate shape.

6. The circuit board as claimed in claim 5, It is characterized in that The connection pad and the signal line are spaced apart from each other in the first direction, and Wherein, each of the plurality of conductive patterns overlaps the connection pad and the signal line in a plan view.

7. The circuit board according to claim 1, It is characterized in that The at least one conductive layer comprises: a first conductive layer, the first conductive layer being arranged on the connection pad and the signal line; a second conductive layer disposed on the first conductive layer; and A third conductive layer is disposed on the second conductive layer.

8. The circuit board as claimed in claim 7, It is characterized in that The plurality of insulating layers include a first insulating layer disposed between the first conductive layer and the connection pad and a second insulating layer disposed on the first insulating layer, wherein the connection pad is connected to the first conductive layer through at least one first contact hole penetrating the first insulating layer, The signal line is connected to the first conductive layer through at least one second contact hole penetrating the first insulating layer, and The second conductive layer is connected to the first conductive layer through at least one third contact hole and at least one fourth contact hole penetrating the second insulating layer.

9. The circuit board as claimed in claim 8, It is characterized in that Each of the first conductive layer and the second conductive layer includes a plurality of conductive patterns each extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, and Wherein, the third conductive layer has a plate shape.

10. The circuit board according to claim 1, It is characterized in that The signal line is arranged on the protection layer, and wherein the signal line is integrated with the connection pad.

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