Array substrate, display panel and electronic equipment

Abstract

The embodiment of the utility model provides an array substrate, a display panel and electronic equipment, and relates to the technical field of display, the array substrate comprises a substrate, a dam structure and an electrostatic discharge wire, and the substrate comprises a first functional layer; the dam structure is located on one side of the substrate; and the electrostatic discharge wire is electrically connected with the first functional layer through the groove structure adjacent to the dam structure. According to the display panel, by arranging the electrostatic discharge routing which is electrically connected with the first functional layer through the groove structure adjacent to the dam structure, an electrostatic export channel can be provided for the first functional layer, so that the static electricity of the first functional layer can be exported in time, the problem of static electricity accumulation on the first functional layer at the display edge of the display panel is not prone to occurring, and the display quality is improved. Therefore, the problem of uneven edge display of the display panel can be improved, and finally the display quality of the display panel is better.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and an electronic device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display panels.

[0003] However, in the related art, the edge of the display panel is unevenly displayed, thereby affecting the display quality of the display panel. Utility Model Content

[0004] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides an array substrate, the array substrate comprising:

[0005] a substrate, the substrate comprising a first functional layer;

[0006] A dam structure and a groove structure located on one side of the substrate;

[0007] The electrostatic release wiring is electrically connected to the first functional layer via a groove structure adjacent to the dam structure.

[0008] In some possible implementations, the array substrate includes a display area and a non-display area surrounding at least a portion of the display area; the dam structure is located in the non-display area;

[0009] And / or, the array substrate includes a border region, and the dam structure is located in the border region;

[0010] And / or, the dam structure includes at least one inorganic insulating layer and / or at least one organic insulating layer stacked along the thickness direction of the array substrate;

[0011] And / or, the array substrate further includes a first voltage line and a plurality of pixel circuits, the first voltage line is electrically connected to the pixel circuits, and the first voltage line is multiplexed as an electrostatic release line;

[0012] and / or, the embankment structure is a cracked embankment;

[0013] And / or, the substrate further comprises at least one organic layer and at least one inorganic layer stacked along the thickness direction of the array substrate, and the first functional layer is located between the organic layer and the inorganic layer of the substrate;

[0014] And / or, the first functional layer includes an amorphous silicon layer, an indium tin oxide layer or a metal layer.

[0015] In some possible implementations, along a direction away from the substrate, the array substrate further includes a first conductive layer, a second conductive layer, and a third conductive layer stacked in sequence;

[0016] The third conductive layer includes an electrostatic discharge trace;

[0017] and / or, in a direction away from the substrate, the dam structure includes a buffer material layer, a gate insulating material layer, a capacitor dielectric material layer and an interlayer insulating material layer stacked in sequence,

[0018] The electrostatic discharge wiring sequentially extends through the side of the interlayer insulating material layer, the side of the capacitor dielectric material layer, the side of the gate insulating material layer and the side of the buffer material layer to be electrically connected to the first functional layer;

[0019] And / or, the array substrate further comprises a first planarization layer located on a side of the third conductive layer away from the substrate, and the first planarization layer fills the groove structure;

[0020] And / or, the first conductive layer includes a gate layer, the second conductive layer includes a capacitor plate layer, and the third conductive layer includes a first source and drain layer.

[0021] In some possible implementations, along a direction away from the substrate, the array substrate further includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer which are stacked in sequence;

[0022] The fourth conductive layer includes an electrostatic discharge trace;

[0023] and / or, in a direction away from the substrate, the dam structure includes a buffer material layer, a gate insulating material layer, a capacitor dielectric material layer, an interlayer insulating material layer and a first planarizing material layer stacked in sequence,

[0024] The electrostatic discharge wiring sequentially extends through the side surface of the first planarization material layer, the side surface of the interlayer insulating material layer, the side surface of the capacitor dielectric material layer, the side surface of the gate insulating material layer and the side surface of the buffer material layer to be electrically connected to the first functional layer;

[0025] And / or, the array substrate further comprises a second planarization layer located on a side of the fourth conductive layer away from the substrate, and the second planarization layer fills the groove structure;

[0026] And / or, the first conductive layer includes a gate layer, the second conductive layer includes a capacitor plate layer, the third conductive layer includes a first source and drain electrode layer, and the fourth conductive layer includes a second source and drain electrode layer.

[0027] In some possible implementations, the array substrate includes a display area and a non-display area; the dam structure is located in the non-display area;

[0028] There are multiple dam structures, and the multiple dam structures are arranged along the direction from the display area to the non-display area. A groove structure is arranged on at least one side of the dam structure, and a groove structure is arranged between the multiple dam structures. The electrostatic release wiring is electrically connected to the first functional layer through at least the groove structure adjacent to the dam structure closest to the display area.

[0029] In some possible implementations, the electrostatic release trace is electrically connected to the first functional layer via a groove structure adjacent to one or more dam structures.

[0030] In some possible implementations, the substrate further includes: a first organic layer, a first barrier layer located on one side of the first organic layer, a second organic layer located on a side of the first barrier layer away from the first organic layer, and a second barrier layer located on a side of the second organic layer away from the first organic layer, the first functional layer is located between the second organic layer and the second barrier layer; the dam structure and the electrostatic release wiring are located on a side of the first functional layer away from the first organic layer;

[0031] and / or, the substrate is a flexible substrate;

[0032] And / or, the groove structure penetrates the second barrier layer and the first functional layer.

[0033] In some possible implementations, the first functional layer includes an amorphous material layer, a metal oxide layer or a metal layer;

[0034] and / or, the electrostatic discharge routing is a DC voltage routing;

[0035] And / or, the electrostatic release wiring includes at least one of a power supply voltage wiring, a common voltage wiring, an initialization voltage wiring and a touch wiring.

[0036] In some possible implementations, the present application further provides a display panel, the display panel comprising:

[0037] The array substrate in this application;

[0038] The packaging dam is located at one side of the array substrate, and the dam structure in the array substrate is located at a side of the packaging dam away from the display area of ​​the display panel.

[0039] In some possible implementations, the present application further provides an electronic device, and the electronic device includes the display panel in the present application.

[0040] Compared with the prior art, this application has the following beneficial effects:

[0041] The present application provides an array substrate, a display panel, and an electronic device. By setting an electrostatic release line electrically connected to the first functional layer through a groove structure adjacent to the dam structure, a static electricity discharge channel can be provided for the first functional layer, so that the static electricity of the first functional layer can be discharged in time. The first functional layer at the display edge of the display panel is not prone to static electricity accumulation, which can improve the problem of uneven display at the edge of the display panel, and ultimately improve the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 A cross-sectional schematic diagram of an array substrate in the related art provided in an embodiment of the present application;

[0044] Figure 2 A schematic cross-sectional view of an array substrate provided in an embodiment of the present application;

[0045] Figure 3 The array substrate provided in the embodiment of the present application includes a cross-sectional schematic diagram of three conductive layers;

[0046] Figure 4 The array substrate provided in the embodiment of the present application includes a cross-sectional schematic diagram of three conductive layers and a first planarization layer;

[0047] Figure 5 A schematic cross-sectional view of four conductive layers provided in an embodiment of the present application;

[0048] Figure 6 A schematic cross-sectional view of four conductive layers and a second planarization layer provided in an embodiment of the present application;

[0049] Figure 7 A schematic cross-sectional view of an array substrate provided in an embodiment of the present application including three conductive layers and an electrostatic discharge wiring extending through the sides of a plurality of dam structures to be electrically connected to the first functional layer;

[0050] Figure 8 A schematic cross-sectional view of an array substrate provided in an embodiment of the present application comprising four conductive layers and an electrostatic discharge wiring extending through the sides of a plurality of dam structures to be electrically connected to the first functional layer;

[0051] Fig. 9 A schematic cross-sectional view of an electrostatic discharge wiring provided in an embodiment of the present application extending to a side of the first functional layer away from the substrate;

[0052] Fig.10 A schematic diagram of a pixel circuit provided in an embodiment of the present application.

[0053] Figure numerals: 1. substrate; 101. first functional layer; 102. second blocking layer; 103. second organic layer; 104. first blocking layer; 105. first organic layer; 2. crack dam; 3. dam structure; 4. electrostatic release routing; 5. buffer layer; 51. buffer material layer; 6. gate insulating layer; 61. gate insulating material layer; 7. semiconductor layer; 8. capacitor dielectric layer; 81. capacitor dielectric material layer; 9. interlayer insulating layer; 91. interlayer insulating material layer; 10. first conductive layer; 11. third conductive layer; 12. second conductive layer; 13. first planarization layer; 131. first planarization material layer; 14. fourth conductive layer; 15. second planarization layer; 16. groove structure. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0055] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0056] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0057] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the utility model product is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0058] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0059] See also Figure 1 The array substrate in the related art includes a substrate 1, a crack dam 2 located on one side of the substrate 1, and the substrate 1 includes a first functional layer 101. The first functional layer 101 can improve the afterimage phenomenon of the display panel corresponding to the array substrate. For example, the first functional layer 101 can be an amorphous silicon layer. However, when etching to form the crack dam 2, a large amount of static electricity in the dry etching equipment of the crack dam 2 remains in the first functional layer 101. After high-temperature reliability verification, the static electricity will be transmitted to the edge of the display area of ​​the display panel through the first functional layer 101, thereby causing the problem of uneven display at the edge of the display panel corresponding to the array substrate, thereby affecting the display quality of the display panel.

[0060] In view of this, the present embodiment provides a solution that can improve the uneven display at the edge of the display panel corresponding to the array substrate. The solution provided by the present embodiment is described in detail below.

[0061] See also Figure 2 This embodiment provides an array substrate, which includes a substrate 1, a dam structure 3 and an electrostatic release wiring 4.

[0062] The substrate 1 includes a first functional layer 101 , and the dam structure 3 is located on one side of the substrate 1 ; the electrostatic discharge trace 4 is electrically connected to the first functional layer 101 via a groove structure 16 adjacent to the dam structure 3 .

[0063] See also Figure 3 The array substrate includes a display area AA and a non-display area AB surrounding at least a portion of the display area AA; the dam structure 3 is located in the non-display area AB; optionally, the array substrate includes a frame area, and the dam structure 3 is located in the frame area.

[0064] The dam structure 3 and the groove structure 16 are arranged adjacent to each other, and the groove structure 16 can be used to disperse the stress generated when cutting the array substrate, and / or block the path of the cracks generated when cutting the array substrate to the display area AA. The electrostatic discharge wiring 4 is electrically connected to the first functional layer 101 through at least one groove structure 16 adjacent to the dam structure 3. The electrostatic discharge wiring 4 is electrically connected to the first functional layer 101 through the groove structure 16 adjacent to the dam structure 3, and the electrostatic discharge wiring 4 has the function of conducting static electricity. After the high-temperature reliability is verified, the static electricity remaining in the first functional layer 101 by the dry etching equipment etching the dam structure 3 will be promptly exported through the electrostatic discharge wiring 4. In this way, it is not easy to generate the problem of static electricity accumulation in the first functional layer 101 at the edge of the display area AA of the display panel corresponding to the array substrate, thereby improving the problem of uneven display at the display edge of the display panel. In the adjacently arranged dam structure 3 and groove structure 16, the side wall of the dam structure 3 close to the groove structure 16 and the side wall of the groove structure 16 close to the dam structure 3 are the same side wall or share the same side wall.

[0065] Based on the above design, in this embodiment, the electrostatic release line 4 electrically connected to the first functional layer 101 through the groove structure 16 adjacent to the dam structure 3 can provide an electrostatic discharge channel for the first functional layer 101, so that the static electricity of the first functional layer 101 can be discharged in time. The first functional layer 101 at the display edge of the display panel is not prone to static electricity accumulation, which can improve the problem of uneven display at the edge of the display panel, and ultimately improve the display quality of the display panel.

[0066] For some possible implementations, see Figure 3 , along the direction away from the substrate 1 , the array substrate further includes a first conductive layer 10 , a second conductive layer 12 and a third conductive layer 11 which are stacked in sequence; the third conductive layer 11 includes an electrostatic discharge trace 4 .

[0067] The array substrate further includes a semiconductor layer 7, the semiconductor layer 7 includes a source region, a drain region and a channel region, a first conductive layer 10 includes a gate layer and a first capacitor plate, the gate layer includes a gate, a second conductive layer 12 includes a second capacitor plate, the first capacitor plate and the second capacitor plate form a capacitor, a third conductive layer 11 includes a first source-drain electrode layer, the source-drain electrode layer includes a drain electrode and a source electrode, the drain electrode is electrically connected to the drain region, the source electrode is electrically connected to the source region, and the gate, the source electrode and the drain electrode form a switching device, i.e., a transistor. The first conductive layer 10, the second conductive layer 12 and the third conductive layer 11 may include a metal layer or an indium tin oxide layer (ITO).

[0068] After the dam structure 3 is formed by etching, a groove structure 16 will be formed between the dam structures 3. When the third conductive layer 11 is formed, part of the third conductive layer 11 will be deposited in the groove structure between the dam structures 3. After etching, the third conductive layer 11 will form an electrostatic release wiring 4. The electrostatic release wiring 4 will be electrically connected to the first functional layer 101 through the groove structure 16 adjacent to the dam structure 3. The electrostatic release wiring 4 will extend from the side of the dam structure 3 to be electrically connected to the first functional layer 101. In this way, the electrostatic release wiring 4 can be formed when the third conductive layer 11 is formed, and there is no need to set the electrostatic release wiring 4 through a special process, thereby simplifying the process and reducing the cost of forming the electrostatic release wiring 4.

[0069] In some possible implementations, the dam structure 3 includes at least one inorganic insulating layer and / or at least one organic insulating layer stacked along the thickness direction of the array substrate. Exemplarily, the dam structure 3 may include one or more of a buffer material layer 51, a gate insulating material layer 61, a capacitor dielectric material layer 81, and an interlayer insulating material layer 91. The at least one inorganic insulating layer may include one or more of a buffer material layer 51, a gate insulating material layer 61, a capacitor dielectric material layer 81, and an interlayer insulating material layer 91.

[0070] Optionally, see again Figure 3 , along the direction away from the substrate 1, the dam structure 3 includes a buffer material layer 51, a gate insulating material layer 61, a capacitor dielectric material layer 81 and an interlayer insulating material layer 91 which are stacked in sequence. Optionally, the electrostatic discharge trace 4 extends through the side of the interlayer insulating material layer 91, the side of the capacitor dielectric material layer 81, the side of the gate insulating material layer 61 and the side of the buffer material layer 51 to be electrically connected to the first functional layer 101. In the display area AA, the array substrate also includes a buffer layer 5 located on one side of the substrate 1, a gate insulating layer 6 located between the buffer layer 5 and the first conductive layer 10, a capacitor dielectric layer 8 located between the first conductive layer 10 and the second conductive layer 12, an interlayer insulating layer 9 located between the second conductive layer 12 and the third conductive layer 11, and a semiconductor layer 7 located between the buffer layer 5 and the gate insulating layer 6.

[0071] Among them, the buffer layer 5 is arranged on the same layer as the buffer material layer 51 , the gate insulation layer 6 is arranged on the same layer as the gate insulation material layer 61 , the capacitor dielectric layer 8 is arranged on the same layer as the capacitor dielectric material layer 81 , and the interlayer insulation layer 9 is arranged on the same layer as the interlayer insulation material layer 91 .

[0072] Along the direction away from the substrate 1, a buffer layer 5, a gate insulating layer 6, a capacitor dielectric layer 8 and an interlayer insulating layer 9 are sequentially formed on one side of the substrate 1, and then the interlayer insulating layer 9, the capacitor dielectric layer 8, the gate insulating layer 6 and the buffer layer 5 are sequentially etched in the non-display area AB, and then the dam structure 3 is formed in the non-display area AB. In this way, there is no need to form the dam structure 3 through a special film layer, so that the process can be simplified and the cost of forming the dam structure 3 can be reduced.

[0073] Optionally, see Figure 4 The array substrate further includes a first planarization layer 13 located on a side of the third conductive layer 11 away from the substrate 1, and the first planarization layer 13 fills the groove structure 16. When the first planarization layer 13 is formed, the first planarization layer 13 will fill the groove structure 16 between the dam structures 3. If the groove structure 16 between the dam structures 3 has an electrostatic discharge wiring 4, the first planarization layer 13 will also cover the side of the electrostatic discharge wiring 4 away from the substrate 1. The first planarization layer 13 can be an organic insulating layer.

[0074] For some possible implementations, see Figure 5 , along the direction away from the substrate 1, the array substrate further includes a first conductive layer 10, a second conductive layer 12, a third conductive layer 11 and a fourth conductive layer 14 stacked in sequence, and the fourth conductive layer 14 includes an electrostatic discharge trace 4. The first conductive layer 10, the second conductive layer 12, the third conductive layer 11 and the fourth conductive layer 14 may include a metal layer or an indium tin oxide layer.

[0075] The first conductive layer 10, the second conductive layer 12, the third conductive layer 11 and the fourth conductive layer 14 are all metal layers. The fourth conductive layer 14 includes a second source and drain electrode layer. When the fourth conductive layer 14 is formed, part of the fourth conductive layer 14 will be deposited in the groove structure between the dam structure 3. After etching, the fourth conductive layer 14 will form an electrostatic release wiring 4, and the electrostatic release wiring 4 will be electrically connected to the first functional layer 101 through the groove structure 16 adjacent to the dam structure 3. In this way, the electrostatic release wiring 4 can be formed when the fourth conductive layer 14 is formed, and there is no need to set the electrostatic release wiring 4 through a special process, thereby simplifying the process and reducing the cost of forming the electrostatic release wiring 4.

[0076] Optionally, see again Figure 5 , along the direction away from the substrate 1, the dam structure 3 includes a buffer material layer 51, a gate insulating material layer 61, a capacitor dielectric material layer 81, an interlayer insulating material layer 91 and a first planarizing material layer 131 which are stacked in sequence. Optionally, the electrostatic discharge trace 4 extends through the side of the first planarizing material layer 131, the side of the interlayer insulating material layer 91, the side of the capacitor dielectric material layer 81, the side of the gate insulating material layer 61 and the side of the buffer material layer 51 to be electrically connected to the first functional layer 101.

[0077] In the display area AA, the array substrate further includes a first planarization layer 13 located between the third conductive layer 11 and the fourth conductive layer 14, and the first planarization layer 13 is disposed in the same layer as the first planarization material layer 131. Along the direction away from the substrate 1, a buffer layer 5, a gate insulating layer 6, a capacitor dielectric layer 8 and an interlayer insulating layer 9 are sequentially formed on one side of the substrate 1, and then the interlayer insulating layer 9, the capacitor dielectric layer 8, the gate insulating layer 6 and the buffer layer 5 are sequentially etched in the non-display area AB, and a part of the dam structure 3 is formed in the non-display area AB. A first planarization layer 13 is then formed on the side of the third conductive layer 11 away from the substrate 1, and the first planarization layer 13 will be filled in the groove structure of the dam structure 3, and then the material of the first planarization layer 13 in the groove structure of the dam structure 3 is etched away, and the first planarization material layer 131 on the side of the dam structure 3 away from the substrate 1 is retained. Then, a fourth conductive layer 14 is formed on a side of the first planarization layer 13 away from the substrate 1 . Part of the fourth conductive layer 14 fills the groove structure of the dam structure 3 and forms an electrostatic discharge trace 4 electrically connected to the first functional layer 101 .

[0078] See also Figure 6 , and then a second planarization layer 15 is formed on the side of the fourth conductive layer 14 away from the substrate 1. The second planarization layer 15 will fill the groove structure between the dam structures 3. If the groove structure between the dam structures 3 has an electrostatic discharge wiring 4, the second planarization layer 15 will also cover the side of the electrostatic discharge wiring 4 away from the substrate 1. In this way, there is no need to form the first planarization material layer 131 and the electrostatic discharge wiring 4 through a special film layer, nor is there a need to form the dam structure 3 through a special film layer, thereby simplifying the process and reducing the cost of forming the dam structure 3. The second planarization layer 15 can be an organic insulating layer.

[0079] In some possible implementations, there are multiple dam structures 3, and the multiple dam structures 3 are arranged in a direction from the display area AA to the non-display area AB. A groove structure 16 is provided on at least one side of the dam structure 3, and a groove structure 16 is provided between the multiple dam structures 3. The electrostatic discharge wiring 4 is electrically connected to the first functional layer 101 via at least the groove structure 16 adjacent to the dam structure 3 closest to the display area AA. The electrostatic discharge wiring 4 can be electrically connected to the first functional layer 101 via one or more groove structures 16. The electrostatic discharge wiring 4 can be electrically connected to the first functional layer 101 via the groove structure 16 adjacent to at least one dam structure 3.

[0080] In the first embodiment, see again Figure 3 When the electrostatic discharge wiring 4 is formed through the third conductive layer 11, the electrostatic discharge wiring 4 is electrically connected to the first functional layer 101 through a groove structure 16 adjacent to a dam structure 3 closest to the display area AA, which is equivalent to being electrically connected to the first functional layer 101 through a groove structure 16.

[0081] In the second embodiment, please refer again to Figure 5 When the electrostatic discharge wiring 4 is formed through the fourth conductive layer 14 , the electrostatic discharge wiring 4 is electrically connected to the first functional layer 101 through a groove structure 16 adjacent to a dam structure 3 closest to the display area AA, which is equivalent to being electrically connected to the first functional layer 101 through a groove structure 16 .

[0082] In the third embodiment, see Figure 7 When the electrostatic discharge wiring 4 is formed through the third conductive layer 11, the electrostatic discharge wiring 4 is arranged on the side of the plurality of dam structures 3, and is electrically connected to the first functional layer 101 through the groove structures 16 adjacent to the plurality of dam structures 3, which is equivalent to being electrically connected to the first functional layer 101 through the plurality of groove structures 16. In this way, the first functional layer 101 can have a plurality of electrostatic discharge channels, so that the static electricity in the first functional layer 101 can be more effectively discharged, and the problem of uneven display at the edge of the display panel can be further improved.

[0083] In the fourth embodiment, see Figure 8 When the electrostatic discharge wiring 4 is formed through the fourth conductive layer 14, the electrostatic discharge wiring 4 is arranged on the side of the plurality of dam structures 3, and is electrically connected to the first functional layer 101 through the groove structures 16 adjacent to the plurality of dam structures 3, which is equivalent to being electrically connected to the first functional layer 101 through the plurality of groove structures 16. In this way, the first functional layer 101 can have a plurality of electrostatic discharge channels, so that the static electricity in the first functional layer 101 can be more effectively discharged, and the problem of uneven display at the edge of the display panel can be further improved.

[0084] In some possible implementations, the dam structure 3 includes at least one inorganic insulating layer and / or at least one organic insulating layer stacked along the thickness direction of the array substrate. Exemplarily, the dam structure 3 may include one or more of a buffer material layer 51, a gate insulating material layer 61, a capacitor dielectric material layer 81, an interlayer insulating material layer 91, and a first planarization material layer 131. The at least one inorganic insulating layer may include one or more of a buffer material layer 51, a gate insulating material layer 61, a capacitor dielectric material layer 81, and an interlayer insulating material layer 91. The at least one organic insulating layer may include a first planarization material layer 131.

[0085] Optionally, the substrate 1 further includes at least one organic layer and at least one inorganic layer stacked along the thickness direction of the array substrate, and the first functional layer 101 is located between the organic layer and the inorganic layer of the substrate 1. Optionally, the first functional layer 101 is used to improve the adhesion between the organic layer and the inorganic layer in contact with both sides of the first functional layer 101. Optionally, the first functional layer 101 includes an amorphous material layer, a metal oxide layer or a metal layer, for example, the amorphous material layer may include an amorphous silicon layer. Optionally, the first functional layer 101 includes an amorphous silicon layer, an indium tin oxide layer (ITO) or a metal layer. The first functional layer 101 includes an aluminum (AL) metal layer, a titanium (Ti) metal layer or a molybdenum (Mo) metal layer. The inorganic layer may include a silicon oxide layer or a silicon nitride layer, etc. The organic layer may include a polyimide layer, etc. The first functional layer 101 may be one or more layers. Optionally, the substrate 1 further includes organic layers and inorganic layers alternately stacked along the thickness direction of the array substrate. Optionally, the substrate 1 includes an organic layer and an inorganic layer, the first functional layer 101 is located between the organic layer and the inorganic layer, and the dam structure 3 and the electrostatic release wiring 4 are located on a side of the first functional layer 101 away from the organic layer.

[0086] Optionally, the substrate 1 includes a first organic layer 105, a first barrier layer 104, a second organic layer 103, and a second barrier layer 102 which are sequentially stacked along the thickness direction of the array substrate. Optionally, at least one first functional layer 101 may be located between the first organic layer 105 and the first barrier layer 104. Optionally, at least one first functional layer 101 may be located between the second organic layer 103 and the second barrier layer 102. Optionally, at least one first functional layer 101 may be located between the first barrier layer 104 and the second organic layer 103. The first barrier layer 104 may be an inorganic layer. The second barrier layer 102 may be an inorganic layer.

[0087] Specifically, the substrate 1 further includes a first organic layer 105, a first barrier layer 104 located on one side of the first organic layer 105, a second organic layer 103 located on a side of the first barrier layer 104 away from the first organic layer 105, and a second barrier layer 102 located on a side of the second organic layer 103 away from the first organic layer 105, the first functional layer 101 is located between the second organic layer 103 and the second barrier layer 102, and the dam structure 3 and the electrostatic release wiring 4 are located on a side of the first functional layer 101 away from the first organic layer 105. Optionally, the substrate 1 is a flexible substrate 1. In some embodiments, please refer again to Figure 8 The groove structure 16 penetrates the second barrier layer 102 and the first functional layer 101 , and the electrostatic discharge trace 4 is in electrical contact with the side wall of the first functional layer 101 in the groove structure 16 .

[0088] In another embodiment, see Fig. 9, the groove structure 16 penetrates the second barrier layer 102, and the electrostatic discharge wiring 4 is in electrical contact with the side of the first functional layer 101 away from the substrate 1. In this way, the electrostatic discharge wiring 4 can be more easily electrically connected to the first functional layer 101. The groove structure 16 may not penetrate the first functional layer 101.

[0089] For some possible implementations, see Fig.10 The array substrate further includes a first voltage line and a plurality of pixel circuits, the first voltage line is electrically connected to the pixel circuit, and the first voltage line is multiplexed as an electrostatic release line. For example, the first voltage line may include at least one of a power supply voltage line VDD and an initialization voltage line Vref. Optionally, the electrostatic release line 4 is a DC voltage line. Optionally, the electrostatic release line 4 includes at least one of a power supply voltage line VDD, a common voltage line VSS, an initialization voltage line Vref, and a touch line. A plurality of pixel circuits may be located in the display area.

[0090] The power voltage routing, the common voltage routing, the initialization voltage routing or the touch routing are reused as the electrostatic release routing 4. On the one hand, it is not necessary to specially set up the electrostatic release routing 4, thereby reducing the cost of specially setting up the electrostatic release routing 4. On the other hand, the electrostatic release effect of the power voltage routing, the common voltage routing, the initialization voltage routing or the touch routing is better, thereby improving the effect of releasing the static electricity in the first functional layer 101. One of the power voltage routing and the common voltage routing is a high voltage, and the other is a low voltage. For example, the power voltage routing is a high voltage, and the common voltage routing is a low voltage.

[0091] The pixel circuit may include a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first initialization transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second initialization transistor T7 and a storage capacitor C ST Part or all of. The initialization voltage line Vref may be electrically connected to the gate of the driving transistor T1 via the first initialization transistor T4. The initialization voltage line Vref may be electrically connected to the first electrode of the light-emitting element D1 via the second initialization transistor T7. The second electrode of the light-emitting element D1 may be electrically connected to the common voltage line VSS. The power supply voltage line VDD may be electrically connected to the first electrode of the driving transistor T1 via the first light-emitting control transistor T5. The data line Vdata may be electrically connected to the first electrode of the driving transistor T1 via the data writing transistor T2. The threshold compensation transistor T3 may be connected between the second electrode and the gate of the driving transistor T1. The second electrode of the driving transistor T1 may be electrically connected to the first electrode of the light-emitting element D1 via the second light-emitting control transistor T6. The storage capacitor C ST It can be connected between the power supply voltage line VDD and the gate of the driving transistor T1. The light emitting element can be located in the display area.

[0092] Optionally, the dam structure is a crack dam. Exemplarily, a large-area array substrate can be formed into multiple small-area array substrates by cutting. The dam structure can be arranged adjacent to the cutting transition zone. The dam structure can be located between the display area and the cutting transition zone. The cutting transition zone can be located between the dam structure and the cutting line. The groove structure 16 can be used to disperse the stress generated when cutting the array substrate, and / or block the path of the crack generated when cutting the array substrate to the display area AA.

[0093] In summary, in the present application, an electrostatic release line 4 electrically connected to the first functional layer 101 through a groove structure 16 adjacent to the dam structure 3 is provided to provide an electrostatic discharge channel for the first functional layer 101, so that the static electricity of the first functional layer 101 can be discharged in time. The first functional layer 101 is not prone to static electricity accumulation at the display edge of the display panel, thereby improving the problem of uneven display at the edge of the display panel, and ultimately improving the display quality of the display panel.

[0094] In some possible implementations, the present application further provides a display panel, and the display panel includes the array substrate in the present application.

[0095] Optionally, the display panel includes the array substrate of the present application and a packaging dam located on one side of the array substrate, and the dam structure in the array substrate is located on the side of the packaging dam away from the display area of ​​the display panel. The display panel may also include a light-emitting unit located on one side of the array substrate, and an encapsulation layer located on the side of the light-emitting unit away from the array substrate, and the encapsulation layer is used to encapsulate the light-emitting unit. Light-emitting unit light-emitting element D1. When forming the organic packaging material of the encapsulation layer, the packaging dam can be used to prevent excessive overflow of the organic packaging material into the non-display area, which is beneficial to reduce the border width. The dam structure in the array substrate of the present application is a crack dam. Since the display panel includes the array substrate of the present application, the edge of the display area AA of the display panel is displayed more uniformly and the display effect is better.

[0096] In some possible implementations, the present application further provides an electronic device, the electronic device including the display panel in the present application. The electronic device may include a device with image processing capabilities, such as a server, a personal computer, a laptop computer, etc. Since the electronic device includes the display panel in the present application, the edge display of the electronic device is more uniform and the display effect is better.

[0097] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0098] The above-mentioned embodiments only express several implementation methods of the utility model, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the utility model patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, which all belong to the protection scope of the utility model. Therefore, the protection scope of the utility model patent shall be based on the attached claims.

Claims

1. An array substrate, characterized in that: The array substrate comprises: a substrate comprising a first functional layer; a dam structure and a groove structure located on one side of the substrate; An electrostatic discharge wiring is electrically connected to the first functional layer via the groove structure adjacent to the dam structure.

2. The array substrate according to claim 1, characterized in that: The array substrate comprises a display area and a non-display area surrounding at least a portion of the display area; the dam structure is located in the non-display area; And / or, the array substrate includes a border region, and the dam structure is located in the border region; And / or, the dam structure includes at least one inorganic insulating layer and / or at least one organic insulating layer stacked along the thickness direction of the array substrate; And / or, the array substrate further includes a first voltage line and a plurality of pixel circuits, the first voltage line is electrically connected to the pixel circuits, and the first voltage line is multiplexed as the electrostatic release wiring; and / or, the dam structure is a cracked dam; And / or, the substrate further comprises at least one organic layer and at least one inorganic layer stacked along the thickness direction of the array substrate, and the first functional layer is located between the organic layer and the inorganic layer of the substrate; And / or, the first functional layer includes an amorphous silicon layer, an indium tin oxide layer or a metal layer.

3. The array substrate according to claim 1, characterized in that: Along the direction away from the substrate, the array substrate further comprises a first conductive layer, a second conductive layer and a third conductive layer which are stacked in sequence; The third conductive layer includes the electrostatic discharge trace; And / or, along a direction away from the substrate, the dam structure includes a buffer material layer, a gate insulating material layer, a capacitor dielectric material layer and an interlayer insulating material layer stacked in sequence; The electrostatic discharge wiring sequentially extends through the side surface of the interlayer insulating material layer, the side surface of the capacitor dielectric material layer, the side surface of the gate insulating material layer and the side surface of the buffer material layer to be electrically connected to the first functional layer; And / or, the array substrate further comprises a first planarization layer located on a side of the third conductive layer away from the substrate, and the first planarization layer fills the groove structure; And / or, the first conductive layer includes a gate layer, the second conductive layer includes a capacitor plate layer, and the third conductive layer includes a first source and drain layer.

4. The array substrate according to claim 1, characterized in that: Along the direction away from the substrate, the array substrate further comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are stacked in sequence; The fourth conductive layer includes the electrostatic discharge trace; and / or, along a direction away from the substrate, the dam structure includes a buffer material layer, a gate insulating material layer, a capacitor dielectric material layer, an interlayer insulating material layer and a first planarizing material layer stacked in sequence, The electrostatic discharge wiring sequentially extends through the side surface of the first planarization material layer, the side surface of the interlayer insulating material layer, the side surface of the capacitor dielectric material layer, the side surface of the gate insulating material layer and the side surface of the buffer material layer to be electrically connected to the first functional layer; And / or, the array substrate further comprises a second planarization layer located on a side of the fourth conductive layer away from the substrate, and the second planarization layer fills the groove structure; And / or, the first conductive layer includes a gate layer, the second conductive layer includes a capacitor plate layer, the third conductive layer includes a first source and drain layer, and the fourth conductive layer includes a second source and drain layer.

5. The array substrate according to claim 1, characterized in that: The array substrate comprises a display area and a non-display area; the dam structure is located in the non-display area; There are multiple dam structures, and the multiple dam structures are arranged along the direction from the display area to the non-display area. The groove structure is arranged on at least one side of the dam structure, and the groove structure is arranged between the multiple dam structures. The electrostatic release wiring is electrically connected to the first functional layer at least through the groove structure adjacent to the dam structure closest to the display area.

6. The array substrate according to claim 5, characterized in that: The electrostatic discharge wiring is electrically connected to the first functional layer via the groove structure adjacent to one or more of the dam structures.

7. The array substrate according to claim 1, characterized in that: The substrate further comprises: a first organic layer, a first barrier layer located on one side of the first organic layer, a second organic layer located on a side of the first barrier layer away from the first organic layer, and a second barrier layer located on a side of the second organic layer away from the first organic layer, the first functional layer being located between the second organic layer and the second barrier layer; the dam structure and the electrostatic release wiring are located on a side of the first functional layer away from the first organic layer; And / or, the substrate is a flexible substrate; And / or, the groove structure penetrates the second barrier layer and the first functional layer.

8. The array substrate according to claim 1, characterized in that: The first functional layer includes an amorphous material layer, a metal oxide layer or a metal layer; And / or, the electrostatic release wiring is a DC voltage wiring; And / or, the electrostatic release wiring includes at least one of a power supply voltage wiring, a common voltage wiring, an initialization voltage wiring and a touch wiring.

9. A display panel, characterized in that: The display panel comprises: The array substrate according to any one of claims 1 to 8; The packaging dam is located at one side of the array substrate, and the dam structure in the array substrate is located at a side of the packaging dam away from the display area of ​​the display panel.

10. An electronic device, characterized in that: The electronic device comprises the display panel described in claim 9.

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