Light emitting diode

Abstract

The embodiment of the utility model discloses a light emitting diode. The light emitting diode comprises a substrate, an epitaxial layer, a first electrode, a second electrode, a first dielectric layer, a third electrode and a fourth electrode. A first semiconductor layer, a multi-quantum well layer and a second semiconductor layer are sequentially stacked on the epitaxial layer from bottom to top, the first electrode is electrically connected with the first semiconductor layer through a through hole, the second electrode is electrically connected with the second semiconductor layer, and the first electrode and the second electrode are arranged in an array mode. The third electrode is arranged along the first direction and covers a row of first electrodes, and the fourth electrode is arranged along the first direction and covers a row of second electrodes. According to the embodiment of the utility model, the minimum sizes of the third electrode and the fourth electrode along the second direction are the same, so that the current congestion conditions of the third electrode and the fourth electrode at the minimum size are the same, and the light-emitting diode is ensured to have higher reliability.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a light emitting diode. Background Art

[0002] As a new type of green lighting source, Light Emitting Diode (LED) has the advantages of energy saving, high efficiency, low carbon, small size, fast response, and strong shock resistance. It can provide users with a new lighting experience that is environmentally friendly, stable, efficient and safe, and has gradually developed into a mature semiconductor lighting industry.

[0003] Flip-Chip LED (Flip-Chip Light Emitting Diode) is a special type of light-emitting diode. Compared with traditional upright light-emitting diodes, flip-chip LEDs have better heat dissipation and reliability, and because they emit light from one side of the substrate, they avoid the problem of pads and leads blocking light. However, flip-chip LEDs have the problem of low photoelectric conversion efficiency. Utility Model Content

[0004] In view of this, an object of the present invention is to provide a light emitting diode to improve the photoelectric conversion efficiency of the light emitting diode.

[0005] The utility model provides a light-emitting diode, which comprises: a substrate; an epitaxial layer located on the substrate, the epitaxial layer comprising a first semiconductor layer, an active layer and a second semiconductor layer stacked in sequence from bottom to top, the first semiconductor layer and the second semiconductor layer having different doping types, the epitaxial layer having a plurality of through holes penetrating the second semiconductor layer and the active layer and exposing the first semiconductor layer, the through holes being arranged in an array; a plurality of first electrodes respectively located on the surface of the first semiconductor layer exposed by the through holes; a plurality of second electrodes arranged in an array on the second semiconductor layer; a first dielectric layer covering the epitaxial layer, the first electrode and the second electrode, the first dielectric layer having a plurality of first openings exposing the first electrodes and a plurality of second openings exposing the second electrodes; a plurality of third electrodes located on the first dielectric layer and covering the first openings, one third electrode covering a row of first openings arranged along a first direction; and a plurality of fourth electrodes located on the first dielectric layer and covering the second openings, one fourth electrode covering a row of second openings arranged along the first direction; wherein the minimum dimensions of the third electrode and the fourth electrode along the second direction are the same.

[0006] Further, a plurality of first electrodes are arranged into a plurality of rows along the first direction, and the plurality of rows of first electrodes are arranged at intervals along the second direction; a plurality of second electrodes are arranged into a plurality of rows along the first direction, and the plurality of rows of second electrodes are arranged at intervals along the second direction; a row composed of a plurality of second electrodes arranged at intervals along the first direction and a row composed of a plurality of first electrodes arranged at intervals along the first direction are alternately arranged along the second direction, and the first electrodes and the second electrodes of two adjacent rows are staggered in the first direction; and / or a plurality of first electrodes are arranged into a plurality of columns along the second direction, and the plurality of columns of first electrodes are arranged at intervals along the first direction; a plurality of second electrodes are arranged into a plurality of columns along the second direction, and the plurality of columns of second electrodes are arranged at intervals along the first direction; a column composed of a plurality of second electrodes arranged at intervals along the second direction and a column composed of a plurality of first electrodes arranged at intervals along the second direction are alternately arranged along the first direction, and the first electrodes and the second electrodes of two adjacent columns are staggered in the second direction.

[0007] Furthermore, the sizes of the third electrode and the fourth electrode along the second direction are the same everywhere.

[0008] Furthermore, the third electrode and the fourth electrode both include a strip structure extending along the first direction, a wavy structure or a broken line structure, a strip structure with rounded corners, or a strip structure with protrusions and / or depressions at a predetermined position, and the shapes of the third electrode and the fourth electrode are the same or different.

[0009] Further, a size of the third electrode along the second direction is larger than a size of the first opening along the second direction; a size of the fourth electrode along the second direction is larger than a size of the second opening along the second direction.

[0010] Further, a size of the third electrode along the second direction is greater than a size of the first electrode along the second direction, and a size of the fourth electrode along the second direction is greater than a size of the second electrode along the second direction.

[0011] Further, the first dielectric layer is a SiO2 film or a DBR reflector or a SiO2 film and a DBR reflector stacked from bottom to top.

[0012] Furthermore, the light-emitting diode also includes: a second dielectric layer covering the first dielectric layer, the third electrode and the fourth electrode, the second dielectric layer having a plurality of third openings exposing the third electrodes and a plurality of fourth openings exposing the fourth electrodes; a first solder pad located on the second dielectric layer and covering all the third openings; and a second solder pad located on the second dielectric layer and covering all the fourth openings.

[0013] Further, the third opening is arranged corresponding to the third electrode, and a plurality of third openings are arranged along the second direction; the fourth opening is arranged corresponding to the fourth electrode, and a plurality of fourth openings are arranged along the second direction.

[0014] Furthermore, the light emitting diode further comprises a current spreading layer arranged on the second semiconductor layer, a projection boundary of the current spreading layer in the direction of the substrate is located within a projection boundary of the second semiconductor layer in the direction of the substrate, and the second electrode is arranged on the current spreading layer.

[0015] Further, each of the third electrodes corresponds to at least one of the third openings, and each of the fourth electrodes corresponds to at least one of the fourth openings.

[0016] The utility model embodiment discloses a light-emitting diode, which includes a substrate, an epitaxial layer, a first electrode, a second electrode, a first dielectric layer, a third electrode and a fourth electrode. The epitaxial layer sequentially stacks a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer from bottom to top, the first electrode is arranged in a through hole and electrically connected to the first semiconductor layer, the second electrode is electrically connected to the second semiconductor layer, and the first electrode and the second electrode array are arranged. The third electrode is arranged along the first direction and covers a row of first electrodes, and the fourth electrode is arranged along the first direction and covers a row of second electrodes. The third electrode and the fourth electrode of the utility model embodiment have the same minimum size along the second direction, ensuring that the current congestion of the third electrode and the fourth electrode at the minimum size is the same, thereby ensuring that the light-emitting diode has high reliability.

[0017] Furthermore, the fourth electrode can quickly inject current into the second electrode and thus into the second semiconductor layer, and the current flowing out of the first semiconductor layer can be quickly input into the third electrode through the first electrode, so that the light-emitting diode is not prone to current congestion, has higher reliability and photoelectric conversion efficiency, and improves the upper limit of the stress that the light-emitting diode can withstand. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other purposes, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0019] Figure 1 is a top view of the light emitting diode provided in the first embodiment of the utility model;

[0020] Figure 2 It is a partial cross-sectional view of the light emitting diode at AA provided in the first embodiment of the utility model;

[0021] Figure 3 It is a partial cross-sectional view of the light emitting diode LL provided in the first embodiment of the utility model;

[0022] Figure 4 It is a flow chart of a method for forming a light emitting diode provided in the first embodiment of the utility model;

[0023] Figure 5-Figure 22It is a schematic diagram of different stages of the light emitting diode provided by the first embodiment of the utility model;

[0024] Fig.23 is a top view of the third electrode and the fourth electrode provided in the second embodiment of the present utility model;

[0025] Fig.24 is a top view of the third electrode and the fourth electrode provided in the third embodiment of the present utility model;

[0026] Fig.25 It is a top view of the third electrode and the fourth electrode provided in the fourth embodiment of the present utility model.

[0027] Description of reference numerals:

[0028] 100-substrate;

[0029] 200-epitaxial layer; 210-first semiconductor layer; 220-active layer; 230-second semiconductor layer; 240-through hole; 250-isolation trench;

[0030] 310 - first electrode; 320 - second electrode;

[0031] 400 - first dielectric layer; 410 - first opening; 420 - second opening;

[0032] 510 - third electrode; 520 - fourth electrode;

[0033] 600- second dielectric layer; 610- third opening; 620- fourth opening

[0034] 710-first pad; 720-second pad;

[0035] 800-Current expansion layer. DETAILED DESCRIPTION

[0036] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for those skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, flows, components and circuits are not described in detail.

[0037] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0038] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0039] For ease of explanation, spatially relative terms such as "inside", "outside", "below", "below", "lower", "above", "upper", etc. are used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature. It will be understood that spatially relative terms may be intended to include different orientations of the device in use or operation other than the orientation depicted in the figures. For example, if the device in the figure is turned over, an element described as being "below" or "below" other elements or features will then be positioned as being "above" the other elements or features. Thus, the example term "below" can include both the orientations of above and below. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0040] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".

[0041] In the description of this application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0042] The photoelectric conversion efficiency of flip-chip light-emitting diodes is mainly divided into external quantum efficiency (EQE) and internal quantum efficiency (IQE). External quantum efficiency refers to the ratio of the device's output photocurrent to the incident photon flow. The main influencing factor of external quantum efficiency is whether the electron-hole can be fully utilized and whether the electrical energy is converted into light energy. Internal quantum efficiency refers to the efficiency of photoelectric conversion inside the device. The main influencing factor of internal quantum efficiency is whether the electron-hole in the epitaxial layer can be fully combined.

[0043] In view of this, an embodiment of the utility model provides a light emitting diode, which can improve the photoelectric conversion efficiency of the light emitting diode. Figure 1 is a top view of a light emitting diode provided in the first embodiment of the utility model, Figure 2This is a partial cross-sectional view of the light emitting diode AA provided in the first embodiment of the utility model. Figure 3 FIG. 1 is a partial cross-sectional view of the light emitting diode LL provided in the first embodiment of the present invention. Figure 1 , Figure 2 and Figure 3 As shown, the light-emitting diode includes a substrate 100, an epitaxial layer 200, a plurality of first electrodes 310, a plurality of second electrodes 320, a first dielectric layer 400, a plurality of third electrodes 510 and a plurality of fourth electrodes 520. The epitaxial layer 200 includes a first semiconductor layer 210, an active layer 220 and a second semiconductor layer 230 stacked sequentially from bottom to top on the surface of the substrate 100, and the first semiconductor layer 210 and the second semiconductor layer 230 have different doping types. In this embodiment, the first semiconductor layer 210 is an N-type gallium nitride layer, and the second semiconductor layer 230 is a P-type gallium nitride layer. The epitaxial layer 200 also includes a plurality of through holes 240 that penetrate the second semiconductor layer 230 and the active layer 220 and expose the first semiconductor layer 210, and the plurality of through holes 240 are arranged in an array in the epitaxial layer 200. The plurality of first electrodes 310 are respectively located on the surface of the first semiconductor layer 210 exposed by the through holes 240, and the plurality of second electrodes 320 are arranged in an array on the second semiconductor layer 230. The first dielectric layer 400 is located on the epitaxial layer 200 and covers the first electrode 310 and the second electrode 320. The first dielectric layer 400 has a plurality of first openings 410 exposing the first electrodes 310 and a plurality of second openings 420 exposing the second electrodes 320. A plurality of third electrodes 510 are located on the first dielectric layer 400 and cover the first openings 410. A plurality of fourth electrodes 520 are located on the first dielectric layer 400 and cover the second openings 420.

[0044] Further, the light emitting diode further includes a second dielectric layer 600, a first pad 710 and a second pad 720. The second dielectric layer 600 is located on the first dielectric layer 400, the third electrode 510 and the fourth electrode 520, and the second dielectric layer 600 has a plurality of third openings 610 exposing the third electrodes 510 and a plurality of fourth openings 620 exposing the fourth electrodes 520. The first pad 710 is located on the second dielectric layer 600 and covers all the third openings 610, and the second pad 720 is located on the second dielectric layer 600 and covers all the fourth openings 620. When the light emitting diode is turned on, the current is uniformly and rapidly injected from the second pad 720 into the plurality of fourth electrodes 520, and then rapidly injected from the fourth electrode 520 into the plurality of second electrodes 320 and enters the second semiconductor layer 230 from the second electrode 320, thereby realizing rapid expansion of the current. After the current enters the second semiconductor layer 230, it flows to the first semiconductor layer 210, and then flows to the plurality of first electrodes 310 through the first semiconductor layer 210, and then flows from the plurality of first electrodes 310 to the third electrode 510, and finally flows from the plurality of third electrodes 510 to the first pad 710. Since the first electrode 310 and the second electrode 320 are evenly distributed, the current density of the third electrode 510 and the fourth electrode 520 is consistent, and current congestion will not be caused, so that the thermal resistance of the light-emitting diode is small, and it has high reliability and photoelectric conversion efficiency. In addition, the first electrode 310 and the second electrode 320 can also improve the expansion capability of the current and enhance the electron-hole combination.

[0045] like Figure 1 and Figure 7 As shown, a plurality of through holes 240 with the same aperture and depth are arranged in an array in the epitaxial layer 200. In the present embodiment, a plurality of through holes 240 are arranged in a matrix, and the through holes 240 are arranged in a plurality of rows at the same interval along the first direction (the x-axis direction in the figure), and the rows formed by the plurality of through holes 240 are spaced equally in the second direction (the y-axis direction in the figure), and the first direction is perpendicular to the second direction. That is, the spacing between any two adjacent through holes 240 in the first direction is equal, and the spacing in the second direction is also equal. Preferably, the spacing between any two adjacent through holes 240 in the first direction is equal to the spacing in the second direction. In addition, the opening shape of the through hole 240 can be circular, elliptical, polygonal, etc., and the specific shape is selected according to actual needs. The through holes 240 uniformly arranged in the epitaxial layer 200 can effectively reduce the stress existing in the epitaxial layer 200 itself and improve the reliability of the overall structure.

[0046] The first electrode 310 and the second electrode 320 are respectively arranged in different areas of the epitaxial layer 200. In the present embodiment, the first electrode 310 and the second electrode 320 are cylindrical structures of the same size. The first electrode 310 and the second electrode 320 may also be columnar structures with other cross-sectional shapes, and the cross-sectional shapes may be other shapes such as polygons and ellipses. Preferably, a cross-sectional shape that is the same as the opening shape of the through hole 240 is adopted. The first electrode 310 is arranged at the bottom of the through hole 240 and is directly connected to the first semiconductor layer 210. In the present embodiment, the cross section of the first electrode 310 in the vertical axis direction is circular, and the opening shape of the through hole 240 is also circular. The two circles have different diameters but are arranged concentrically. Since the through holes 240 are arranged in an array with equal spacing, the first electrodes 310 arranged in the through holes 240 are also arranged in an array with equal spacing, so that the current expansion between the first semiconductor layer 210 and the first electrode 310 is better, the recombination of electrons and holes is improved, and the internal quantum efficiency is improved.

[0047] The second electrodes 320 are arranged on the surface of the second semiconductor layer 230 avoiding the through-holes 240 array. A plurality of second electrodes 320 are arranged in a matrix, and the second electrodes 320 are arranged in multiple rows at the same interval in the first direction, and the intervals of the second electrodes 320 in each row are equal in the second direction. The rows composed of the second electrodes 320 arranged at intervals along the first direction and the rows composed of the through-holes 240 (and the first electrodes 310 arranged in the through-holes 240) arranged at intervals along the first direction are arranged alternately, and the first electrodes 310 and the second electrodes 320 of two adjacent rows are staggered in the first direction; the columns composed of the second electrodes 320 arranged at intervals along the second direction and the columns composed of the through-holes 240 (and the first electrodes 310 arranged in the through-holes 240) arranged at intervals along the second direction are arranged alternately, and the first electrodes 310 and the second electrodes 320 of two adjacent columns are staggered in the second direction. That is, each through-hole 240 has four second electrodes 320 on the periphery, and the four second electrodes 320 can be connected to form a square, and the four second electrodes 320 are arranged at the four vertices of the square, and the through-holes 240 are arranged at the intersection of the diagonals of the square. The distances from the four second electrodes 320 to the through hole 240 are equal. The second electrodes 320 uniformly arranged on the surface of the second semiconductor layer 230 make the current transmission more uniform when the second electrodes 320 and the second semiconductor layer 230 are turned on. The uniformly arranged first electrodes 310 and second electrodes 320 can improve the current transmission uniformity of the light-emitting diode, thereby improving the utilization rate of electrons and holes in the diode, thereby reducing heat energy and improving the photoelectric conversion efficiency of the light-emitting diode.

[0048] The arrangement of the through hole 240, the first electrode 310 and the second electrode 320 of the embodiment of the utility model is not limited to this, and can be arranged in other ways according to needs, such as a matrix array, a pentagonal array, a hexagonal array, etc., to achieve the purpose of making the current distribution more uniform and maximizing the current expansion.

[0049] In this embodiment, the light emitting diode further includes a current spreading layer 800 disposed between the first electrode 310 and the second semiconductor layer 230, and the second electrode 320 forms an ohmic contact with the current spreading layer 800. The current spreading layer 800 is a metal film system, an oxide film system, other compound film systems, a polymer film system, a composite film system, etc. having high transmittance and conductivity. Preferably, it is indium tin oxide (ITO). Figure 2 , Figure 3 and Fig.11 As shown, the current spreading layer 800 is disposed on the second semiconductor layer 230, and the current spreading layer 800 does not cover the edge of the second semiconductor layer 230, the interior and edge of the through hole 240. That is, the boundary of the projection of the current spreading layer 800 in the direction of the substrate 100 is located within the boundary of the projection of the second semiconductor layer 230 in the direction of the substrate 100.

[0050] The first dielectric layer 400 covers the top surface and sidewalls of the epitaxial layer 200, the first electrode 310 and the second electrode 320. The first dielectric layer 400 has a plurality of first openings 410 exposing the first electrode 310 and a plurality of second openings 420 exposing the second electrode 320. Fig.15 and Fig.16 As shown, the size of the first opening 410 is smaller than the diameter of the first electrode 310 , and the size of the second opening 420 is smaller than the diameter of the second electrode 320 .

[0051] The first dielectric layer 400 can be a SiO2 film, a distributed Bragg reflector (DBR) reflector, or a SiO2 film and a DBR reflector stacked on the epitaxial layer 200, the first electrode 310, and the second electrode 320. The DBR reflector includes a plurality of pairs of two or more dielectric materials or optical films with different refractive indices that are grown alternately. In this embodiment, the DBR reflector is formed by alternating stacking of SiO2 and Ti3O5. When the first dielectric layer 400 has a DBR reflector, the DBR reflector can reflect the light emitted by the active layer 220 away from the substrate 100 in the direction of the substrate 100 when the light-emitting diode is turned on, thereby reducing the brightness loss and improving the light output rate of the light-emitting diode.

[0052] The light emitting diode further includes a plurality of third electrodes 510 arranged along the first direction, each of which covers a row of first openings 410 arranged along the first direction. The third electrode 510 covers the first openings 410 and is electrically connected to the first electrodes 310 exposed from the first openings 410. The fourth electrode 520 also extends along the first direction and covers a row of second openings 420 arranged along the first direction, and the fourth electrode 520 covers the second openings 420 and is electrically connected to the second electrodes 320 exposed from the second openings 420. In this embodiment, the third electrode 510 and the fourth electrode 520 are both strip structures arranged along the first direction, and the widths (dimensions along the second direction) of the third electrode 510 and the fourth electrode 520 are equal everywhere, so that the current density is similar when the two are turned on, and current congestion will not be caused. The third electrode 510 and the fourth electrode 520 are arranged in parallel, and a plurality of third electrodes 510 and a plurality of fourth electrodes 520 are alternately arranged on the first dielectric layer 400. The arrangement of such strip-shaped third electrodes 510 and fourth electrodes 520 can release the die stress of the light-emitting diode and expand the process window for subsequent packaging stress mismatch. And when the current flows through the third electrode 510 and the fourth electrode 520, there is no weak point and no current congestion will be caused. In addition, this design can also effectively reduce the thermal resistance of the product and improve reliability. In some embodiments, the third electrode 510 and the fourth electrode 520 are both strip structures arranged along the second direction, each third electrode 510 covers a column of first openings 410 arranged along the second direction, and each fourth electrode 520 covers a column of second openings 420 arranged along the second direction. The third electrode 510 and the fourth electrode 520 are arranged in parallel, and multiple third electrodes 510 and multiple fourth electrodes 520 are alternately arranged on the first dielectric layer 400.

[0053] Fig.23 is a top view of the third electrode and the fourth electrode provided in the second embodiment of the present invention. The second embodiment is different from the first embodiment only in the shape and arrangement position of the third electrode 510 and the fourth electrode 520. Fig.23 As shown, the third electrode 510 and the fourth electrode 520 are strip structures with protrusions along the second direction. The strip structure extends along the first direction, and the size of the third electrode 510 in the first direction is smaller than the size of the fourth electrode in the first direction. The third electrode 510 has an arc-shaped protrusion at a position corresponding to the first electrode 310, and the fourth electrode 520 has an arc-shaped protrusion at a position corresponding to the second electrode 320. That is, in the third electrode, the size of the third electrode 510 corresponding to the first electrode 310 in the second direction is the largest; in the fourth electrode, the size of the fourth electrode 520 corresponding to the second electrode 320 in the second direction is the largest.

[0054] Fig.241 is a top view of the third electrode and the fourth electrode provided in the third embodiment of the present invention. The third embodiment is different from the first embodiment only in the shape and arrangement position of the third electrode 510 and the fourth electrode 520. Fig.24 As shown, the third electrode 510 has a protrusion along the second direction in the middle and at a position corresponding to the first electrode 310, and the size of the protrusion in the middle is larger than the size of the protrusion at a position corresponding to the first electrode 310. The fourth electrodes 520 arranged on both sides of the third electrode 510 have corresponding depressions arranged along the second direction at positions corresponding to the protrusions of the third electrode 510. In addition, the ends of the third electrode 510 and the fourth electrode 520 extending along the first direction have rounded corners.

[0055] Fig.25 is a top view of the third electrode and the fourth electrode provided in the fourth embodiment of the present invention. The fourth embodiment is different from the first embodiment only in the shape and arrangement position of the third electrode 510 and the fourth electrode 520. Fig.25 As shown, the end of the third electrode 510 extending along the first direction has a rounded corner, the first end of the fourth electrode 520 extending along the first direction has a right angle, one side of the second end of the fourth electrode 520 extending along the first direction has a right angle, and the other side has a protrusion. The second ends of the fourth electrodes 520 located on both sides extend toward the fourth electrode 520 located in the middle, and the second ends of the fourth electrode 520 located in the middle extend toward the two fourth electrodes 520 located on both sides respectively. Adjacent fourth electrodes 520 do not contact each other. The dimension of the third electrode 510 in the first direction is shorter than the dimension of the fourth electrode 520 in the first direction. The third electrode 510 is arranged close to the first end of the fourth electrode 520 having a right angle, that is, the third electrode 510 is close to Fig.25 The right side is arranged so that the second end circumference side of the fourth electrode 520 does not have the third electrode 510 .

[0056] In some embodiments, the third electrode 510 and the fourth electrode 520 are in a zigzag, wavy or other shape. The third electrode 510 and the fourth electrode 520 of the special-shaped structure can be more conducive to the release of external stress compared to the regular strip structure of the first embodiment. The size of the third electrode 510 in the second direction may vary, for example, it may be an olive shape, a cone shape, etc. The size of the fourth electrode 520 in the second direction may vary, for example, it may be an olive shape, a cone shape, etc. The size in the second direction refers to the size along the second direction at any position in the top view. The third electrode 510 needs to have a size covering the first opening 410 at the corresponding position of the first electrode 310, and the fourth electrode 520 needs to have a size covering the second opening 420 at the corresponding position of the second electrode 320. The shape of the third electrode 510 at a position outside the corresponding area of ​​the first electrode 310, and the shape of the fourth electrode 520 at a position outside the corresponding area of ​​the second electrode 320 can be set according to requirements. The size of the third electrode 510 along the second direction is greater than the width of the first opening 410 along the second direction, and the size of the fourth electrode 520 along the second direction is greater than the width of the second opening 420 along the second direction. Preferably, the size of the third electrode 510 along the second direction is greater than the width of the first electrode 310 along the second direction, and the size of the fourth electrode 520 along the second direction is greater than the width of the second electrode 320 along the second direction. The size of the third electrode 510 and the fourth electrode 520 at the smallest point of the size along the second direction is equal, ensuring that the current congestion of the third electrode 510 and the fourth electrode 520 at the smallest point of the size is the same, thereby ensuring that the light-emitting diode has high reliability. When the third electrode 510 and the fourth electrode 520 are shaped according to requirements, the minimum size of the third electrode 510 and the fourth electrode 520 in the second direction is the same. It can be understood that if the third electrode 510 and the fourth electrode 520 are both strip structures arranged along the second direction, the minimum size of the third electrode 510 and the fourth electrode 520 in the first direction is the same.

[0057] Furthermore, the third electrode 510 and the fourth electrode 520 are made of one or more layers of conductive material. The third electrode 510 is provided with a metal reflective layer on one side close to the first electrode 310, and the fourth electrode 520 is provided with a metal reflective layer on one side close to the second electrode 320. It is preferred to use a metal reflective layer with a high reflectivity, such as silver, aluminum, gold, etc. The above metals can form an ODR reflector with a DBR reflector to improve the light extraction rate of the light emitting diode.

[0058] The second dielectric layer 600 is disposed on the first dielectric layer 400, the third electrode 510 and the fourth electrode 520. The third opening 610 is disposed in the region where the second dielectric layer 600 and the third electrode 510 overlap, and the fourth opening 620 is disposed in the region where the second dielectric layer 600 and the fourth electrode 520 overlap. The opening shapes of the third opening 610 and the fourth opening 620 may be circular, elliptical, polygonal, etc. The opening shapes of the third opening 610 and the fourth opening 620 may be the same or different, which is not limited here. The shapes of the third opening 610 and the fourth opening 620 are selected according to actual use scenarios or needs. The number of the third openings 610 of the second dielectric layer 600 is greater than or equal to the number of the third electrodes 510, and each third electrode 510 corresponds to at least one third opening 610. Preferably, the third openings 610 are arranged along the second direction, and the projection of the third opening 610 in the direction of the substrate 100 does not overlap with the projection of the first electrode 310 in the direction of the substrate, nor does it overlap with the projection of the second electrode 320 in the direction of the substrate. In some embodiments, the projection of the third opening 610 in the direction of the substrate 100 coincides with the projection of the first electrode 310 in the direction of the substrate. The number of the fourth openings 620 of the second dielectric layer 600 is greater than or equal to the number of the fourth electrodes 520, and each fourth electrode 520 corresponds to at least one fourth opening 620. The fourth openings 620 are preferably arranged along the second direction, and the projection of the fourth opening 620 in the direction of the substrate 100 does not coincide with the projection of the second electrode 320 in the direction of the substrate 100. In some embodiments, the projection of the fourth opening 620 in the direction of the substrate 100 coincides with the projection of the second electrode 320 in the direction of the substrate 100. In this embodiment, a plurality of third openings 610 are arranged in a row along the second direction, and a plurality of fourth openings 620 are arranged in a row along the second direction, and the row composed of the third openings 610 and the row composed of the fourth openings 620 are arranged relatively far away. It can be understood that if the third electrode 510 and the fourth electrode 520 are both strip structures arranged along the second direction, the third openings 610 and the fourth openings 620 can be arranged along the first direction.

[0059] A first gap is provided between projections of a plurality of first electrodes 310 electrically connected to the same third electrode 510 in the direction of the substrate 100 and on the side of the outermost first electrode 310 away from the other first electrodes 310, and a projection of a third opening 610 corresponding to the third electrode 510 in the direction of the substrate 100 is located within any of the first gaps. A second gap is provided between projections of a plurality of second electrodes 320 electrically connected to the same fourth electrode 520 in the direction of the substrate 100 and on the side of the outermost second electrode 320 away from the other second electrodes 320, and a projection of a fourth opening 620 corresponding to the fourth electrode 520 in the direction of the substrate 100 is located within any of the second gaps.

[0060] The light emitting diode further includes a first pad 710 and a second pad 720 disposed on the second dielectric layer 600. The first pad 710 covers all the third openings 610, and the second pad 720 covers all the fourth openings 620. The shapes of the first pad 710 and the second pad 720 can be set as required. Figure 1 As shown, the first pad 710 and the second pad 720 are both rectangular structures, and the first pad 710 and the second pad 720 are respectively arranged on both sides of the second dielectric layer 600, and the two are not in contact. Preferably, the first pad 710 and the second pad 720 are as large as possible, and the distance between them is as large as possible, so as to facilitate heat dissipation and improve device reliability.

[0061] Figure 4 1 is a flow chart of a method for forming a light emitting diode provided in the first embodiment of the present invention. The method for forming a light emitting diode comprises the following steps:

[0062] Step S100: providing a substrate, and forming an epitaxial layer on the substrate.

[0063] Step S200: forming a through hole in the epitaxial layer.

[0064] Step S300: forming an isolation trench.

[0065] Step S400: forming a current spreading layer.

[0066] Step S500: forming a first electrode and a second electrode.

[0067] Step S600: forming a first dielectric layer.

[0068] Step S700: forming a third electrode and a fourth electrode.

[0069] Step S800: forming a second dielectric layer.

[0070] Step S900: forming a first pad and a second pad.

[0071] Figure 5-Figure 22 Schematic diagram of different stages of the light emitting diode provided by the first embodiment of the utility model. Figure 5 and Figure 6 are the corresponding top view and cross-sectional view, Figure 7 and Figure 8 are the corresponding top view and cross-sectional view, Fig. 9 and Fig.10 are the corresponding top view and cross-sectional view, Fig.11 and Fig.12 are the corresponding top view and cross-sectional view, Fig.13 and Fig.14 are the corresponding top view and cross-sectional view, Fig.15 and Fig.16 are the corresponding top view and cross-sectional view, Fig.17 , Fig.18 and Fig.19 are the corresponding top view and cross-sectional view, Fig. 20 , Fig.21 and Fig. 22 The top view and the cross-sectional view correspond to each other.

[0072] In step S100, a substrate 100 is provided, and an epitaxial layer 200 is formed on the substrate 100. Figure 5 and Figure 6 shown.

[0073] The substrate 100 is a transparent substrate, such as sapphire (Al2O3). The epitaxial layer 200 includes a first semiconductor layer 210, an active layer 220, and a second semiconductor layer 230 stacked from bottom to top on the surface of the substrate 100. The first semiconductor layer 210 and the second semiconductor layer 230 have different doping types. The first semiconductor layer 210 is N-type gallium nitride, and the second semiconductor layer 230 is P-type gallium nitride. The active layer 220 is a multi-quantum well.

[0074] In step S200, a through hole 240 is formed in the epitaxial layer 200, such as Figure 7 and Figure 8 shown.

[0075] A photoresist is coated on the epitaxial layer 200, and then a series of steps such as exposure and development are performed to cure the photoresist in a specific area to form a patterned first mask layer. The second semiconductor layer 230, the active layer 220, and a portion of the first semiconductor layer 210 are etched by dry etching technology to form a through hole 240. After the etching is completed, the remaining first mask layer is removed. Specifically, the epitaxial layer 200 is etched using ICP (Inductively Coupled Plasma) etching technology.

[0076] In step S300, an isolation trench 250 is formed. Fig. 9 and Fig.10 shown.

[0077] A photoresist is coated on the epitaxial layer 200, and then the photoresist in a specific area is cured through a series of steps such as exposure and development to form a patterned second mask layer. A portion of the epitaxial layer 200 is etched by dry etching technology to form an isolation groove 250. After the etching is completed, the remaining second mask layer is removed. Specifically, the epitaxial layer 200 is etched using ICP (Inductively Coupled Plasma) etching technology.

[0078] The isolation trench 250 separates the epitaxial layer 200 into a plurality of units. The bottom of the isolation trench 250 is the surface of the substrate 100, and the sidewalls of at least one side of the isolation trench 250 are the sidewalls of the first semiconductor layer 210, the active layer 220, and the second semiconductor layer 230. That is, the isolation trench 250 penetrates the epitaxial layer 200 and exposes the surface of the substrate 100.

[0079] Step S400, forming a current spreading layer 800. Step S400 specifically includes:

[0080] S401, depositing current spreading material.

[0081] The current spreading material is a transparent conductive material, and the current spreading material can be a metal film system, an oxide film system, other compound film systems, a polymer film system, a composite film system, etc. with high transmittance. Preferably, indium tin oxide (ITO) is used. The current spreading material can be formed by any thin film preparation technology known to those skilled in the art. Preferably, physical vapor deposition (PVD) or plasma enhanced chemical vapor deposition (PECVD) is used to form it, and chemical vapor deposition (CVD) can also be used, such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), atomic layer deposition (ALD) and other methods to deposit the conductive spreading material.

[0082] S402, etching current expansion material, such as Fig.11 and Fig.12 shown.

[0083] A photoresist is coated on the current spreading material, and then a series of steps such as exposure and development are performed to cure the photoresist in a specific area to form a patterned third mask layer. The excess current spreading material is etched using a wet etching technique to form a current spreading layer 800. After the etching is completed, the remaining third mask layer is removed. The formed current spreading layer 800 does not cover the edge area of ​​the second semiconductor layer 230, the interior and the edge of the through hole 240.

[0084] Step S500: forming the first electrode 310 and the second electrode 320. Step S500 specifically includes:

[0085] Step S501 , depositing a fourth mask layer.

[0086] Specifically, photoresist is first coated, and then the photoresist in a specific area is cured through a series of steps such as exposure and development to form a patterned fourth mask layer.

[0087] Step S502: evaporating a first metal layer.

[0088] A first metal layer is formed on the fourth mask layer by physical vapor deposition (PVD), and the first metal layer covers the current spreading layer 800, the second semiconductor layer 230, and the first semiconductor layer 210 exposed from the through hole 240. The first metal layer is made of one or more materials selected from chromium (Cr), aluminum (Al), and titanium (Ti). Preferably, the first metal layer includes a Cr layer, an Al layer, a Ti layer, an Al layer, and a Ti layer stacked in sequence from bottom to top.

[0089] Step S503: remove the redundant first metal layer to form the first electrode 310 and the second electrode 320. Fig.13 and Fig.14 shown.

[0090] The excess first metal layer is removed by metal lift-off technology, and the remaining first metal layer forms the first electrode 310 and the second electrode 320. The first electrode 310 is disposed on the first semiconductor layer 210 exposed from the through hole 240 and forms an ohmic contact with the first semiconductor layer 210, and the second electrode 320 is disposed on the current spreading layer 800 and forms an ohmic contact with the current spreading layer 800.

[0091] Step S600: forming a first dielectric layer 400. Step S600 specifically includes:

[0092] Step S601: depositing a first dielectric material.

[0093] When the first dielectric layer 400 is a SiO2 film, the first dielectric material is grown by plasma enhanced chemical vapor deposition (PECVD) or electron beam evaporation (E-beam). The thickness of the first dielectric material is, for example,

[0094] When the first dielectric layer 400 is a DBR reflector, an electron beam evaporator is used to evaporate alternately stacked SiO2 and Ti3O5 layers to form the first dielectric material.

[0095] When the first dielectric layer 400 is a stacked SiO2 film and a DBR reflector, the SiO2 layer is first grown by plasma enhanced chemical vapor deposition (PECVD) or electron beam evaporation (E-beam), and then the alternately stacked SiO2 and Ti3O5 layers are evaporated by an electron beam evaporator.

[0096] Step S602: etching the first dielectric material to form a first opening 410 and a second opening 420. Fig.15 and Fig.16 shown.

[0097] A photoresist is coated on the first dielectric material, and then a series of steps such as exposure and development are performed to cure the photoresist in a specific area to form a patterned fifth mask layer. The first dielectric material is etched into a first dielectric layer 400 having a first opening 410 and a second opening 420 by dry etching technology, such as plasma etching (Plasma-Enhanced Chemical Vapor Deposition, PECVD) using CF4 gas. After the etching is completed, the remaining fifth mask layer is removed.

[0098] Step S700: forming the third electrode 510 and the fourth electrode 520. Step S700 specifically includes:

[0099] Step S701 , depositing a sixth mask layer.

[0100] Specifically, photoresist is first coated, and then the photoresist in a specific area is cured through a series of steps such as exposure and development to form a patterned sixth mask layer.

[0101] Step S702: evaporating a second metal layer.

[0102] The second metal layer is deposited on the sixth mask layer by an electron beam evaporation machine. The second metal layer covers the first dielectric layer 400 and covers the first electrode 310 exposed from the first opening 410 and the second electrode 320 exposed from the second opening 420. The second metal layer is formed by alternately stacking Al layers and Ti layers on the side close to the first electrode 310 and the second electrode 320. A metal reflective layer with high reflectivity is used, such as gold, silver, copper, aluminum, etc.

[0103] Step S703: remove the redundant metal layer to form the third electrode 510 and the fourth electrode 520. Fig.17 , Fig.18 and Fig.19 shown.

[0104] The excess second metal layer is removed by metal lift-off technology, and the remaining second metal layer forms a third electrode 510 and a fourth electrode 520. The third electrode 510 covers the first opening 410 and is electrically connected to the first electrode 310 exposed from the first opening 410, and the fourth electrode 520 covers the second opening 420 and is electrically connected to the second electrode 320 exposed from the second opening 420. The third electrode 510 and the fourth electrode 520 are not in contact with each other.

[0105] Step S800: forming a second dielectric layer 600. Step S800 specifically includes:

[0106] S801 , depositing a second dielectric material.

[0107] The second dielectric material can be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination of one or more layers, preferably a silicon oxide layer. The second dielectric material can be formed by any thin film preparation technology known to those skilled in the art. Preferably, the second dielectric material is deposited by plasma enhanced chemical vapor deposition (PECVD). The thickness of the second dielectric material is, for example,

[0108] Step S802: etching the second dielectric material to form a third opening 610 and a fourth opening 620. Fig. 20 , Fig.21 and Fig. 22 shown.

[0109] A photoresist is coated on the second dielectric material, and then the photoresist in a specific area is cured through a series of steps such as exposure and development to form a patterned seventh mask layer. The second dielectric material is etched into a second dielectric layer 600 having a third opening 610 and a fourth opening 620 by dry etching technology. After the etching is completed, the remaining seventh mask layer is removed.

[0110] Step S900: forming a first pad 710 and a second pad 720. Step S900 specifically includes:

[0111] Step S901 , depositing an eighth mask layer.

[0112] Specifically, photoresist is first coated, and then the photoresist in a specific area is cured through a series of steps such as exposure and development to form a patterned eighth mask layer.

[0113] Step S902: evaporating a third metal layer.

[0114] The third metal layer is deposited on the eighth mask layer by using an electron beam evaporator. The third metal layer covers the second dielectric layer 600 , the third electrode 510 exposed from the third opening 610 , and the fourth electrode 520 exposed from the fourth opening 620 .

[0115] Step S903: remove the redundant metal layer to form the first pad 710 and the second pad 720. Figure 1 , Figure 2 and Figure 3 shown.

[0116] The excess third metal layer is stripped and removed by the metal stripping technology, and the remaining third metal layer forms a first pad 710 and a second pad 720. The first pad 710 covers all the third openings 610 and is electrically connected to the third electrode 510 exposed from the third openings 610, and the second pad 720 covers all the fourth openings 620 and is electrically connected to the fourth electrode 620 exposed from the fourth openings 620. The first pad 710 and the second pad 720 are not in contact with each other.

[0117] Then, thinning and grinding are performed, and the isolation groove 250 is cleaved and cut to obtain a plurality of light emitting diode dies.

[0118] The embodiment of the utility model discloses a light-emitting diode, which optimizes the arrangement position of the through hole, the first electrode and the second electrode, improves the electron-hole combination efficiency of the light-emitting diode, and achieves the purpose of improving the photoelectric conversion efficiency by improving the light output and reducing the heat energy. In addition, by setting a third electrode and a fourth electrode with equal minimum width, the third electrode is set along the first direction and covers a row of first electrodes, the fourth electrode is set along the first direction and covers a row of second electrodes, and the first pad connecting all the third electrodes and the second pad connecting all the fourth electrodes, the electrical connection mode of the light-emitting diode and its metal structure are optimized, the stress release of the light-emitting diode is improved, the light output rate and the maximum tolerable stress of the product are increased, thereby achieving the purpose of improving the photoelectric conversion efficiency and high reliability of the product.

[0119] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A light emitting diode, characterized in that: The light emitting diode comprises: substrate; an epitaxial layer, located on the substrate, the epitaxial layer comprising a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence from bottom to top, the first semiconductor layer and the second semiconductor layer having different doping types, the epitaxial layer having a plurality of through holes penetrating the second semiconductor layer and the active layer and exposing the first semiconductor layer, the through holes being arranged in an array; A plurality of first electrodes, respectively located on the surface of the first semiconductor layer exposed by the through holes; A plurality of second electrodes are arranged in an array on the second semiconductor layer; A first dielectric layer, covering the epitaxial layer, the first electrode and the second electrode, the first dielectric layer having a plurality of first openings exposing the first electrode and a plurality of second openings exposing the second electrode; a plurality of third electrodes, located on the first dielectric layer and covering the first openings, wherein one of the third electrodes covers a row of the first openings arranged along a first direction; and A plurality of fourth electrodes, located on the first dielectric layer and covering the second openings, wherein one of the fourth electrodes covers a row of the second openings arranged along the first direction; The third electrode and the fourth electrode have the same minimum size along the second direction.

2. The light emitting diode according to claim 1, characterized in that: A plurality of the first electrodes are arranged in a plurality of rows along the first direction, and the plurality of rows of the first electrodes are arranged at intervals along the second direction; a plurality of the second electrodes are arranged in a plurality of rows along the first direction, and the plurality of rows of the second electrodes are arranged at intervals along the second direction; a row composed of a plurality of the second electrodes arranged at intervals along the first direction and a row composed of a plurality of the first electrodes arranged at intervals along the first direction are alternately arranged along the second direction, and the first electrodes and the second electrodes of two adjacent rows are staggered in the first direction; and / or, A plurality of the first electrodes are arranged into a plurality of columns along the second direction, and the plurality of columns of the first electrodes are spaced apart along the first direction; a plurality of the second electrodes are arranged into a plurality of columns along the second direction, and the plurality of columns of the second electrodes are spaced apart along the first direction; a column composed of a plurality of the second electrodes spaced apart along the second direction and a column composed of a plurality of the first electrodes spaced apart along the second direction are alternately arranged along the first direction, and the first electrodes and the second electrodes of two adjacent columns are staggered with each other in the second direction.

3. The light emitting diode according to claim 1, characterized in that: The sizes of the third electrode and the fourth electrode along the second direction are the same everywhere.

4. The light emitting diode according to claim 1, characterized in that: The third electrode and the fourth electrode both include a strip structure extending along the first direction, a wavy structure, a broken line structure, a strip structure with rounded corners, and a strip structure with protrusions and / or depressions at a predetermined position. The shapes of the third electrode and the fourth electrode are the same or different.

5. The light emitting diode according to any one of claims 1, 3 or 4, characterized in that: The size of the third electrode along the second direction is greater than the size of the first opening along the second direction; the size of the fourth electrode along the second direction is greater than the size of the second opening along the second direction.

6. The light emitting diode according to claim 5, characterized in that: A size of the third electrode along the second direction is greater than a size of the first electrode along the second direction, and a size of the fourth electrode along the second direction is greater than a size of the second electrode along the second direction.

7. The light emitting diode according to claim 1, characterized in that: The first dielectric layer is a SiO2 film or a DBR reflector or a SiO2 film and a DBR reflector stacked from bottom to top.

8. The light emitting diode according to claim 1, characterized in that: The light emitting diode further comprises: a second dielectric layer, covering the first dielectric layer, the third electrode and the fourth electrode, the second dielectric layer having a plurality of third openings exposing the third electrode and a plurality of fourth openings exposing the fourth electrode; A first pad, located on the second dielectric layer and covering all of the third openings; and The second pad is located on the second dielectric layer and covers all the fourth openings.

9. The light emitting diode according to claim 8, characterized in that: The third opening is arranged corresponding to the third electrode, and a plurality of the third openings are arranged along the second direction; the fourth opening is arranged corresponding to the fourth electrode, and a plurality of the fourth openings are arranged along the second direction.

10. The light emitting diode according to claim 1, characterized in that: The light emitting diode further includes a current spreading layer disposed on the second semiconductor layer, a projection boundary of the current spreading layer toward the substrate is located within a projection boundary of the second semiconductor layer toward the substrate, and the second electrode is disposed on the current spreading layer.

11. The light emitting diode according to claim 8, characterized in that: Each of the third electrodes corresponds to at least one of the third openings, and each of the fourth electrodes corresponds to at least one of the fourth openings.

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