Time-division multiplexing video interface control circuit and device
By designing a time-divided and multiplexable video interface control circuit in the FPGA module, and using the switching control module and the logic control module to realize the time-divided multiplexed video interface, the problem of limited pin resources of the FPGA module is solved and production costs are reduced.
Patent Information
- Application Number
- CN202420935453.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-30
- Publication Date
- 2025-01-03
- Estimated Expiration
- 2034-04-30
AI Technical Summary
The pin resources of the FPGA module are limited, which leads to the need to replace more pins when the interface increases, which increases production costs.
A video interface control circuit that can be time-divided and multiplexed is designed. By switching the combination of control module, FPGA module, logic control module and video input interface module, time-divided and multiplexed video interfaces is realized, reducing the pins of the FPGA module. use.
Effectively reduces the pin usage of FPGA modules and reduces production costs.
Smart Images
Figure CN222301869U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of video technology, in particular to a video interface control circuit and device capable of time-division multiplexing. Background Art
[0002] FPGA (Field Programmable Gate Array) is a product that is further developed on the basis of programmable devices such as PAL (Programmable Array Logic) and GAL (General Array Logic). It appears as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.
[0003] In the prior art, the pin resources of FPGA are limited. Once the interface is increased, corresponding pins are required for connection, which will result in the need to replace FPGA devices with more pins, thus raising higher requirements on cost. Therefore, it is an urgent problem for technicians in this field to propose a video interface circuit and device that can be used in time division. Utility Model Content
[0004] The purpose of this application is to provide a video interface control circuit and device that can be time-division multiplexed. In this solution, the use of FPGA module pins can be effectively reduced, and the production cost can be effectively reduced.
[0005] In order to solve the above technical problems, the present application provides a time-division multiplexed video interface control circuit, including a switching control module, an FPGA module, a first logic control module, a first video input interface module and a second video input interface module;
[0006] The host computer is electrically connected to the switching control module, the switching control module is electrically connected to the first logic control module, the first logic control module is electrically connected to the FPGA module, and the first logic control module is electrically connected to the first video input interface module and the second video input interface module respectively.
[0007] Preferably, the time-division multiplexed video interface control circuit further comprises a second logic control module, a third video input interface module and a fourth video input interface module;
[0008] The second logic control module is electrically connected to the switching control module and the FPGA module respectively, and the second logic control module is electrically connected to the third video input interface module and the fourth video input interface module respectively.
[0009] Preferably, the time-division multiplexed video interface control circuit further comprises a third logic control module, a fifth video input interface module and a sixth video input interface module;
[0010] The third logic control module is electrically connected to the switching control module and the FPGA module respectively, and the third logic control module is electrically connected to the fifth video input interface module and the sixth video input interface module respectively.
[0011] Preferably, the switching control module is configured as an MCU module.
[0012] Preferably, the first logic control module includes a clock data logic control unit and a video data logic control unit;
[0013] The clock data logic control unit is electrically connected to the switching control module and the FPGA module respectively, and the video data logic control unit is electrically connected to the switching control module and the FPGA module respectively.
[0014] Preferably, the video data logic control unit includes a voltage division subunit and a first logic control subunit;
[0015] The voltage divider subunit is electrically connected to the power input terminal and the first logic control subunit respectively, and the first logic control subunit is electrically connected to the switching control module, the FPGA module, the first video input interface module and the second video input interface module respectively.
[0016] Preferably, the voltage dividing subunit comprises a first resistor and a second resistor;
[0017] The first end of the first resistor is electrically connected to the power input end and the first logic control subunit respectively, the second end of the first resistor is electrically connected to the first logic control subunit and the first end of the second resistor respectively, and the second end of the second resistor is grounded.
[0018] Preferably, the model of the first logic control subunit is set to 74CBTLV3257PWR.
[0019] In order to solve the above technical problems, the present application provides a time-division multiplexed video interface control device, including the above-mentioned time-division multiplexed video interface control circuit.
[0020] The utility model discloses a time-division multiplexed video interface control circuit and device, which has the following beneficial effects: the utility model discloses a time-division multiplexed video interface control circuit, which includes a switching control module, an FPGA module, a first logic control module, a first video input interface module, and a second video input interface module; the host computer is electrically connected to the switching control module, the switching control module is electrically connected to the first logic control module, the first logic control module is electrically connected to the FPGA module, and the first logic control module is electrically connected to the first video input interface module and the second video input interface module, respectively. Therefore, the utility model can effectively reduce the use of FPGA module pins and effectively reduce production costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the utility model will be further described below in conjunction with the accompanying drawings and embodiments. The drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work:
[0022] Figure 1 It is a schematic diagram of the principle block diagram of a time-division multiplexed video interface control circuit of a preferred embodiment of the utility model;
[0023] Figure 2 It is a schematic block diagram of a time-division multiplexed video interface control circuit according to another preferred embodiment of the utility model;
[0024] Figure 3 It is a schematic block diagram of a time-division multiplexed video interface control circuit according to another preferred embodiment of the utility model;
[0025] Figure 4 This is a circuit schematic diagram of a clock data logic control unit of a preferred embodiment of the utility model;
[0026] Figure 5 The utility model is a circuit diagram of a video data logic control unit in a preferred embodiment. DETAILED DESCRIPTION
[0027] The core of this application is to provide a video interface control circuit and device that can be used in time-sharing mode. In this solution, the use of FPGA module pins can be effectively reduced, effectively reducing production costs.
[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0029] See also Figure 1 , Figure 1 A schematic block diagram of a time-division multiplexed video interface control circuit provided in the present application, comprising a switching control module 1, an FPGA module 2, a first logic control module 3, a first video input interface module 4 and a second video input interface module 5;
[0030] The host computer is electrically connected to the switching control module 1, the switching control module 1 is electrically connected to the first logic control module 3, the first logic control module 3 is electrically connected to the FPGA module 2, and the first logic control module 3 is electrically connected to the first video input interface module 4 and the second video input interface module 5 respectively.
[0031] In the prior art, the pin resources of FPGA are limited. Once the interface is increased, corresponding pins are required for connection, which will result in the need to replace FPGA devices with more pins, thus placing higher demands on costs.
[0032] In view of the above shortcomings, in the present application, time-division multiplexing of the video interface is achieved through the cooperation of the switching control module 1, the FPGA module 2, the first logic control module 3, the first video input interface module 4 and the second video input interface module 5.
[0033] Specifically, when there are multiple video input sources, the prior art needs to simultaneously connect multiple video source signals to the FPGA module 2 for image processing. In this embodiment, the first logic control module 3 receives 2 video source signals, and through the cooperation between the switching control module 1 and the first logic control module 3, the switching control module 1 controls the selection pin of the first logic control module 3 to achieve time-division multiplexing, so that only one video source signal is connected to the pin of the FPGA module 2 each time, thereby reducing the use of pins of the FPGA module 2 and reducing production costs.
[0034] Specifically, in this embodiment, the host computer sends a control instruction to the switching control module 1 to select one of the video sources in the first video input interface module 4 and the second video input interface module 5 as input. The switching control module 1 receives the instruction and configures the strobe of the first logic control module 3, and selects the configuration bit to logic 0 or logic 1 according to the video source, so that the 2-to-1 function of the first logic control module 3 is effective.
[0035] In summary, the present application provides a time-division multiplexed video interface control circuit, which includes a switching control module 1, an FPGA module 2, a first logic control module 3, a first video input interface module 4, and a second video input interface module 5; the host computer is electrically connected to the switching control module 1, the switching control module 1 is electrically connected to the first logic control module 3, the first logic control module 3 is electrically connected to the FPGA module 2, and the first logic control module 3 is electrically connected to the first video input interface module 4 and the second video input interface module 5. Therefore, the present utility model can effectively reduce the use of the pins of the FPGA module 2 and effectively reduce the production cost.
[0036] Based on the above embodiments:
[0037] Please refer to Figure 2 , Figure 2 A schematic block diagram of a time-division multiplexed video interface control circuit provided in the present application.
[0038] As a preferred embodiment, a time-division multiplexed video interface control circuit further includes a second logic control module 6, a third video input interface module 7 and a fourth video input interface module 8;
[0039] The second logic control module 6 is electrically connected to the switching control module 1 and the FPGA module 2 respectively, and the second logic control module 6 is electrically connected to the third video input interface module 7 and the fourth video input interface module 8 respectively.
[0040] As a preferred embodiment, a time-division multiplexed video interface control circuit further includes a third logic control module, a fifth video input interface module and a sixth video input interface module;
[0041] The third logic control module is electrically connected to the switching control module 1 and the FPGA module 2 respectively, and the third logic control module is electrically connected to the fifth video input interface module and the sixth video input interface module respectively.
[0042] Specifically, in this embodiment, one logic control module is configured with two video input interface modules, and the video input interface modules are used to receive video source signals. The number of video source signals can be set as needed and is not specifically limited here.
[0043] Please refer to Figure 3 , Figure 3 A schematic block diagram of another time-division multiplexed video interface control circuit provided in the present application.
[0044] As a preferred embodiment, the switching control module 1 is configured as an MCU module.
[0045] Specifically, the switching control module 1 may also be configured as other existing switching control devices, and the model of the switching control module 1 is not specifically limited herein.
[0046] Please refer to Figure 4 , Figure 4 This is a circuit schematic diagram of the clock data logic control unit provided in this application.
[0047] Please refer to Figure 5 , Figure 5 This is a circuit schematic diagram of the video data logic control unit provided in this application.
[0048] As a preferred embodiment, the first logic control module 3 includes a clock data logic control unit 31 and a video data logic control unit 32;
[0049] The clock data logic control unit 31 is electrically connected to the switching control module 1 and the FPGA module respectively, and the video data logic control unit 32 is electrically connected to the switching control module 1 and the FPGA module respectively.
[0050] Specifically, in this embodiment, the clock data logic control unit 31 is used to implement the logic switching of the clock and control signals of the two video source signals, and the video data logic control unit 32 is used to implement the switching of the video transmission signals of the two video source signals.
[0051] As a preferred embodiment, the video data logic control unit 32 includes a voltage division subunit 321 and a first logic control subunit 322;
[0052] The voltage divider subunit 321 is electrically connected to the power input terminal and the first logic control subunit 322 respectively. The first logic control subunit 322 is electrically connected to the switching control module 1, the FPGA module 2, the first video input interface module 4 and the second video input interface module 5 respectively.
[0053] As a preferred embodiment, the voltage dividing subunit 321 includes a first resistor R902 and a second resistor R901;
[0054] The first end of the first resistor R902 is electrically connected to the power input end and the first logic control subunit 322 respectively. The second end of the first resistor R902 is electrically connected to the first logic control subunit 322 and the first end of the second resistor R901 respectively. The second end of the second resistor R901 is grounded.
[0055] As a preferred embodiment, the model of the first logic control subunit is set to 74CBTLV3257PWR, and the model of the clock data logic control unit is set to 74CBTLV3257PWR. In another preferred embodiment, the models of the first logic control subunit and the clock data logic control unit are not specifically limited.
[0056] The present application also provides a time-division multiplexed video interface control device, comprising the time-division multiplexed video interface control circuit.
[0057] For an introduction to a time-division multiplexed video interface control circuit provided in the present application, please refer to the above-mentioned embodiment, and the present application will not go into details here.
[0058] It should be noted that, in this specification, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.
[0059] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A time-division multiplexed video interface control circuit, characterized in that: It includes a switching control module, an FPGA module, a first logic control module, a first video input interface module and a second video input interface module; The host computer is electrically connected to the switching control module, the switching control module is electrically connected to the first logic control module, the first logic control module is electrically connected to the FPGA module, and the first logic control module is electrically connected to the first video input interface module and the second video input interface module respectively.
2. A time-division multiplexed video interface control circuit according to claim 1, characterized in that: The time-division multiplexed video interface control circuit further comprises a second logic control module, a third video input interface module and a fourth video input interface module; The second logic control module is electrically connected to the switching control module and the FPGA module respectively, and the second logic control module is electrically connected to the third video input interface module and the fourth video input interface module respectively.
3. A time-division multiplexed video interface control circuit according to claim 1, characterized in that: The time-division multiplexed video interface control circuit further comprises a third logic control module, a fifth video input interface module and a sixth video input interface module; The third logic control module is electrically connected to the switching control module and the FPGA module respectively, and the third logic control module is electrically connected to the fifth video input interface module and the sixth video input interface module respectively.
4. The time-division multiplexed video interface control circuit according to claim 1, characterized in that: The switching control module is configured as an MCU module.
5. The time-division multiplexed video interface control circuit according to claim 1, characterized in that: The first logic control module includes a clock data logic control unit and a video data logic control unit; The clock data logic control unit is electrically connected to the switching control module and the FPGA module respectively, and the video data logic control unit is electrically connected to the switching control module and the FPGA module respectively.
6. A time-division multiplexed video interface control circuit according to claim 5, characterized in that: The video data logic control unit includes a voltage division subunit and a first logic control subunit; The voltage divider subunit is electrically connected to the power input terminal and the first logic control subunit respectively, and the first logic control subunit is electrically connected to the switching control module, the FPGA module, the first video input interface module and the second video input interface module respectively.
7. A time-division multiplexed video interface control circuit according to claim 6, characterized in that: The voltage dividing subunit includes a first resistor and a second resistor; The first end of the first resistor is electrically connected to the power input end and the first logic control subunit respectively, the second end of the first resistor is electrically connected to the first logic control subunit and the first end of the second resistor respectively, and the second end of the second resistor is grounded.
8. The time-division multiplexed video interface control circuit according to claim 6, characterized in that: The model of the first logic control subunit is set to 74CBTLV3257PWR.
9. A video interface control device capable of time division multiplexing, characterized in that: A time-division multiplexed video interface control circuit comprising the circuit described in any one of claims 1 to 8.