Data acquisition and processing circuit and equipment thereof
By designing the data acquisition and processing circuit of a multi-core processing architecture, the ZYNQ chip and DSP chip are used to realize the synchronous acquisition and real-time processing of multiple data, the problems of data acquisition delay and signal distortion in the existing technology are solved, and the data processing efficiency is improved and transmission rate, adapted to the communication interface for industrial measurement.
Patent Information
- Application Number
- CN202420932558.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-29
- Publication Date
- 2025-01-07
- Estimated Expiration
- 2034-04-29
AI Technical Summary
The existing synchronous acquisition circuit cannot meet the requirements of high-speed data acquisition, and there is signal distortion and noise, high computational complexity and high power consumption, resulting in increased data processing delays and cannot meet the real-time data processing requirements of industrial measurements.
A circuit including data acquisition, data synchronization transmission and data processing module was designed, and the ZYNQ chip and DSP chip were used to perform multi-channel data synchronization acquisition and real-time processing, clock synchronization and algorithm operations were realized through FPGA and ARM modules, and a multi-core processing architecture was adopted. and high-performance interface protocols to ensure data synchronization and real-time.
It realizes synchronous acquisition and real-time processing of multiple high-speed data, reduces signal distortion and noise, improves data processing efficiency, reduces delay, supports high-performance communication interfaces, adapts to commonly used communication interfaces for industrial measurement, and improves data Transmission rate.
Smart Images
Figure CN222319451U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of high-speed data synchronous acquisition and digital signal processing, and in particular to a circuit and device for data acquisition and processing. Background Art
[0002] Multi-channel synchronous data acquisition and digital signal processing play an important role in industrial measurement. At present, most synchronous acquisition circuits in the industry cannot fully meet the requirements of industrial measurement. Specifically, they include: 1. There are sampling rate limitations, which cannot meet certain high-speed or real-time application requirements. 2. Signal distortion and noise are inevitable. Due to factors such as circuit design, sensor quality and production environment, the signal quality is reduced, making the collected signal data inaccurate and unreliable. 3. Lack of high-speed data processing capabilities. Industrial measurement usually requires real-time data processing and algorithm operations on the collected high-speed signals.
[0003] At the same time, existing digital signal processing circuits also have some shortcomings and challenges, including: 1. Algorithm complexity. The computational complexity of some DSP algorithms is very high and requires a lot of computing resources, which leads to increased circuit costs and increased algorithm difficulty. 2. Computational delay issues. Some DSP algorithms have a long processing time, which leads to increased delays in high-speed signal processing, which is unacceptable in some real-time measurements. 3. Performance and power consumption. High-performance DSP processors usually have high power consumption. For measuring equipment or circuits, long-term high power consumption operation will shorten their service life. Utility Model Content
[0004] The main technical problem solved by the present application is to provide a data acquisition and processing circuit that supports multi-channel data acquisition and can process data in real time, and a device equipped with the circuit.
[0005] In a first aspect, an embodiment of the present application provides a circuit for data acquisition and processing, comprising:
[0006] Data acquisition module, used to obtain multiple channels of raw data;
[0007] A data synchronization transmission module, connected to the data acquisition module, is used to perform clock synchronization on multiple channels of original data to obtain synchronized data;
[0008] A data processing module, connected to the data synchronization transmission module, the data processing module is used to obtain the synchronization data, output algorithm data corresponding to the synchronization data, and send the algorithm data to the data synchronization transmission module;
[0009] The communication module is connected to the data synchronization transmission module to obtain the synchronization data and algorithm data for communication transmission.
[0010] According to an embodiment of the first aspect, the data acquisition module includes:
[0011] An analog quantity acquisition module, wherein the analog quantity acquisition module is used to acquire analog quantity data;
[0012] An encoder acquisition module, wherein the encoder acquisition module is used to acquire encoder data;
[0013] A digital quantity acquisition module is used to acquire digital quantity data.
[0014] According to an embodiment of the first aspect, the data synchronization transmission module includes:
[0015] A data synchronization module, the data synchronization module includes a filtering module and a data synchronization submodule; the input end of the filtering module is connected to the analog quantity acquisition module to filter the analog quantity data; the input end of the data synchronization submodule is connected to the filtering module, the encoder acquisition module and the digital quantity acquisition module to obtain the filtered analog quantity data, encoder data and digital quantity data, and perform clock synchronization on the filtered analog quantity data, encoder data and digital quantity data to generate the synchronization data;
[0016] A first interface transmission module, wherein an input end of the first interface transmission module is connected to a first output end of the data synchronization module, and an output end of the first interface transmission module is connected to the data processing module, and is used to send the synchronization data to the data processing module;
[0017] A high-speed interface module, wherein the first input end of the high-speed interface module is connected to the second output end of the data synchronization module to obtain the synchronization data; the second input end of the high-speed interface module is connected to the data processing module to obtain the algorithm data; the output end of the high-speed interface module is connected to the communication module to send the synchronization data and algorithm data.
[0018] According to an embodiment of the first aspect, the data processing module includes:
[0019] A memory module, the memory module is connected to the first interface transmission module, and the memory module is used to obtain the synchronization data and output the algorithm data;
[0020] A second interface transmission module, wherein the input end of the second interface transmission module is connected to the memory module, and the output end of the second interface transmission module is connected to the data synchronization transmission module to send the algorithm data to the data synchronization transmission module.
[0021] According to an embodiment of the first aspect, the data synchronization transmission module further includes an ARM module, and the ARM module is connected to the high-speed interface module to store the synchronization data and algorithm data.
[0022] According to an embodiment of the first aspect, the circuit also includes a logic control module, which is connected to the data synchronization module to control the cutoff frequency of the filtering module; the logic control module is also connected to the high-speed interface module to control the transmission rate of the synchronization data and algorithm data sent by the high-speed interface module to the communication module; the logic control module is also connected to the data acquisition module to control the sampling parameters of the data acquisition module.
[0023] According to an embodiment of the first aspect, the encoder acquisition module and the digital quantity acquisition module both include an optocoupler isolation module to electrically isolate the encoder data from the digital quantity data.
[0024] According to an embodiment of the first aspect, the data synchronization transmission module copies the synchronization data into two paths, one path is output to the data processing module, and the other path is output to the communication module.
[0025] According to an embodiment of the first aspect, the data synchronization transmission module includes an XC7Z7020 chip, and the data processing module includes a TMS320C6748 chip.
[0026] In a second aspect, an embodiment of the present application provides a device for data acquisition and processing, and the device for data acquisition and processing adopts the data acquisition and processing circuit described in any one of the above embodiments.
[0027] According to the data acquisition and processing circuit and the device thereof of the above embodiment, the circuit includes a data acquisition module, a data synchronization transmission module, a data processing module and a communication module. The data acquisition module is used to realize the acquisition of multiple channels of original data, and the data synchronization transmission module is used to process the original data to obtain synchronization data, and the real-time transmission of the synchronization data is guaranteed. The data processing module is used to process the synchronization data in real time to generate algorithm data, and the algorithm data is then sent to the data synchronization transmission module, and finally the communication module is used to send the algorithm data and synchronization data to the host computer, thereby ensuring the synchronization of the synchronization data and the real-time nature of the algorithm data, and providing technical support for industrial measurement. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 A schematic diagram of the structure of a data acquisition and processing circuit according to an embodiment;
[0029] Figure 2 A circuit connection diagram of a data acquisition and processing circuit of an embodiment;
[0030] Figure 3 A schematic diagram of the structure of a ZYNQ chip in a data acquisition and processing circuit according to an embodiment. DETAILED DESCRIPTION
[0031] The present application is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments adopt associated similar element numbers. In the following embodiments, many detailed descriptions are intended to enable the present application to be better understood. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, and methods. In some cases, some operations related to the present application are not shown or described in the specification, in order to avoid the core part of the present application being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations based on the description in the specification and the general technical knowledge in the art.
[0032] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various implementations. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a required sequence, unless otherwise specified that a certain sequence must be followed.
[0033] The serial numbers of the components in this document, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings).
[0034] The present application provides a data acquisition and processing circuit that can synchronously acquire multi-channel analog data, encoder data and digital data, can support multi-channel high-speed data synchronous acquisition, and can process data in real time, ensuring real-time control and real-time monitoring of data in industrial measurement. The present application designs the circuit according to the on-site requirements of industrial measurement, and specifically includes a data acquisition module, a data synchronous transmission module, a data processing module and a communication module. The data acquisition module is mainly responsible for high-speed data conversion at the industrial measurement site, the data synchronous transmission module is responsible for high-speed data transmission and synchronization, the data processing module is responsible for digital signal processing of high-speed data, and the communication module is responsible for sending data. The measured signal is connected to the data acquisition module through an industrial cable, processed by the data processing module, and finally transmitted to the host computer or connected to other communication devices through a gigabit network cable, thereby ensuring the synchronization of the synchronous data and the real-time of the algorithm data, and providing technical support for industrial measurement, which is specifically described below.
[0035] Please refer to Figure 1 A data acquisition and processing circuit provided in an embodiment includes a data acquisition module 100, a data synchronization transmission module 200, a data processing module 300, a communication module 400 and a logic control module 500.
[0036] In one embodiment, the data acquisition module 100 includes an analog quantity acquisition module 110 , an encoder acquisition module 120 and a digital quantity acquisition module 130 .
[0037] In one embodiment, the analog quantity acquisition module 110 is used to acquire multiple analog quantity data. The analog quantity acquisition module 110 includes an analog quantity input part and an analog quantity acquisition part. While the analog quantity input part converts the current value into a voltage value, it converts the single-ended signal into a differential signal. The analog quantity acquisition part is controlled by the logic control module 500 to set the analog quantity sampling rate and data transmission format and other analog quantity parameter controls. The sampling rate refers to the number of times the analog quantity data is sampled per second. By setting the sampling rate, the sampling frequency of the analog quantity data can be controlled, thereby affecting the time resolution of the collected analog quantity data. The data transmission format determines how the analog quantity data is transmitted and stored after digitization. Among them, the analog quantity acquisition module 110 can use the AD7768 chip, which has 8 channels, 24 bits, 250kSPS, and bipolar input synchronous sampling capabilities.
[0038] In one embodiment, a current-voltage converter may be used in the analog quantity acquisition module 110 to convert the current value into a voltage value. Meanwhile, a differential amplifier may be used in the analog quantity acquisition module 110 to convert the single-ended signal into a differential signal to improve the anti-interference capability of the analog quantity.
[0039] In one embodiment, the encoder acquisition module 120 is used to acquire multiple encoder data. The encoder data is a digital quantity, so an optocoupler isolation module is provided in the encoder acquisition module 120 to electrically isolate the encoder data.
[0040] In one embodiment, the digital quantity acquisition module 130 is used to acquire multiple channels of digital quantity data. An optocoupler isolation module is also provided in the digital quantity acquisition module 130 to electrically isolate the digital quantity data using the optocoupler isolation module.
[0041] In one embodiment, the data synchronization transmission module 200 is connected to the data acquisition module 100 and is used to perform clock synchronization on multiple channels of raw data to obtain synchronized data. The data synchronization transmission module 200 uses a ZYNQ chip, specifically a XC7Z7020 chip.
[0042] Please refer to Figure 3 In one embodiment, the ZYNQ chip is a highly integrated new product, which is part of the Xilinx ZynqSoC, which includes FPGA, AXI bus and ARM. When the data acquisition module adopts an ADC chip, it can be directly connected to the ADC chip, and the highly integrated design simplifies the layout and connection of the system. In addition, the ZYNQ chip has high-speed interfaces, which can provide sufficient bandwidth to process a large amount of raw data sent from the data acquisition module 100. These raw data can be processed in the FPGA in the ZYNQ chip, thereby reducing processing delays and achieving more efficient real-time processing. FPGA provides flexible programming capabilities, and various data processing algorithms can be designed and implemented as needed, which makes the system highly flexible and scalable and can adapt to different application requirements.
[0043] In one embodiment, a data synchronization transmission module 200 is mounted on an FPGA, and the data synchronization transmission module 200 includes a data synchronization module 210 , a first interface transmission module 220 , and a high-speed interface module 230 .
[0044] Please refer to Figure 2 In one embodiment, the data synchronization module 210 includes a filter module 211 and a data synchronization submodule 212. The input end of the filter module 211 is connected to the analog quantity acquisition module 110 to filter the analog quantity data and reduce the noise interference of the industrial site on the analog quantity data. The filter module 211 can use an IIR filter or a FIR filter.
[0045] Please refer to Figure 2In one embodiment, the input end of the data synchronization submodule 212 is connected to the filtering module 211, the encoder acquisition module 120 and the digital quantity acquisition module 130 to obtain the filtered analog data, encoder data and digital data, and perform clock synchronization on the filtered analog data, encoder data and digital data to generate synchronous data to ensure the synchronization and real-time nature of various data.
[0046] In one embodiment, during clock synchronization, a stable clock source can be selected as a reference clock to generate corresponding timestamps for analog data, encoder data, and digital data to mark the acquisition time of the analog data, encoder data, and digital data, and then the analog data, encoder data, and digital data can be synchronized to the reference clock using timestamps or other synchronization mechanisms.
[0047] In one embodiment, after the analog data, encoder data and digital data are synchronized according to the reference clock, the sampling rate of the analog data, encoder data and digital data is synchronized using the mean algorithm. Specifically, the average sampling rate of the analog data, encoder data and digital data is calculated using the mean algorithm, and the sampling interval of the analog data, encoder data and digital data is adjusted according to the calculated average sampling rate to achieve synchronization of the sampling rate.
[0048] Please refer to Figure 2 In one embodiment, the input end of the first interface transmission module 220 is connected to the first output end of the data synchronization module 210, and the output end of the first interface transmission module 220 is connected to the data processing module 300, for sending synchronization data to the data processing module 300, wherein the first interface transmission module 220 can adopt a UPP interface, which is a parallel interface that can transmit data at high speed. The UPP interface is generally used to connect external devices or other processor modules to achieve high-speed data transmission, and is suitable for scenarios that require large bandwidth and high-performance data transmission. In the ZYNQ chip, the UPP interface can be connected to an external data processing module 300 for high-speed data transmission, such as audio, video and other applications.
[0049] Please refer to Figure 2 In one embodiment, the first input end of the high-speed interface module 230 is connected to the second output end of the data synchronization module 210 to obtain synchronization data, the second input end of the high-speed interface module 230 is connected to the data processing module 300 to obtain the algorithm data sent by the data processing module 300, and the output end of the high-speed interface module 230 is connected to the communication module 400 for sending synchronization data and algorithm data. Among them, the high-speed interface module 230 adopts an AXI high-speed interface module. The AXI interface is a high-performance, low-latency, and scalable bus protocol provided by Xilinx, and is often used to connect various IP cores inside FPGA.
[0050] In the ZYNQ chip, the AXI high-speed interface module is mainly used for data transmission, and is responsible for efficiently transmitting and exchanging the algorithm data from the data processing module 300 and the synchronous data after clock synchronization of the multi-channel original data collected by the data acquisition module 100.
[0051] It should be noted that in the ZYNQ chip, the FPGA and ARM are connected using the AXI high-speed interface module, the FPGA obtains synchronization data and algorithm data, and the synchronization data and algorithm data are sent to the ARM module for storage using the AXI high-speed interface module. The ARM module can read and write the BRAM of the FPGA and use the EMIFA (external storage interface simulator) interface to access the external memory, so that different processing algorithms can be selected to process the synchronization data. The ZYNQ chip also sets the chip parameters of the analog quantity acquisition module 110 through the SPI protocol to control the analog quantity data acquisition. In addition, the synchronization data is copied into two paths in the data synchronization transmission module 200, one path is output to the data processing module 300 for data analysis and processing, and the other path is output to the communication module 400 to be directly sent to the host computer. In the actual circuit, the output end of the data synchronization transmission module 200 is divided into two paths, one path is connected to the data processing module 300, and the other path is connected to the communication module 400 to achieve the replication of synchronization data.
[0052] In one embodiment, the data processing module 300 includes a memory module 310 and a second interface transmission module 320. The data processing module 300 uses a DSP chip, specifically a TMS320C6748 chip. DSP chip (digital signal processing) is a technology for processing digital signals, which can be applied in many fields such as audio processing, image processing, communication, radar, medical imaging, etc. DSP chip is mainly used to process synchronous data, perform complex algorithm operations, and transmit the results back to the ZYNQ chip.
[0053] Please refer to Figure 2 In one embodiment, the memory module 310 is connected to the first interface transmission module 220, the memory module 310 obtains the processing algorithm from the ARM module and stores it, the memory module 310 obtains the synchronization data, processes the synchronization data using the processing algorithm, generates algorithm data, and outputs the algorithm data.
[0054] Please refer to Figure 2In one embodiment, the input end of the second interface transmission module 320 is connected to the memory module 310, and the output end of the second interface transmission module 320 is connected to the data synchronization transmission module 200, that is, the output end of the second interface transmission module 320 is connected to the high-speed interface module 230, and the second interface transmission module 320 is used to send the algorithm data to the data synchronization transmission module 200. Among them, the second interface transmission module 320 also adopts the UPP interface transmission module, and the UPP interface transmission module in the second interface transmission module 320 needs to be used together with the first interface transmission module 220 in the data synchronization transmission module 200, and full-duplex communication is used for data transmission.
[0055] It should be noted that the algorithm data is transmitted to the ARM module through the AXI high-speed interface module, C language code is written in the ARM module, the FreeRTOS real-time operating system is transplanted, and the control thread and the communication thread are separated to meet the needs of the industrial site. The control thread sets the FPGA or DSP by reading and writing the BRAM of the FPGA to control the data transmission type and processing algorithm type of the data synchronization transmission module 200 and the data processing module 300. The communication thread receives the algorithm data and synchronization data through the AXI-DMA (direct memory in the ZYNQ chip) technology.
[0056] This application uses the connection between the DSP chip and the ZYNQ chip. Both the ZYNQ chip and the DSP chip have processing capabilities. By connecting them, distributed data processing can be realized. The task of synchronizing data is executed in the ZYNQ chip, and the task of algorithm data is executed in the DSP chip, thereby improving the overall processing capability of the system. In addition, the DSP chip has excellent real-time processing capabilities and low latency characteristics, so the DSP chip can be used to execute tasks of algorithm data with high real-time requirements to ensure the real-time performance of the entire system.
[0057] In one embodiment, the input end of the communication module 400 is connected to the data synchronization transmission module 200, and the output end of the communication module 200 is used to connect to the host computer to upload the algorithm data and the original data to the host computer to facilitate industrial site analysis and display. The LWIP protocol is transplanted in the communication module 400, and the algorithm data and the synchronization data are sent to the host computer through the 485 bus, the 232 bus or the gigabit network port. The LWIP protocol is a lightweight TCP / IP protocol stack that can be transplanted and used on a variety of embedded platforms. This means that no matter what kind of operating system or device the host computer is, as long as it supports the TCP / IP protocol, it can easily communicate with the communication module 400. Data transmission also supports multiple communication interfaces such as 485 bus, 232 bus or gigabit network port, so that the most suitable communication method can be selected according to specific application scenarios and requirements. For example, for long-distance communication, the 485 bus can be selected; for short-distance point-to-point communication, the 232 bus can be selected; for high-speed data transmission, the gigabit network port can be selected.
[0058] In one embodiment, the logic control module 500 is connected to the data synchronization module 210, and controls the cutoff frequency of the filter module 211 through the AXI bus. The logic control module 500 is also connected to the high-speed interface module 230 to control the transmission rate of the synchronization data and algorithm data sent by the high-speed interface module 230 to the communication module 400. The logic control module 500 is also connected to the data acquisition module 100, and controls the sampling parameters of the data acquisition module 100 through the AXI bus. The logic control module 500 communicates and transmits data with other modules through the AXI bus, and the logic control module 500 can realize parameter control of other modules by configuring the AXI interface parameters.
[0059] The data acquisition and processing circuit provided by this application adopts a multi-core processing architecture. The DSP is responsible for algorithm processing and can efficiently perform complex logical operations, solving the problem of insufficient computing power of some synchronous data acquisition boards on the market. As the high-speed data interaction center of the entire circuit system, ZYNQ uses DMA and AXI bus to realize the transparent transmission of synchronous data and algorithm data, ensuring the synchronization of synchronous data and the real-time nature of algorithm data, and providing technical support for industrial measurement. This application improves the data sampling frequency and data transmission rate, and can support multi-channel data synchronous acquisition. Its maximum synchronous upload rate can reach 250K×the total number of data bytes of multiple channels / s. It also supports real-time algorithm data upload, and can adapt to commonly used communication interfaces in industrial measurement, as well as support long-distance transmission.
[0060] In another embodiment, a data acquisition and processing device is provided. The device adopts the data acquisition and processing circuit in any one of the above embodiments. Since the data acquisition and processing circuit has been clearly explained in the above embodiments, it will not be repeated here.
[0061] The above specific examples are used to illustrate the present application, which is only used to help understand the present application and is not intended to limit the present application. For technicians in the technical field to which the present application belongs, they can also make some simple deductions, deformations or substitutions based on the ideas of the present application.
Claims
1. A circuit for data acquisition and processing, characterized in that: include: Data acquisition module, used to obtain multiple channels of raw data; A data synchronization transmission module, connected to the data acquisition module, is used to perform clock synchronization on multiple channels of original data to obtain synchronized data; A data processing module, connected to the data synchronization transmission module, the data processing module is used to obtain the synchronization data, output algorithm data corresponding to the synchronization data, and send the algorithm data to the data synchronization transmission module; The communication module is connected to the data synchronization transmission module to obtain the synchronization data and algorithm data for communication transmission.
2. The data acquisition and processing circuit according to claim 1, characterized in that: The data acquisition module comprises: An analog quantity acquisition module, wherein the analog quantity acquisition module is used to acquire analog quantity data; An encoder acquisition module, wherein the encoder acquisition module is used to acquire encoder data; A digital quantity acquisition module is used to acquire digital quantity data.
3. The data acquisition and processing circuit according to claim 2, characterized in that: The data synchronization transmission module includes: A data synchronization module, the data synchronization module includes a filtering module and a data synchronization submodule; the input end of the filtering module is connected to the analog quantity acquisition module to filter the analog quantity data; the input end of the data synchronization submodule is connected to the filtering module, the encoder acquisition module and the digital quantity acquisition module to obtain the filtered analog quantity data, encoder data and digital quantity data, and perform clock synchronization on the filtered analog quantity data, encoder data and digital quantity data to generate the synchronization data; A first interface transmission module, wherein an input end of the first interface transmission module is connected to a first output end of the data synchronization module, and an output end of the first interface transmission module is connected to the data processing module, and is used to send the synchronization data to the data processing module; A high-speed interface module, wherein the first input end of the high-speed interface module is connected to the second output end of the data synchronization module to obtain the synchronization data; the second input end of the high-speed interface module is connected to the data processing module to obtain the algorithm data; the output end of the high-speed interface module is connected to the communication module to send the synchronization data and algorithm data.
4. The data acquisition and processing circuit according to claim 3, characterized in that: The data processing module comprises: A memory module, the memory module is connected to the first interface transmission module, and the memory module is used to obtain the synchronization data and output the algorithm data; A second interface transmission module, wherein the input end of the second interface transmission module is connected to the memory module, and the output end of the second interface transmission module is connected to the data synchronization transmission module to send the algorithm data to the data synchronization transmission module.
5. The data acquisition and processing circuit as claimed in claim 3, characterized in that: The data synchronization transmission module also includes an ARM module, and the ARM module is connected to the high-speed interface module to store the synchronization data and algorithm data.
6. The data acquisition and processing circuit according to claim 3, characterized in that: The circuit also includes a logic control module, which is connected to the data synchronization module to control the cutoff frequency of the filtering module; the logic control module is also connected to the high-speed interface module to control the transmission rate of the synchronization data and algorithm data sent by the high-speed interface module to the communication module; the logic control module is also connected to the data acquisition module to control the sampling parameters of the data acquisition module.
7. The data acquisition and processing circuit according to claim 2, characterized in that: The encoder acquisition module and the digital quantity acquisition module both include an optical coupling isolation module to electrically isolate the encoder data from the digital quantity data.
8. The data acquisition and processing circuit according to claim 1, characterized in that: The data synchronization transmission module copies the synchronization data into two paths, one of which is output to the data processing module, and the other is output to the communication module.
9. The data acquisition and processing circuit according to claim 1, characterized in that: The data synchronous transmission module includes an XC7Z7020 chip, and the data processing module includes a TMS320C6748 chip.
10. A data collection and processing device, characterized in that: The data acquisition and processing device adopts the data acquisition and processing circuit as described in any one of claims 1-9.