Embedded multi-chip packaging structure
By setting up gaskets in embedded multi-chip packaging structures and using embedded wire bonding technology, the problem of easy replication and insufficient storage density of traditional chip packaging is solved, and higher chip life and performance stability are achieved, and suitable for confidentiality Chip package.
Patent Information
- Application Number
- CN202420124391.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-18
- Publication Date
- 2025-01-07
- Estimated Expiration
- 2034-01-18
AI Technical Summary
Traditional chip packaging technology is easy to be copied by competitors, difficult to apply to confidential chip packaging, and has shortcomings in storage density, lifespan and performance stability.
Using an embedded multi-chip packaging structure, by setting up a gasket between the active chip and the top chip, combining embedded wire bonding technology and gasket stacking, the bottom chip, active chip and top chip are stacked in sequence in the vertical direction, using The plastic sealing material is encapsulated and electrically connected to the substrate through bonding wires.
It improves storage density, enhances chip life and performance stability, and effectively prevents competitors from copying circuit designs, suitable for confidential chip packaging.
Smart Images
Figure CN222320240U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to an embedded multi-chip packaging structure, belonging to the technical field of semiconductor packaging. Background Art
[0002] In traditional chip packaging, chips are stacked and pasted on a packaging substrate or a packaging lead frame, and a packaging interconnection technology is used through wire bonding, injection molding, ball planting, cutting and separation. This packaging technology is already a mature process. It uses a substrate or lead frame as the threshold, and competitors can easily imitate and copy the circuit design. The above solution is not suitable for confidential chip packaging solutions. Utility Model Content
[0003] The utility model aims to provide an embedded multi-chip packaging structure in order to overcome the deficiencies of the prior art.
[0004] To achieve the above-mentioned purpose, the technical solution adopted by the utility model is: an embedded multi-chip packaging structure, comprising a substrate, a bottom chip, an active chip and a top chip; the bottom chip, the active chip and the top chip are stacked on the substrate in sequence along the vertical direction; the bottom chip is mounted on the substrate, and the bottom chip is electrically connected to the substrate through a first welding wire; the active chip is electrically connected to the substrate through a second welding wire; a gasket is arranged between the top chip and the active chip, and the gasket is used to connect the top chip and the active chip, and the top chip is electrically connected to the substrate through a gold wire; the bottom chip, the active chip, the top chip, the first welding wire, the second welding wire and the gold wire are all encapsulated on the substrate through a plastic packaging material.
[0005] Preferably, the active chip has a thin film material, and the active chip is adhered to the bottom chip through the thin film material.
[0006] Preferably, the gasket has no electrical properties.
[0007] Preferably, the lower ends of the first bonding wire, the second bonding wire and the gold wire are all bonded to the bonding pad of the substrate.
[0008] Preferably, a plurality of solder balls are arranged on the lower side of the substrate, and the plurality of solder balls are all soldered to the electroplated solder wire layer of the substrate.
[0009] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:
[0010] An embedded multi-chip packaging structure of the utility model scheme combines the buried wire bonding technology and the gasket stacking by setting a gasket between the active chip and the top chip, so that when the storage density is increased, the chip also has better performance in terms of life, performance, stability, etc. At the same time, it can also effectively prevent competitors from imitating and copying the circuit design, which is suitable for confidential chip packaging. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The technical solution of the utility model is further described below in conjunction with the accompanying drawings:
[0012] Attached Figure 1 This is a structural schematic diagram of an embedded multi-chip packaging structure described in the utility model;
[0013] Attached Figure 2 It is a schematic diagram of step 1 of the processing process described in the utility model;
[0014] Attached Figure 3 It is a schematic diagram of step 2 of the processing process described in the utility model;
[0015] Attached Figure 4 It is a schematic diagram of step three of the processing process described in the utility model;
[0016] Attached Figure 5 It is a schematic diagram of step 4 of the processing process described in the utility model;
[0017] Attached Figure 6 It is a schematic diagram of step five of the processing process described in the utility model.
[0018] In the figure: 1. substrate; 2. bottom chip; 3. active chip; 4. top chip; 5. first welding wire; 6. second welding wire; 7. gasket; 8. gold wire; 9. plastic packaging material; 10. film material; 11. welding pad; 12. solder ball; 13. electroplated welding wire layer. DETAILED DESCRIPTION
[0019] The utility model is further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0020] As attached Figure 1 As shown, an embedded multi-chip packaging structure described in the present invention comprises a substrate 1, a bottom chip 2, an active chip 3 and a top chip 4; the bottom chip 2, the active chip 3 and the top chip 4 are stacked on the substrate 1 in sequence along the vertical direction.
[0021] The bottom chip 2 is mounted on the substrate 1, and the bottom chip 2 is electrically connected to the substrate 1 through the first bonding wire 5; the active chip 3 has a thin film material 10, and the active chip 3 is attached to the bottom chip 2 through the thin film material 10, and the active chip 3 is electrically connected to the substrate 1 through the second bonding wire 6. In this embodiment, the first bonding wire 5 and the second bonding wire 6 are both gold wires, and can also be set to electrical connection materials such as copper wires commonly used in the art.
[0022] A gasket 7 is arranged between the top chip 4 and the active chip 3. The gasket 7 is used to connect the top chip 4 and the active chip 3, and the gasket 7 does not have electrical properties. The top chip 4 is electrically connected to the substrate 1 through a gold wire 8; the bottom chip 2, the active chip 3, the top chip 4, the first welding wire 5, the second welding wire 6 and the gold wire 8 are all encapsulated on the substrate 1 through a plastic encapsulation material 9. In this embodiment, the plastic encapsulation material 9 is epoxy resin.
[0023] The lower ends of the first bonding wire 5 , the second bonding wire 6 and the gold wire 8 are all bonded to the bonding pad 11 of the substrate 1 .
[0024] A plurality of solder balls 12 are disposed on the lower side of the substrate 1 , and the plurality of solder balls 12 are all soldered on the electroplated solder wire layer 13 of the substrate 1 .
[0025] As attached Figure 2-6 As shown, the processing process of the packaging structure of this solution is as follows:
[0026] Step 1: Mount the bottom chip and wire it:
[0027] The bottom chip is mounted on the substrate, and the whole is placed in an oven for baking. After baking, it is cooled to room temperature, and the bottom chip circuit is connected to the substrate using traditional wire bonding technology.
[0028] Step 2: Mounting using wire embedding bonding technology:
[0029] The active chip with thin film material is attached to the bottom chip, and the buried wire bonding technology (film overwire) is used without affecting the bottom wire arc. The second layer chip is connected to the substrate using the traditional wire bonding process (wire bonding).
[0030] Step 3: Mount the gasket and top chip and wire bond:
[0031] The gold wire is electrically connected to the top active chip pad and the substrate end pad, and the gasket is used between the second layer chip and the top layer chip and has no electrical properties.
[0032] Step 4: Plastic sealing:
[0033] The plastic encapsulation material is filled on the substrate carrier to protect the internal active chips and bonding wires.
[0034] Step 5: Planting the ball:
[0035] The solder balls are soldered onto the electroplated wire layer of the ball planting pad on the back of the substrate carrier.
[0036] The advantages of the embedded multi-chip packaging structure described in the present invention are that, when the storage density is increased, the chip also has better performance in terms of life, performance, stability, etc.
[0037] The above are only specific application examples of the utility model and do not constitute any limitation to the protection scope of the utility model; any technical solutions formed by equivalent transformation or equivalent replacement shall fall within the protection scope of the utility model.
Claims
1. An embedded multi-chip packaging structure, characterized in that: The invention comprises a substrate (1), a bottom chip (2), an active chip (3) and a top chip (4); the bottom chip (2), the active chip (3) and the top chip (4) are stacked on the substrate (1) in sequence along a vertical direction; the bottom chip (2) is mounted on the substrate (1), and the bottom chip (2) is electrically connected to the substrate (1) via a first welding wire (5); the active chip (3) is electrically connected to the substrate (1) via a second welding wire (6); a gasket (7) is provided between the top chip (4) and the active chip (3), and the gasket (7) is used to connect the top chip (4) and the active chip (3); the top chip (4) is electrically connected to the substrate (1) via a gold wire (8); the bottom chip (2), the active chip (3), the top chip (4), the first welding wire (5), the second welding wire (6) and the gold wire (8) are all encapsulated on the substrate (1) via a plastic encapsulation material (9).
2. The embedded multi-chip package structure according to claim 1, characterized in that: The active chip (3) has a thin film material (10), and the active chip (3) is adhered to the bottom chip (2) via the thin film material (10).
3. The embedded multi-chip package structure according to claim 1, characterized in that: The gasket (7) has no electrical properties.
4. The embedded multi-chip package structure according to claim 1, characterized in that: The lower ends of the first welding wire (5), the second welding wire (6) and the gold wire (8) are all welded to the welding pad (11) of the substrate (1).
5. The embedded multi-chip package structure according to claim 1, characterized in that: A plurality of solder balls (12) are arranged on the lower side of the substrate (1), and the plurality of solder balls (12) are all soldered to the electroplated solder wire layer (13) of the substrate (1).