Micro-display wafer and micro-display module

Abstract

The utility model discloses a micro-display wafer and a micro-display module. The micro-display wafer comprises a substrate comprising a first surface and a second surface which are opposite to each other; the driving circuit comprises a plurality of driving units and a plurality of signal lines, the signal lines extend into the substrate, and at least one signal line comprises at least one interface; the plurality of first bonding pads are located on the side where the second surface of the substrate is located; at least part of each electric connection structure extends to the first surface and / or the second surface, the electric connection structures are electrically connected with the corresponding first bonding pads, and the electric connection structures are connected with the interfaces of the corresponding signal lines through via hole structures arranged on the substrate. According to the micro-display wafer, a binding area does not need to be reserved any more, and the narrow frame design can be achieved conveniently.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to a micro display chip and a micro display module. Background Art

[0002] Micro Light Emitting Diode (Micro-LED) display modules are considered to be the most suitable display modules for application in the field of Augmented Reality (AR) due to their high stability and high brightness.

[0003] The micro-display chip of the existing micro-display module needs to reserve a binding area at the edge, and the binding area is arranged with pads for binding. The binding area will occupy the planar space of the micro-display chip and cannot meet the AR glasses' demand for a narrow frame of the micro-display module. Utility Model Content

[0004] The present application provides a micro display chip and a micro display module, which can obtain a micro display module with a narrower frame.

[0005] In a first aspect, an embodiment of the present application provides a microdisplay chip, the microdisplay chip comprising: a substrate, comprising a first surface and a second surface opposite to each other; a driving circuit, comprising a plurality of driving units and a plurality of signal lines, the plurality of driving units being arranged in an array within the substrate, each of the driving units being used to drive a corresponding micro-light-emitting diode to emit light, the plurality of signal lines extending within the substrate, the plurality of signal lines being electrically connected to the plurality of driving units, at least one of the signal lines comprising at least one interface; a plurality of first pads, located on the side of the substrate where the second surface is located; a plurality of electrical connection structures, at least a portion of each of the electrical connection structures extending over the first surface and / or the second surface, the electrical connection structure being electrically connected to the corresponding first pad, and the electrical connection structure being connected to the interface corresponding to the signal line through a via structure provided on the substrate.

[0006] According to the aforementioned implementation of the first aspect of the present application, the at least one interface of the signal line includes a first interface, and the electrical connection structure includes a first electrical connection structure that at least partially extends over the first surface.

[0007] According to any of the aforementioned embodiments of the first aspect of the present application, the first electrical connection structure includes: a first wiring layer extending on the first surface; a first interconnection portion extending from the first surface to the first interface and electrically connecting the first wiring layer to the first interface; and a second interconnection portion extending through the substrate and electrically connecting the first wiring layer to the first pad.

[0008] According to any of the aforementioned embodiments of the first aspect of the present application, the average value of the cross-sectional area of ​​the second interconnection portion is greater than the average value of the cross-sectional area of ​​the first interconnection portion.

[0009] According to any of the aforementioned embodiments of the first aspect of the present application, the micro display chip further includes: a first passivation layer located between the first electrical connection structure and the substrate; and a first protective layer covering the first surface, the first protective layer covering the first electrical connection structure.

[0010] According to any of the aforementioned embodiments of the first aspect of the present application, the at least one interface of the signal line includes a second interface, and the electrical connection structure includes a second electrical connection structure that at least partially extends over the second surface.

[0011] According to any of the aforementioned embodiments of the first aspect of the present application, the second electrical connection structure includes: a second wiring layer extending on the second surface; and a third interconnect portion extending from the second surface to the second interface and electrically connecting the second wiring layer to the second interface.

[0012] According to any of the aforementioned embodiments of the first aspect of the present application, the micro display chip also includes: a second passivation layer, located between the second electrical connection structure and the substrate; a second protective layer, covering the second surface, the second protective layer covering the second electrical connection structure, and the first pad is located on the side of the second protective layer away from the substrate and is electrically connected to the second electrical connection structure.

[0013] According to any of the aforementioned embodiments of the first aspect of the present application, the at least one interface of the signal line includes a first interface and a second interface, the distance from the first interface to the first surface is smaller than the distance from the second interface to the first surface, and the electrical connection structure includes a first electrical connection structure at least partially extending on the first surface and a second electrical connection structure at least partially extending on the second surface, wherein the first interface of at least one of the signal lines is electrically connected to the first pad through the first electrical connection structure, and the second interface of at least one of the signal lines is electrically connected to the first pad through the second electrical connection structure.

[0014] In a second aspect, an embodiment of the present application provides a micro display module, comprising: a micro display chip according to any of the aforementioned embodiments of the first aspect of the present application; and a driving board, located on the side where the second surface of the substrate is located, and a plurality of second pads are provided on the driving board, wherein each of the first pads is bonded to a corresponding second pad.

[0015] According to the micro-display chip of the embodiment of the present application, the micro-display chip includes a substrate, a driving circuit, a plurality of electrical connection structures and a plurality of first pads, the electrical connection structure at least partially extends to the first surface and / or the second surface, and the first pad is electrically connected to the interface of the corresponding signal line through the corresponding electrical connection structure. Therefore, the interface of the signal line is rewired through the electrical connection structure and then led out to the first pad on the side where the second surface of the substrate is located, which improves the flexibility of the position of the first pad to a certain extent. The above-mentioned micro-display module no longer needs to reserve a binding area on the micro-display chip, thereby avoiding the position occupation of the binding area on the plane space of the micro-display chip, and facilitating the realization of the narrow frame design of the micro-display module. In the micro-display module of the above-mentioned embodiment of the present application, the first pad is used to bond and connect with the second pad at the corresponding position on the driving board, which can realize the circuit structure connection between the micro-display chip and the driving board, abandoning the packaging method of the traditional micro-display module using a flexible circuit board to realize the electrical connection between the micro-display chip and the driving board, and the spacing between the micro-display chip and the driving board is smaller, thereby reducing the delay of signal transmission and improving the display response speed of the micro-display module. The micro-display chip and the driving board can be packaged by using a surface mount fixed connection method, which improves the working stability of the micro-display module and also improves the heat dissipation efficiency of the micro-display module. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0017] Figure 1 A cross-sectional schematic diagram of an embodiment of a micro display module of the present application;

[0018] Figure 2 It is a bottom view schematically showing an embodiment of a micro display chip of the present application.

[0019] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0021] It should be noted that all directional indications in the embodiments of the present application, such as up, down, left, right, front, back, etc., are only used to explain the relative position relationship, movement, etc. between the components in a certain specific posture as shown in the accompanying drawings. If the specific posture changes, the directional indication will also change accordingly. When describing the structure of a component, when a layer or an area is referred to as being "above" or "above" another layer or another area, it may refer to being directly above another layer or another area, or containing other layers or areas between it and another layer or another area. Furthermore, if the component is turned over, the layer or the area will be "below" or "below" another layer or another area.

[0022] In addition, the descriptions of "first", "second", etc. in this application are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. The terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "include..." do not exclude the existence of other identical elements in the process, method, article or device including the elements. In addition, the technical solutions between the various embodiments can be combined with each other, but must be based on the ability of ordinary technicians in the field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that the combination of such technical solutions does not exist and is not within the scope of protection required by this application.

[0023] The embodiments of the present application provide a micro display chip and a micro display module. Figure 1 FIG. 1 is a cross-sectional diagram of an embodiment of a micro display module of the present application. The micro display module includes a micro display chip 100 and a driving board 200 .

[0024] The micro display wafer 100 includes a substrate 110 , a driving circuit 120 , a plurality of electrical connection structures 130 , and a plurality of first pads 140 .

[0025] The substrate 110 includes a first surface S1 and a second surface S2 opposite to each other. In some embodiments, the first surface S1 is the front surface of the substrate 110 , ie, the surface for display, and the second surface S2 is the back surface of the substrate 110 , ie, the surface opposite to the display surface.

[0026] The driving circuit 120 includes a plurality of driving units and a plurality of signal lines LN. The plurality of driving units are arrayed in the substrate 110, and each driving unit is used to drive a corresponding micro-light emitting diode (Micro-LED) to emit light. The plurality of signal lines LN extend in the substrate 110, and the plurality of signal lines LN are electrically connected to the plurality of driving units, and at least one signal line LN includes at least one interface 121.

[0027] Herein, the driving unit refers to a part of the circuit structure unit formed in the substrate 110, each of which corresponds to a light-emitting pixel, that is, corresponds to a micro-LED, and is used to drive the light-emitting pixel to emit light. In some embodiments, the driving unit is a complementary metal oxide semiconductor (CMOS) driving unit, that is, the driving unit includes a CMOS transistor.

[0028] At least a portion of each electrical connection structure 130 extends over the first surface S1 and / or the second surface S2 , the electrical connection structure 130 is electrically connected to the corresponding first pad 140 , and the electrical connection structure 130 is connected to the interface 121 of the corresponding signal line LN through a via structure disposed on the substrate 110 .

[0029] The plurality of first pads 140 are located on the side of the second surface S2 of the substrate 110. The first pads 140 are electrically connected to the interfaces 121 of the corresponding signal lines LN through the corresponding electrical connection structures 130.

[0030] The driving board 200 is located at the side where the second surface S2 of the substrate 110 is located, and a plurality of second pads 210 are disposed on the driving board 200 .

[0031] In this embodiment, each first pad 140 is bonded to a corresponding second pad 210 .

[0032] Herein, a "micro display chip" refers to a display component that uses micro light emitting diodes as light-emitting pixels, which may include a driving array substrate having a plurality of driving units. In some embodiments, the driving array substrate is formed on a silicon-based chip.

[0033] Herein, "micro" light emitting diodes and other "micro" devices refer to the size of light emitting diodes and devices. In some embodiments, the term "micro" refers to the size of the device at a scale of 1 micron to 100 microns. However, it is understood that the embodiments of the present application may not be limited thereto, and certain aspects of the embodiments may be applicable to larger or smaller sizes.

[0034] Herein, the plurality of signal lines LN are directly or indirectly electrically connected to the plurality of driving units, and are used to provide a plurality of signals to the driving circuit 120. In some embodiments, the plurality of signal lines LN include a plurality of signal lines LN that transmit different signals. For example, the plurality of signal lines LN include a clock signal line CLK, a first power supply voltage line VDD, a second power supply voltage line VSS, a plurality of data lines, etc. In some embodiments, the plurality of signal lines LN also include a reset line RESET, a test line TEST, etc.

[0035] The first pad 140 may be formed of a conductive metal such as Ta, Ti, Cu, Au, Al, Ag, Cr, Ni, Pt, TaN, or TiN, or an alloy thereof, and may be a single layer or a stacked layer structure. In some embodiments, the diameter of the first pad 140 is 20um to 80um.

[0036] According to the micro display chip 100 and the micro display module of the embodiment of the present application, the micro display chip 100 includes a substrate 110, a driving circuit 120, a plurality of electrical connection structures 130 and a plurality of first pads 140, the electrical connection structure 130 at least partially extends to the first surface S1 and / or the second surface S2, and the first pad 140 is electrically connected to the interface 121 of the corresponding signal line LN through the corresponding electrical connection structure 130. Therefore, the interface 121 of the signal line LN is rewired through the electrical connection structure 130 and then leads to the first pad 140 on the side where the second surface S2 of the substrate 110 is located, which improves the flexibility of the position of the first pad 140 to a certain extent. The above-mentioned micro display module no longer needs to reserve a binding area on the micro display chip 100, thereby avoiding the position occupation of the binding area on the plane space of the micro display chip 100, facilitating the realization of a narrow frame design of the micro display module, facilitating the improvement of the screen-to-body ratio of the micro display module, and further reducing the volume and weight of the micro display module. In the micro display module of the above-mentioned embodiment of the present application, the first pad 140 is used to bond and connect with the second pad 210 at the corresponding position on the driving board 200, which can realize the circuit structure connection between the micro display chip 100 and the driving board 200, abandoning the packaging method of using a flexible circuit board to realize the electrical connection between the micro display chip 100 and the driving board 200 adopted by the traditional micro display module, and the distance between the micro display chip 100 and the driving board 200 is smaller, thereby reducing the delay of signal transmission and improving the display response speed of the micro display module. The micro display chip 100 and the driving board 200 can be packaged by a surface mount fixed connection method, which improves the working stability of the micro display module and also improves the heat dissipation efficiency of the micro display module.

[0037] According to the micro display module of the embodiment of the present application, compared with the packaging method of realizing electrical connection between the micro display chip 100 and the driving board 200 by metal wire bonding, the packaging method of the embodiment of the present application by bonding the first pad 140 and the second pad 210 can reduce the circuit loss of the electrical connection structure 130 between the micro display chip 100 and the driving board 200, improve the conductive performance of the electrical connection structure 130, provide the possibility for the use scenario of high brightness by large current driving, and reduce the requirements for related process equipment that need to adopt die bonding and wire bonding processes.

[0038] In some embodiments, the interface 121 of the signal line LN is close to the first surface S1 of the substrate 110. In some embodiments, the interface 121 of the signal line LN is close to the second surface S2 of the substrate 110. In some embodiments, the signal line LN includes a single interface 121. In some embodiments, the signal line LN includes two, three, four, or other numbers of interfaces 121. In some embodiments, the signal line LN includes at least two interfaces 121, wherein at least one interface 121 is close to the first surface S1 of the substrate 110, and at least one interface 121 is close to the second surface S2 of the substrate 110. In some embodiments, the multiple interfaces 121 of the signal line LN are all close to the first surface S1 of the substrate 110 or are all close to the second surface S2 of the substrate 110.

[0039] In some embodiments, the orthographic projections of the first pad 140 and the interface 121 electrically connected by the same electrical connection structure 130 on the substrate 110 do not overlap, so that the electrical connection structure 130 is used to adjust the position of the actual electrical connection end of the signal line LN on the plane of the substrate 110.

[0040] In some embodiments, the at least one interface 121 of the signal line LN includes a first interface 121 a .

[0041] In some embodiments, the electrical connection structure 130 includes a first electrical connection structure 130 a at least partially extending from the first surface S1 .

[0042] In some embodiments, the electrical connection structure 130 includes a first wiring layer 131, and the first wiring layer 131 extends to the first surface S1. In some embodiments, the first interface 121a is close to the first surface S1 of the substrate 110, that is, the distance between the first interface 121a and the first surface S1 is smaller than the distance between the first interface 121a and the second surface S2.

[0043] In some embodiments, the first electrical connection structure 130a further includes a first interconnect 151 and a second interconnect 152. The first interconnect 151 extends from the first surface S1 to the first interface 121a and electrically connects the first wiring layer 131 to the first interface 121a. The second interconnect 152 extends through the substrate 110 and electrically connects the first wiring layer 131 to the first pad 140.

[0044] The first interconnection 151 and the second interconnection 152 are conductive structures. In some embodiments, the first interconnection 151 and the second interconnection 152 are made of metal materials.

[0045] In some embodiments, the average value of the cross-sectional area of ​​the second interconnect 152 is greater than the average value of the cross-sectional area of ​​the first interconnect 151 , ensuring that the second interconnect 152 has better conductivity.

[0046] In some embodiments, the micro display wafer 100 further includes a first passivation layer 161 located between the first electrical connection structure 130a and the substrate 110 , that is, the first passivation layer 161 is located between the first wiring layer 131 and the substrate 110 , between the first interconnection portion 151 and the substrate 110 , and between the second interconnection portion 152 and the substrate 110 .

[0047] In some embodiments, the thickness of the first passivation layer 161 is 20nm to 350nm. In this embodiment, the first passivation layer 161 is preferably a silicon oxide (SiOx) layer with a thickness of 150nm. At this time, while achieving better insulation performance and relatively low film stress, the process is easier to implement. In some other embodiments, the material of the first passivation layer 161 can also be an insulating material such as silicon nitride (SiN), silicon oxynitride (SiNO), aluminum nitride (AlN), aluminum oxide (AlO), or aluminum oxynitride (AlNO).

[0048] In some embodiments, the micro display wafer 100 further includes a first protection layer 171 . The first protection layer 171 covers the first surface S1 . The first protection layer 171 covers the first electrical connection structure 130 a . In this embodiment, the first protection layer 171 covers the first wiring layer 131 .

[0049] The first protective layer 171 is formed of an insulating material, which may be an organic material. In some embodiments, the first protective layer 171 is an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, or aluminum oxynitride. In this embodiment, the first protective layer 171 is formed of a silicon oxide material with a thickness of 40um to 400um. By providing the first protective layer 171, the first electrical connection structure 130a can be effectively protected.

[0050] In some embodiments, the at least one interface 121 of the signal line LN includes a second interface 121 b .

[0051] The electrical connection structure 130 includes a second electrical connection structure 130 b at least partially extending from the second surface.

[0052] In some embodiments, the electrical connection structure 130 includes a second wiring layer 132 extending on the second surface S2. In some embodiments, the second interface 121b is close to the second surface S2 of the substrate 110, that is, the distance between the second interface 121b and the second surface S2 is less than the distance between the second interface 121b and the first surface S1.

[0053] In some embodiments, the second electrical connection structure 130b further includes a third interconnection 153. The third interconnection 153 extends from the second surface S2 to the second interface 121b and electrically connects the second wiring layer 132 with the second interface 121b.

[0054] The third interconnect 153 is a conductive structure. In some embodiments, the third interconnect 153 is a metal material.

[0055] In some embodiments, the micro display wafer 100 further includes a second passivation layer 162 , which is located between the second electrical connection structure 130 b and the substrate, that is, between the second wiring layer 132 and the substrate 110 , and between the third interconnection 153 and the substrate 110 .

[0056] The second passivation layer 162 has a thickness of 20 nm to 350 nm. In this embodiment, the second passivation layer 162 is preferably a silicon oxide layer with a thickness of 150 nm. At this time, while obtaining good insulation performance and relatively low film stress, the process is easier to implement. In some other embodiments, the material of the second passivation layer 162 can also be an insulating material such as silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, or aluminum oxynitride.

[0057] In some embodiments, the micro display wafer 100 further includes a second protective layer 172, the second protective layer 172 covers the second surface S2, the second protective layer covers the second electrical connection structure 130b, and the first pad is located on a side of the second protective layer away from the substrate and is electrically connected to the second electrical connection structure 130b. In this embodiment, the second protective layer 172 covers the second wiring layer 132, and the first pad 140 is located on a side of the second protective layer 172 away from the substrate 110 and is electrically connected to the second wiring layer 132.

[0058] The first protective layer 171 is formed of an insulating material. In some embodiments, the second protective layer 172 is an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, or aluminum oxynitride. By providing the second protective layer 172, the second electrical connection structure 130b can be effectively protected.

[0059] In some embodiments, at least one interface 121 of the signal line LN includes a first interface 121a and a second interface 121b, and the distance from the first interface 121a to the first surface S1 is less than the distance from the second interface 121b to the first surface S1. The electrical connection structure 130 includes a first electrical connection structure 130a that at least partially extends on the first surface S1 and a second electrical connection structure 130b that at least partially extends on the second surface S2. The first interface 121a of at least one signal line LN is electrically connected to the first pad 140 through the first electrical connection structure 130a, and the second interface 121b of at least one signal line LN is electrically connected to the first pad 140 through the second electrical connection structure 130b.

[0060] Figure 2 1 is a bottom view of an embodiment of the micro display chip of the present application. In some embodiments, a plurality of first pads 140 are arranged in an array on the side where the second surface S2 of the substrate 110 is located. The interfaces 121 of the plurality of signal lines LN are rewired through the electrical connection structure 130 and then led out to the first pads 140 on the side where the second surface S2 of the substrate 110 is located. The plurality of first pads 140 are arranged in an array, which facilitates the surface mounting process between the micro display chip 100 and the driving board 200.

[0061] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. All equivalent structural changes made under the concept of the present application using the contents of the present application specification and drawings, or directly / indirectly used in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A micro display chip, characterized in that: include: a substrate comprising opposing first and second surfaces; A driving circuit, comprising a plurality of driving units and a plurality of signal lines, wherein the plurality of driving units are arranged in an array in the substrate, each of the driving units is used to drive a corresponding micro-LED to emit light, the plurality of signal lines extend in the substrate, the plurality of signal lines are electrically connected to the plurality of driving units, and at least one of the signal lines comprises at least one interface; A plurality of first pads, located on the side where the second surface of the substrate is located; A plurality of electrical connection structures, each of which at least partially extends over the first surface and / or the second surface, is electrically connected to the corresponding first pad, and is connected to the interface corresponding to the signal line through a via structure provided on the substrate.

2. The micro display chip according to claim 1, characterized in that: The at least one interface of the signal line includes a first interface, and the electrical connection structure includes a first electrical connection structure at least partially extending on the first surface.

3. The micro display chip according to claim 2, characterized in that: The first electrical connection structure comprises: a first wiring layer extending on the first surface; a first interconnection portion extending from the first surface to the first interface and electrically connecting the first wiring layer to the first interface; A second interconnection extends through the substrate and electrically connects the first wiring layer with the first pad.

4. The micro display chip according to claim 3, characterized in that: An average value of the cross-sectional areas of the second interconnections is greater than an average value of the cross-sectional areas of the first interconnections.

5. The micro display chip according to claim 2, characterized in that: The micro display chip also includes: a first passivation layer, located between the first electrical connection structure and the substrate; A first protective layer covers the first surface, and the first protective layer covers the first electrical connection structure.

6. The micro display chip according to claim 1, characterized in that: The at least one interface of the signal line includes a second interface, and the electrical connection structure includes a second electrical connection structure that at least partially extends over the second surface.

7. The micro display chip according to claim 6, characterized in that: The second electrical connection structure comprises: a second wiring layer extending on the second surface; A third interconnection portion extends from the second surface to the second interface and electrically connects the second wiring layer to the second interface.

8. The micro display chip according to claim 6, characterized in that: The micro display chip also includes: a second passivation layer, located between the second electrical connection structure and the substrate; A second protective layer covers the second surface, the second protective layer covers the second electrical connection structure, and the first pad is located on a side of the second protective layer away from the substrate and is electrically connected to the second electrical connection structure.

9. The micro display chip according to claim 1, characterized in that: The at least one interface of the signal line includes a first interface and a second interface, the distance from the first interface to the first surface is smaller than the distance from the second interface to the first surface, The electrical connection structure includes a first electrical connection structure at least partially extending from the first surface and a second electrical connection structure at least partially extending from the second surface. The first interface of at least one of the signal lines is electrically connected to the first pad via the first electrical connection structure, and the second interface of at least one of the signal lines is electrically connected to the first pad via the second electrical connection structure.

10. A micro display module, characterized in that: include: The micro display chip according to any one of claims 1 to 9; as well as a driving board, located on the side where the second surface of the substrate is located, and a plurality of second pads are provided on the driving board, Each of the first pads is bonded to a corresponding second pad.

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