Chip stacking structure comprising double wiring layers

Abstract

The utility model discloses a chip stacking structure containing double wiring layers. The chip stacking structure comprises a lower layer structure and an upper layer structure, the lower layer structure comprises a substrate and at least one first chip inversely arranged on the substrate, the upper surface of the substrate is covered with a first plastic package body, the first plastic package body wraps the first chip, a first rewiring layer is arranged on the first plastic package body, the substrate and the first rewiring layer are interconnected through copper columns, and first solder balls are arranged on the lower surface of the substrate; the upper layer structure comprises a second rewiring layer, a second chip and a third chip, the second chip and the third chip are mounted on the two sides of the second rewiring layer, the second chip and the third chip are a normal chip and a flip chip respectively, and the surface of the second rewiring layer for mounting the second chip is covered with a second plastic package body; the first rewiring layer and the second rewiring layer are interconnected through a second solder ball, and a passive element can be arranged on the second rewiring layer. According to the utility model, various structures such as a flip chip, a copper column and a normal chip are integrated, two layers of RDL structures are included, passive elements can be integrated according to actual needs, and the integration level is improved while the requirements of different application scenes are met.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor packaging, and more specifically to a chip stacking structure including a double wiring layer. Background Art

[0002] The existing chip stacking structure is generally structured as follows: the lower layer is a flip chip, and the upper layer is a ball-embedded plastic package containing a face-up chip. The upper and lower chips are connected by copper pillars or solder balls, and some structures will include an RDL (ReDistribution Layer) redistribution layer.

[0003] In the existing chip stacking structure, the chip types are relatively single and the overall functions are not rich enough. With the rapid development of consumer electronics such as mobile phones and tablets, the functional requirements for chips are becoming more and more diversified. Therefore, a new packaging structure is needed to encapsulate chips with various functions and structures in a plastic package, while improving the integration and meeting the needs of different application scenarios. Utility Model Content

[0004] In order to solve the above problems, the utility model provides a packaging structure including chips of various structures and functions, which is a chip stacking structure including a double wiring layer, which improves the integration while meeting the requirements of different application scenarios.

[0005] According to one aspect of the utility model, there is provided a chip stacking structure including a double wiring layer, which includes a lower structure and an upper structure;

[0006] The lower structure includes a substrate, at least one chip flipped on the substrate, the upper surface of the substrate is covered with a plastic package, the plastic package wraps the chip, a redistribution layer is provided on the plastic package, the substrate and the redistribution layer are interconnected through copper pillars, and a solder ball is provided on the lower surface of the substrate;

[0007] The upper structure includes a second redistribution layer, a second chip and a third chip mounted on both sides of the second redistribution layer, the surface of the second redistribution layer on which the second chip is mounted is covered with a second plastic package, and the second plastic package wraps the second chip;

[0008] The redistribution layer 1 and the redistribution layer 2 are interconnected, and the redistribution layer 1 is located below the side where the chip 2 is located.

[0009] In some implementations, the redistribution layer 1 and the redistribution layer 2 are interconnected via solder balls 2, the solder balls 2 are distributed around the chip 2, and the plastic package 2 wraps the solder balls 2.

[0010] In some embodiments, chip two is a face-up chip and chip three is a flip-chip.

[0011] In some implementations, chip 2 and redistribution layer 2 are interconnected via bonding wires.

[0012] In some embodiments, the bottom filling is achieved between chip 1 and the substrate by using filler 1, and the bottom filling is achieved between chip 3 and the redistribution layer 2 by using filler 2.

[0013] In some embodiments, the diameter of the first solder ball is 200-600 μm, and the diameter of the second solder ball is 100-300 μm.

[0014] In some embodiments, passive components are disposed on the second redistribution layer.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: the chip stacking structure including a double wiring layer provided by the present invention integrates a variety of structures such as flip chips, copper pillars, and upright chips, and includes a two-layer RDL (ReDistribution Layer) structure of redistribution layer one and redistribution layer two. Passive components can also be integrated according to actual needs. The chip stacking packaging structure can meet the needs of different application scenarios while improving the degree of integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the packaging process of the lower structure in the chip stacking structure;

[0017] Figure 2 It is a schematic diagram of the packaging process before the upper structure is connected to the lower structure;

[0018] Figure 3 It is a schematic diagram of the subsequent packaging process of interconnecting the upper structure with the lower structure;

[0019] Figure 4 It is a structural schematic diagram of an implementation mode of a chip stacking structure including a double wiring layer of the utility model. DETAILED DESCRIPTION

[0020] The utility model is further described below in conjunction with specific implementation methods.

[0021] like Figure 4As shown, a chip stacking structure including a double wiring layer according to an embodiment of the present invention includes a lower structure and an upper structure. Specifically, the lower structure includes a substrate 1, at least one chip 2 flipped on the substrate 1, the upper surface of the substrate 1 is covered with a plastic package 4, the plastic package 4 wraps the chip 2, and the plastic package 4 has a redistribution layer 5, the substrate 1 and the redistribution layer 5 are interconnected through copper pillars 3, and the lower surface of the substrate 1 is provided with a solder ball 11. The upper structure includes a redistribution layer 2 6, a chip 2 7 and a chip 3 8 mounted on both sides of the redistribution layer 2 6, the surface of the redistribution layer 2 6 on which the chip 2 7 is mounted is covered with a plastic package 2 9, and the plastic package 2 9 wraps the chip 2 7. The redistribution layer 1 5 and the redistribution layer 2 6 are interconnected through solder balls 2 10, the solder balls 2 10 are distributed around the chip 2 7, the plastic package 2 9 wraps the solder balls 2 10, and the redistribution layer 1 5 is located below the side where the chip 2 7 is located.

[0022] According to product requirements, passive components 12 may be mounted on the second redistribution layer 6 , and the passive components 12 include but are not limited to capacitors, resistors, inductors, etc.

[0023] In this embodiment, the second chip 7 is a face-up chip, the pads on the surface of the second chip 7 are interconnected with the second redistribution layer 6 through the bonding wires 71, and the third chip 8 is a flip chip. In practical applications, the second chip 7 and the third chip 8 mounted on both sides of the second redistribution layer 6 can be chips of the same or different structures.

[0024] When the chip 1 2 and the chip 3 8 are flipped, it is necessary to implement bottom filling between the chip 1 2 and the substrate 1 through the filler 1 21 , and to implement bottom filling between the chip 3 8 and the redistribution layer 2 6 through the filler 2 81 , so as to improve the stability of the connection.

[0025] In the chip stacking structure including a double wiring layer, the substrate 1 is generally 4 to 16 layers, the bump pitch of the chip 2 is generally 80 to 200 μm, the diameter of the copper column 3 is generally 100 to 200 μm, and the pitch is 200 to 400 μm, the redistribution layer 1 5 can be 1 to 8 layers, and the line width and line spacing are generally 1 to 15 μm, the redistribution layer 2 6 can be 1 to 8 layers, and the line width and line spacing are generally 1 to 15 μm, the bump pitch of the chip 3 8 is generally 30 to 100 μm, the diameter of the solder ball 1 11 is 200 to 600 μm, and the diameter of the solder ball 2 10 is 100 to 300 μm.

[0026] Combination Figures 1 to 3 , specifically describing the packaging process of the chip stacking structure including the double wiring layer described in the present application, the steps are as follows:

[0027] Step 1: If Figure 1As shown in 1A and 1B, a substrate 1 is taken, a TMV (Through-Molding Via) copper column 3 is mounted on the front side of the substrate 1, a chip 2 is flipped, and reflow is performed to complete the welding.

[0028] Step 2: Complete the bottom filling of chip 1 2. Filler 1 21 is filled between chip 1 2 and substrate 1 and around the lower part of chip 1 2. Figure 1 As shown in Figure 1B.

[0029] In each chip stacking structure including a double wiring layer, the number of the chips 1 2 can be one or more.

[0030] Step 3: If Figure 1 As shown in Figure 1C, the substrate 1 is plastic-sealed to form a plastic-sealed body 4 on the front side of the substrate 1. During the plastic-sealing process, the plastic-sealed body 4 covers the front side of the substrate 1, the copper pillar 3 and the chip 2. After the plastic-sealed body 4 is solidified, the plastic-sealed body 4 is subjected to a wafer thinning process to expose the end face of the copper pillar 3.

[0031] Step 4: Continue the packaging process and make a redistribution layer 5 on the plastic package body 4, such as Figure 1 As shown in Figure 1D.

[0032] Step 5: At the same time, take the glass carrier 100 and make the second redistribution layer 6 on the glass carrier 100, such as Figure 2 As shown in Figure 2A.

[0033] Step 6: If Figure 2 As shown in FIG. 2B , a second chip 7 is mounted on the surface of the second redistribution layer 6 . The second chip 7 is a front-mounted chip, and a wire bonding process 71 is completed.

[0034] Step 7: Planting balls on the surface of the second redistribution layer 6 to form solder balls 10, such as Figure 2 As shown in Figure 2B.

[0035] Step 8: If Figure 3 As shown in FIG. 3A , the second redistribution layer 6 is flipped onto the first redistribution layer 5 , and the upper and lower layer structures are interconnected through the second solder ball 10 .

[0036] Step 9: Complete the encapsulation between the upper and lower structures to form a plastic package body 9, such as Figure 3 As shown in Figure 3B.

[0037] Step 10: Remove the glass carrier 100 .

[0038] Step 11: Figure 3As shown in 3C, the chip three 8 is flipped on the other side of the redistribution layer two 6, and the passive components 12 are mounted as needed. The chip three 8 can be mounted through processes such as TCB; and the bottom filling of the chip three 8 is completed, and the filler two 81 is filled between the chip three 8 and the redistribution layer two 6, and around the lower half of the chip three 8.

[0039] Step 12: Planting balls on the back of the substrate 1 to form solder balls 11, such as Figure 3 As shown in 3D.

[0040] The chip stacking structure including a double wiring layer provided by the utility model integrates a variety of structures such as flip chips, copper pillars 3, and upright chips. It includes a two-layer RDL (ReDistribution Layer) structure of a redistribution layer 1 5 and a redistribution layer 2 6. Passive components 12 can also be integrated according to actual needs. The chip stacking packaging structure can meet the needs of different application scenarios while improving the integration level.

[0041] The above are only some embodiments of the present invention. It should be pointed out that for ordinary technicians in this field, other modifications and improvements can be made without departing from the creative concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A chip stacking structure including a double wiring layer, comprising a lower structure and an upper structure, characterized in that: The lower structure comprises a substrate (1), at least one chip (2) flipped on the substrate (1), the upper surface of the substrate (1) is covered with a plastic package (4), the plastic package (4) wraps the chip (2), a redistribution layer (5) is provided on the plastic package (4), the substrate (1) and the redistribution layer (5) are interconnected via copper pillars (3), and a solder ball (11) is provided on the lower surface of the substrate (1); The upper structure comprises a second redistribution layer (6), a second chip (7) and a third chip (8) mounted on both sides of the second redistribution layer (6), the surface of the second redistribution layer (6) on which the second chip (7) is mounted is covered with a second plastic package (9), and the second plastic package (9) wraps the second chip (7); The redistribution layer 1 (5) and the redistribution layer 2 (6) are interconnected, and the redistribution layer 1 (5) is located below the side where the chip 2 (7) is located.

2. The chip stacking structure comprising a double wiring layer according to claim 1, characterized in that: The redistribution layer 1 (5) and the redistribution layer 2 (6) are interconnected via solder balls 2 (10), the solder balls 2 (10) are distributed around the chip 2 (7), and the plastic package 2 (9) wraps the solder balls 2 (10).

3. The chip stacking structure comprising a double wiring layer according to claim 2, characterized in that: The chip two (7) is a front-mounted chip, and the chip three (8) is a flip-chip.

4. The chip stacking structure comprising a double wiring layer according to claim 3, characterized in that: The second chip (7) and the second redistribution layer (6) are interconnected via welding wires (71).

5. The chip stacking structure comprising a double wiring layer according to claim 3, characterized in that: The bottom filling is achieved between the chip one (2) and the substrate (1) by means of filler one (21), and the bottom filling is achieved between the chip three (8) and the redistribution layer two (6) by means of filler two (81).

6. The chip stacking structure comprising a double wiring layer according to claim 3, characterized in that: The diameter of the solder ball one (11) is 200-600 μm, and the diameter of the solder ball two (10) is 100-300 μm.

7. The chip stacking structure comprising a double wiring layer according to claim 1, characterized in that: Passive components (12) are provided on the second redistribution layer (6).

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