Micro electro mechanical system

Abstract

The utility model provides a micro-electro-mechanical system. The micro-electro-mechanical system comprises a lead frame; the integrated circuit chip is arranged on the lead frame, one side, far away from the lead frame, of the integrated circuit chip (IC chip) is provided with a first bonding pad, and the first bonding pad is coupled to the lead frame through a lead; the MEMS chip is arranged on the integrated circuit chip, one side, far away from the integrated circuit chip, of the MEMS chip is provided with a second bonding pad, and the second bonding pad is coupled with the integrated circuit chip through a lead; wherein the micro-electro-mechanical chip comprises a CAP layer and a TSV layer, and the thickness of the CAP layer is 20 [mu] m-70 [mu] m; and / or the thickness of the TSV layer is 50 [mu] m-100 [mu] m, through the above mode, the corresponding required size value is selected according to the influence degree of different parameter values on the frequency deviation value of the micro-electro-mechanical chip, and the structure is adjusted to reduce the influence on the frequency deviation caused by the packaging stress of the micro-electro-mechanical chip.

Description

Technical Field

[0001] The present application mainly relates to the technical field of micro-electromechanical systems, and in particular to a micro-electromechanical system. Background Art

[0002] Micro-Electro-Mechanical System (MEMS), also known as micro-electro-mechanical system, micro-system, micro-machine, etc., refers to high-tech devices with a size of a few millimeters or even smaller. A MEMS is a micro device or system that integrates micro-sensors, micro-actuators, micro-mechanical structures, micro-power sources, signal processing and control circuits, high-performance electronic integrated devices, interfaces, and communications.

[0003] Among them, micro-electromechanical systems are the integration of microcircuits and micromechanics on a chip according to functional requirements, and the size is usually in the millimeter or micrometer level. Generally speaking, the circuit part is often designed on an integrated circuit (IC) chip, and the micromechanics are designed on a MEMS chip, and the IC chip is coupled with the MEMS chip.

[0004] The resonant frequency is an important performance parameter of the MEMS resonator. Since the resonant frequency of the MEMS resonator is very sensitive to the stress during the packaging process, the change in packaging stress is one of the most critical factors affecting the long-term stability of the MEMS resonator; the packaging stress will impose an additional external stress on the MEMS resonator, thereby causing the frequency output of the MEMS resonator to shift. The resonant frequency shift caused by packaging mainly comes from two aspects: the packaging stress causes the gap between the MEMS chip device to change, thereby causing the electrostatic stiffness to change, resulting in frequency deviation; the packaging stress causes the MEMS chip structure to deform, thereby causing the mechanical stiffness to change, resulting in frequency deviation. Utility Model Content

[0005] The main purpose of this application is to propose a micro-electromechanical system to solve the problem that during the packaging process of the micro-electromechanical system chip, the stress generated during the packaging process may cause the gap of the MEMS chip to change or / and the structure of the chip to change, which ultimately causes its resonant frequency to shift, affecting the performance of the entire micro-electromechanical system.

[0006] To solve the above problems, the present application provides a micro-electromechanical system, which includes: a lead frame; an integrated circuit chip, which is arranged on the lead frame, and a first pad is arranged on the side of the integrated circuit chip (IC chip) away from the lead frame, and the first pad is coupled to the lead frame through a lead; a micro-electromechanical chip, which is arranged on the integrated circuit chip, and a second pad is arranged on the side of the micro-electromechanical chip (MEMS chip) away from the integrated circuit chip, and the second pad is coupled to the integrated circuit chip through a lead; wherein the micro-electromechanical chip includes a CAP layer and a TSV layer, the thickness of the CAP layer is 20μm to 70μm; and / or the thickness of the TSV layer is 50μm to 100μm.

[0007] In one embodiment, the lead frame includes a half-etched area facing the integrated circuit chip, and the thickness of the half-etched area is 50 μm to 150 μm; and / or the thickness of the integrated circuit chip is 50 μm to 200 μm.

[0008] In one embodiment, the width of the integrated circuit chip is 800 μm to 1600 μm; and / or the width of the micro-electromechanical chip is 400 μm to 700 μm.

[0009] To solve the above problems, the present application also provides a second micro-electromechanical system, which includes: a lead frame; an integrated circuit chip, which is arranged on the lead frame, and a third pad is arranged on the side of the integrated circuit chip away from the lead frame, and the third pad is coupled to the lead frame through a lead; a micro-electromechanical chip, which is arranged on the integrated circuit chip, and a fourth pad is arranged on the side of the micro-electromechanical chip facing the integrated circuit chip, and the fourth pad is flip-chip coupled to the integrated circuit chip through a conductive bump; wherein the micro-electromechanical chip includes a CAP layer and a TSV layer, and the thickness of the CAP layer is 20μm to 70μm.

[0010] In one embodiment, the lead frame includes a half-etched area facing the integrated circuit chip, and the thickness of the half-etched area is 50 μm to 150 μm; and / or the width of the micro-electromechanical chip is 400 μm to 700 μm.

[0011] In one embodiment, the thickness of the integrated circuit chip is 50 μm to 200 μm; and / or the width of the integrated circuit chip is 800 μm to 1600 μm; and / or the thickness of the TSV layer is 50 μm to 100 μm.

[0012] To solve the above problems, the present application provides a third micro-electromechanical system, which includes: a lead frame; an integrated circuit chip, which is arranged on the lead frame, and a fifth pad is arranged on the side of the integrated circuit chip facing the lead frame, and the fifth pad is coupled to the lead frame through a conductive bump; a micro-electromechanical chip, which is arranged on the side of the integrated circuit chip facing the lead frame, and a fourth pad is arranged on the side of the micro-electromechanical chip facing the integrated circuit chip, and the fourth pad is flip-chip coupled to the integrated circuit chip through a conductive bump; wherein the lead frame includes a half-etched area facing the side of the integrated circuit chip, and the thickness of the half-etched area is 50μm to 150μm.

[0013] In one embodiment, the micro-electromechanical chip includes a CAP layer and a TSV layer, the thickness of the TSV layer is 50 μm to 100 μm; and / or the thickness of the CAP layer is 20 μm to 70 μm.

[0014] In one embodiment, the width of the MEMS chip is 400 μm to 700 μm.

[0015] In one embodiment, the thickness of the integrated circuit chip is 50 μm to 200 μm; and / or the width of the integrated circuit chip is 800 μm to 1600 μm.

[0016] Through the above method, according to the different degrees of influence of various structural size parameters in the micro-electromechanical system on its frequency deviation, each structural size is adjusted to reduce the influence of the frequency deviation of the micro-electromechanical chip caused by the existence of packaging stress during the packaging process, thereby improving the production efficiency and production yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0018] Figure 1 It is a structural schematic diagram of an embodiment of a micro-electromechanical system provided by the present application;

[0019] Figure 2 It is a structural schematic diagram of an embodiment of a micro-electromechanical chip provided by the present application;

[0020] Figure 3 is a structural schematic diagram of a second embodiment of a micro-electromechanical system provided by the present application;

[0021] Figure 4 It is a structural schematic diagram of the third embodiment of the micro-electromechanical system provided by the present application.

[0022] Reference numerals: 100, micro-electromechanical system; 10, lead frame; 11, half-etched area; 20, integrated circuit chip; 30, micro-electromechanical chip; a, lead; b, conductive bump. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be appreciated that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the art without making creative work are within the scope of protection of the present application.

[0024] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0025] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0026] In micro-electromechanical systems, the main function of packaging is to provide a channel for the chip to connect to the outside world, and includes mechanical support and protection, electrical insulation and protection, and protection against moisture, ions and harmful chemicals; the heat generated by the chip when it is working cannot be dissipated in time by the small size of the chip alone, and the packaging provides a channel for the evacuation of heat; the packaging provides interconnection between the power module and the chip. However, since most micro-electromechanical devices include suspended and vibrating structures, the packaging stress generated in the packaging will have a great impact on the performance and reliability of the micro-electromechanical devices, especially micro-electromechanical devices with similar thin film structures; specifically, the packaging stress generated by the packaging causes the frequency generated by the MEMS chip to shift, and the frequency generated by the MEMS chip is its important performance parameter, so the frequency shift generated by the packaging has a huge impact on the performance of the MEMS chip, and the packaging stress is mainly for: on the one hand, the packaging stress causes the gap between the MEMS chip device to change, thereby causing the electrostatic stiffness to change, resulting in frequency shift; on the other hand, the packaging stress causes the MEMS chip structure to deform, thereby causing the mechanical stiffness to change, resulting in frequency shift.

[0027] Therefore, the present application proposes a micro-electromechanical system to "offset" or reduce the frequency deviation of the micro-electromechanical system caused by the stress generated during the packaging process by adjusting / optimizing the dimensions of the MEMS chip, IC chip, and lead frame, such as X&Y length, thickness, etc.

[0028] Since the stress caused by different packaging processes leads to different frequency shifts, the optimized and adjusted structures have different effects and corresponding priorities. Different packaging processes use different structural adjustments. By designing different parameter values ​​of corresponding structures in different processes, the packaging is optimized with the optimal combination that causes frequency shift.

[0029] See also Figure 1 As shown, Figure 1 It is a structural schematic diagram of an embodiment of a micro-electromechanical system provided by the present application; wherein the micro-electromechanical system 100 is packaged by a wire bonding process, specifically, the micro-electromechanical system 100 includes: a lead frame 10, an integrated circuit chip 20, and a micro-electromechanical chip 30; wherein the integrated circuit chip 20 is arranged on the lead frame 10, and a first pad is arranged on a side of the integrated circuit chip 20 away from the lead frame 10, and the first pad is coupled to the lead frame 10 through a lead; the micro-electromechanical chip 30 is arranged on the integrated circuit chip 20, and a second pad is arranged on a side of the micro-electromechanical chip 30 away from the integrated circuit chip 20, and the second pad is coupled to the integrated circuit chip 20 through a lead a; wherein the micro-electromechanical chip 30 includes a CAP layer and a TSV layer, and the thickness of the CAP layer is 20μm to 70μm; and / or the thickness of the TSV layer is 50μm to 100μm.

[0030] Among them, the wire bonding process is a process that uses thin metal wires and utilizes heat, pressure, and ultrasonic energy to tightly weld the metal leads to the lead frame pads to achieve electrical interconnection between the chip and the lead frame and information exchange between the chips. Under ideal control conditions, electron sharing or atomic mutual diffusion will occur between the leads and the lead frame, thereby achieving atomic-level bonding between the two metals.

[0031] For further information, see Figure 2 As shown, Figure 2 1 is a schematic diagram of the structure of an embodiment of a micro-electromechanical chip provided by the present application; wherein the micro-electromechanical chip 30 includes: a CAP layer and a TSV layer (Through Silicon Via layer); wherein the TSV layer (Through Silicon Via layer) is one of the key technologies for realizing 3D advanced packaging by making vertical conduction between chips and between wafers. The CAP layer is an important structure in semiconductor devices. It refers to an extremely thin silicon oxide layer sandwiched between a P-type semiconductor and an N-type semiconductor in a PN junction. Its function is to form a high electric field region in the PN junction to improve the performance and reliability of the device.

[0032] Similarly, the CAP layer and TSV layer (through silicon via layer) in the micro-electromechanical chip 30 will also affect the frequency offset value of the micro-electromechanical chip 30, so simulation testing is also used to determine the degree of their influence on the frequency offset value of the micro-electromechanical chip 30; a simulation test is performed on the thickness value of the CAP layer in the micro-electromechanical chip 30, and the thickness value parameters are selected as 20μm, 30μm, 40μm, 50μm, 60μm, and 70μm, and simulation tests are performed respectively, as shown in Table 1, which is a simulation parameter table of an embodiment of a micro-electromechanical system provided in the present application.

[0033] Table 1:

[0034]

[0035] The thickness of the CAP layer in the micro-electromechanical chip 30 is in the range of 20 μm to 70 μm. As the thickness gradually increases, the corresponding frequency offset value of the micro-electromechanical chip 30 gradually increases, and the frequency offset value increases by about 10 ppm. Therefore, in one embodiment, the thickness of the CAP layer in the micro-electromechanical chip 30 is selected to be 20 μm. The thickness value of the TSV layer (through silicon via layer) in the micro-electromechanical chip 30 is simulated and tested, and the thickness value parameters are selected as 50μm, 60μm, 70μm, 80μm, 90μm, and 100μm, and the simulation tests are performed respectively. As shown in Table 1, the thickness value of the TSV layer (through silicon via layer) in the micro-electromechanical chip 30 is in the range of 50μm to 100μm. As the thickness value gradually increases, the corresponding frequency offset value of the micro-electromechanical chip 30 gradually decreases, and the frequency offset value decreases by about 10ppm. Therefore, in one embodiment, the corresponding thickness value of the TSV layer (through silicon via layer) in the micro-electromechanical chip 30 is selected to be 100μm.

[0036] Optionally, in one embodiment, the lead frame 10 includes a half-etched area 11 facing the side of the integrated circuit chip 20, and the thickness of the half-etched area 11 is 50μm to 150μm; and / or the thickness of the integrated circuit chip 20 is 50μm to 200μm. As shown in Table 1, the structure thereof is simulated and calculated, and the thickness of the half-etched area 11 of the lead frame 10 is simulated and calculated, and the thickness of the half-etched area 11 is selected to be 50μm, 100μm, and 150μm for simulation respectively. The simulation results show that when the thickness of the half-etched area 11 is within the range of 50μm to 150μm, the frequency offset of the micro-electromechanical chip 30 gradually increases, and the frequency offset increases by about 7ppm; as the thickness of the half-etched area 11 gradually increases, the frequency offset of the micro-electromechanical chip 30 gradually increases, so in one embodiment, the thickness value of the half-etched area 11 is selected to be 50μm.

[0037] Optionally, in one embodiment, the width of the integrated circuit chip 20 is 800μm to 1600μm; and / or the width of the micro-electromechanical chip 30 is 400μm to 700μm. As shown in Table 1, in the corresponding simulation test, the width parameters of the integrated circuit chip 20 are selected as 800μm, 900μm, 1000μm, 1100μm, 1200μm, 1300μm, 1400μm, 1500μm, and 1600μm, and simulation tests are performed respectively. The simulation results show that the width of the integrated circuit chip 20 is within the range of 800μm to 1600μm. As the width of the integrated circuit chip 20 increases, the frequency offset value of the corresponding micro-electromechanical chip 30 gradually increases, and the frequency offset value increases by about 1ppm. Therefore, in one embodiment, the width value of the corresponding integrated circuit chip 20 is selected as 800μm. It also includes a simulation test on the thickness value of the integrated circuit chip 20, and the thickness value parameters of the integrated circuit chip 20 are selected as 50μm, 100μm, 150μm, and 200μm, and simulations are performed respectively. The simulation results show that the thickness value of the integrated circuit chip 20 is in the range of 50μm to 200μm. As the thickness value of the integrated circuit chip 20 increases, the frequency offset value of the corresponding micro-electromechanical chip 30 gradually increases, and the frequency offset value increases by about 7ppm. Therefore, in one embodiment, the corresponding thickness value of the integrated circuit chip 20 is selected as 50μm. In addition, a simulation test is performed on the width of the microelectromechanical chip 30, wherein the width parameters of the microelectromechanical chip 30 are selected as 400μm, 450μm, 500μm, 550μm, 600μm, 650μm, and 700μm, and simulation tests are performed on them respectively. The simulation results show that the width parameter of the microelectromechanical chip 30 is in the range of 400μm to 700μm, and as the width value of the microelectromechanical chip 30 increases, the frequency offset value of the microelectromechanical chip 30 gradually decreases, and the frequency offset value decreases to less than 1ppm. Therefore, in one embodiment, the width value of the corresponding microelectromechanical chip 30 is selected as 700μm.

[0038] Lead frame refers to a thin metal frame used to connect the contact points of the internal chip of a semiconductor integrated block and the external wires. It is a main structural material for semiconductor packaging. Specifically, the lead frame is mainly composed of two parts: a chip pad and a lead finger. As a chip carrier of an integrated circuit, the lead frame is a key structural component that uses bonding materials (gold wire, aluminum wire, copper wire) to electrically connect the internal circuit lead end (bonding point) of the chip to the external lead through the inner lead to form an electrical circuit. It acts as a bridge to connect to the external wires. The micro-electromechanical chip 30, the integrated circuit chip 20 and the lead frame 10 can be physically coupled together by an electrically insulating epoxy resin.

[0039] Furthermore, it can be seen from the above embodiments and the parameter value simulation structure of Table 1 that, as for the degree of influence of the parameter values, the thickness value of the CAP layer, the thickness value of the TSV layer (through silicon via layer), the thickness value of the integrated circuit chip 20 and the thickness value of the half-etched area 11 have a greater influence on the frequency offset value of the micro-electromechanical chip 30, among which the thickness value of the CAP layer and the thickness value of the TSV layer (through silicon via layer) have the greatest influence. The frequency offset caused by the stress influence in the chip packaging process is adjusted by optimizing and adjusting the above numerical parameters; in one embodiment, the corresponding parameter values ​​are selected as the thickness value of the TSV layer (through silicon via layer) of 100 μm, the thickness value of the CAP layer of 20 μm, the thickness value of the integrated circuit chip 20 of 50 μm, the thickness value of the half-etched area 11 of 50 μm, the width value of the micro-electromechanical chip 30 is selected in the range of 400 μm to 700 μm, and the width value of the integrated circuit chip 20 is selected in the range of 800 μm to 1600 μm. The size scheme in this embodiment can obtain a better size optimization result to reduce the frequency offset influence caused by packaging stress.

[0040] In the above manner, through simulation tests, the corresponding required values ​​are selected according to the degree of influence of different parameter values ​​on the frequency offset value of the micro-electromechanical chip 30, so as to reduce the influence of its packaging stress on its frequency offset, thereby optimizing the result.

[0041] See also Figure 3 As shown, Figure 3 It is a structural schematic diagram of the second embodiment of the micro-electromechanical system provided by the present application; wherein the micro-electromechanical system 100 is packaged by a process of wire bonding combined with flip-chip welding. Specifically, the micro-electromechanical system 100 includes: a lead frame 10; an integrated circuit chip 20, which is arranged on the lead frame 10, and a third pad is arranged on the side of the integrated circuit chip 20 away from the lead frame 10, and the third pad is coupled to the lead frame 10 through a lead a; a micro-electromechanical chip 30, which is arranged on the integrated circuit chip 20, and a fourth pad is arranged on the side of the micro-electromechanical chip 30 facing the integrated circuit chip 20, and the fourth pad is flip-coupled to the integrated circuit chip 20 through a conductive bump b; wherein the micro-electromechanical chip 30 includes a CAP layer and a TSV layer, and the thickness of the CAP layer is 20μm to 70μm. Refer to Table 2, which is a simulation parameter table of the second embodiment of the micro-electromechanical system provided by the present application.

[0042] Table 2:

[0043]

[0044]

[0045] Specifically, a simulation test is performed on the thickness value of the CAP layer in the micro-electromechanical chip 30, and the thickness value parameters are selected as 20μm, 30μm, 40μm, 50μm, 60μm, and 70μm, and simulation tests are performed respectively. As shown in Table 2, the thickness value of the CAP layer in the micro-electromechanical chip 30 is in the range of 20μm to 70μm. As the thickness value gradually increases, the corresponding frequency offset value of the micro-electromechanical chip 30 gradually decreases, and the frequency offset value decreases by about 11ppm. Therefore, in one embodiment, the corresponding thickness value of the CAP layer in the micro-electromechanical chip 30 is selected to be 70μm.

[0046] Among them, Flip-Chip, also known as flip-chip welding or flip-chip packaging, is a type of chip packaging technology. This packaging technology is mainly different from the interconnection method of wire bonding. Flip-chip packaging is named after the bare chip is grown with bumps (bμmp), and then the bare chip is turned over to connect the bumps directly to the lead frame 10.

[0047] Optionally, in one embodiment, the lead frame 10 includes a half-etched area 11 facing the side of the integrated circuit chip 20, and the thickness of the half-etched area 11 is 50μm to 150μm; and / or the width of the micro-electromechanical chip 30 is 400μm to 700μm. The simulation calculation of its structure shows that when the half-etched area 11 of the lead frame 10 is simulated, the thickness of the half-etched area 11 is selected as 50μm, 100μm, and 150μm for simulation respectively. The simulation results show that when the thickness of the half-etched area 11 is within the range of 50μm to 150μm, the frequency offset of the micro-electromechanical chip 30 gradually increases, and the frequency offset increases by about 3ppm; as the thickness of the half-etched area 11 gradually increases, the frequency offset of the micro-electromechanical chip 30 gradually increases, so in one embodiment, the thickness of the half-etched area 11 is selected as 50μm.

[0048] Optionally, in one embodiment, the thickness of the integrated circuit chip 20 is 50 μm to 200 μm; and / or the width of the integrated circuit chip 20 is 800 μm to 1600 μm. As shown in Table 2, in the corresponding simulation test, the width parameters of the integrated circuit chip 20 are selected as 800 μm, 900 μm, 1000 μm, 1100 μm, 1200 μm, 1300 μm, 1400 μm, 1500 μm, and 1600 μm, and simulation tests are performed respectively. The simulation results show that the width of the integrated circuit chip 20 is within the range of 800 μm to 1600 μm. As the width of the integrated circuit chip 20 increases, the frequency offset value of the corresponding micro-electromechanical chip 30 gradually decreases, and the frequency offset value decreases by about 1 ppm. Therefore, in one embodiment, the width value of the corresponding integrated circuit chip 20 is selected as 1600 μm. It also includes a simulation test on the thickness value of the integrated circuit chip 20, and the thickness value parameters of the integrated circuit chip 20 are selected as 50μm, 100μm, 150μm, and 200μm, and simulations are performed respectively. The simulation results show that the thickness value of the integrated circuit chip 20 is in the range of 50μm to 200μm. As the thickness value of the integrated circuit chip 20 increases, the frequency offset value of the corresponding micro-electromechanical chip 30 gradually increases, and the frequency offset value increases by about 1ppm. Therefore, in one embodiment, the corresponding thickness value of the integrated circuit chip 20 is selected as 50μm. In addition, a simulation test is performed on the width of the microelectromechanical chip 30, wherein the width parameters of the microelectromechanical chip 30 are selected as 400μm, 450μm, 500μm, 550μm, 600μm, 650μm, and 700μm, and simulation tests are performed on them respectively. The simulation results show that the width parameter of the microelectromechanical chip 30 is in the range of 400μm to 700μm, and as the width value of the microelectromechanical chip 30 increases, the frequency offset value of the microelectromechanical chip 30 gradually increases, and the frequency offset value increases by about 3ppm. Therefore, in one embodiment, the corresponding width value of the microelectromechanical chip 30 is selected as 400μm.

[0049] Optionally, in one embodiment, the thickness of the TSV layer is 50 μm to 100 μm. Among them, the thickness value of the TSV layer (silicon through hole layer) in the micro-electromechanical chip 30 is simulated and tested, and its thickness value parameters are selected as 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, and 100 μm, and simulation tests are performed respectively. As shown in Table 2, the thickness value of the TSV layer (silicon through hole layer) in the micro-electromechanical chip 30 is within the range of 50 μm to 100 μm. As its thickness value gradually increases, its corresponding frequency offset value of the micro-electromechanical chip 30 gradually decreases, and its frequency offset value increase value is less than about 1 ppm, and its value has little effect on the frequency offset. Therefore, in one embodiment, the thickness value of the TSV layer (silicon through hole layer) in the micro-electromechanical chip 30 corresponding to it is selected as 100 μm.

[0050] Furthermore, it can be seen from the above embodiments and the parameter value simulation structure of Table 2 that, in terms of the degree of influence of the parameter values, the thickness value of the CAP layer has a greater influence on the frequency offset, followed by the width value of the micro-electromechanical chip 30 and the thickness value of the half-etched area 11; and in one embodiment, the corresponding parameter values ​​are selected as the width value of the micro-electromechanical chip 30 is 400μm, the thickness value of the CAP layer is 70μm, and the thickness value of the half-etched area 11 is 50μm, the thickness value of the TSV layer (silicon through via layer) is selected in the range of 50μm to 100μm, the thickness value of the integrated circuit chip 20 is selected in the range of 50μm to 200μm, and the width value of the integrated circuit chip 20 is selected in the range of 800μm to 1600μm. The size scheme in this embodiment can obtain better size optimization results to reduce the influence of frequency offset caused by packaging stress.

[0051] In the above manner, through simulation tests, the corresponding required values ​​are selected according to the degree of influence of different parameter values ​​on the frequency offset value of the micro-electromechanical chip 30, so as to reduce the influence of its packaging stress on its frequency offset, thereby optimizing the result.

[0052] See also Figure 4 As shown, Figure 4 It is a structural schematic diagram of the third embodiment of the micro-electromechanical system provided by the present application; wherein the micro-electromechanical system 100 is packaged by a flip-chip process, specifically, the micro-electromechanical system 100 includes: a lead frame 10; an integrated circuit chip 20, which is arranged on the lead frame 10, and a fifth pad is arranged on the side of the integrated circuit chip 20 facing the lead frame 10, and the fifth pad is coupled to the lead frame 10 through a conductive bump b; a micro-electromechanical chip 30, which is arranged on the side of the integrated circuit chip 20 facing the lead frame 10, and a fourth pad is arranged on the side of the micro-electromechanical chip 30 facing the integrated circuit chip 20, and the fourth pad is flip-chip coupled to the integrated circuit chip 20 through a conductive bump b; wherein the lead frame 10 includes a half-etched area 11 facing the side of the integrated circuit chip 20, and the thickness of the half-etched area 11 is 50μm to 150μm.

[0053] Wherein, referring to Table 3, Table 3 is a simulation parameter table of the third embodiment of the micro-electromechanical system provided by the present application.

[0054] Table 3:

[0055]

[0056] The structure is simulated and calculated. When simulating the half-etched area 11 of the lead frame 10, the thickness of the half-etched area 11 is selected as 50μm, 100μm, and 150μm for simulation. The simulation results show that when the thickness of the half-etched area 11 is in the range of 50μm to 150μm, the frequency offset of the micro-electromechanical chip 30 gradually increases, and the frequency offset increases by about 14ppm. As the thickness of the half-etched area 11 gradually increases, the frequency offset of the micro-electromechanical chip 30 gradually increases. Therefore, in one embodiment, the thickness value of the half-etched area 11 is selected to be 50μm.

[0057] Optionally, in one embodiment, the micro-electromechanical chip 30 includes a CAP layer and a TSV layer, and the thickness of the TSV layer is 50μm to 100μm. Specifically, by using simulation test, the influence of the thickness of the TSV layer on the frequency offset value of the micro-electromechanical chip 30 is measured, as shown in Table 3, the thickness value of the TSV layer (silicon through hole layer) in the micro-electromechanical chip 30 is simulated and tested, and the thickness value parameters are selected as 50μm, 60μm, 70μm, 80μm, 90μm, and 100μm, and simulation tests are performed respectively. As shown in Table 3, the thickness value of the TSV layer (silicon through hole layer) in the micro-electromechanical chip 30 is within the range of 50μm to 100μm. As the thickness value gradually increases, the corresponding frequency offset value of the micro-electromechanical chip 30 gradually decreases, and the frequency offset value decreases by about 8ppm. Therefore, in one embodiment, the thickness value of the TSV layer (silicon through hole layer) in the micro-electromechanical chip 30 is selected as 100μm.

[0058] Optionally, in one embodiment, the thickness of the CAP layer is 20 μm to 70 μm. Among them, the thickness value of the CAP layer in the micro-electromechanical chip 30 is simulated and tested, and its thickness value parameters are selected as 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, and 70 μm, and simulation tests are performed respectively. As shown in Table 3, the thickness value of the CAP layer in the micro-electromechanical chip 30 is within the range of 20 μm to 70 μm. As its thickness value gradually increases, its corresponding frequency offset value of the micro-electromechanical chip 30 gradually decreases, and its frequency offset value decreases by about 3 ppm. Therefore, in one embodiment, the thickness value of the CAP layer in the micro-electromechanical chip 30 corresponding to it is selected as 70 μm.

[0059] Optionally, in one embodiment, the width of the micro-electromechanical chip 30 is 400 μm to 700 μm. A simulation test is performed on the width value of the micro-electromechanical chip 30, wherein the width parameters of the micro-electromechanical chip 30 are selected as 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, and 700 μm, and simulation tests are performed on them respectively. The simulation results show that the width parameter of the micro-electromechanical chip 30 is within the range of 400 μm to 700 μm, and as the width value of the micro-electromechanical chip 30 increases, the frequency offset value of the micro-electromechanical chip 30 gradually increases, and the frequency offset value increases by about 2 ppm. Therefore, in one embodiment, the width value of the corresponding micro-electromechanical chip 30 is selected as 400 μm.

[0060] Optionally, in one embodiment, the width of the integrated circuit chip 20 is 800 μm to 1600. As shown in Table 3, in the corresponding simulation test, the width parameters of the integrated circuit chip 20 are selected as 800 μm, 900 μm, 1000 μm, 1100 μm, 1200 μm, 1300 μm, 1400 μm, 1500 μm, and 1600 μm, and simulation tests are performed respectively. The simulation results show that the width of the integrated circuit chip 20 is within the range of 800 μm to 1600. As the width of the integrated circuit chip 20 increases, the frequency offset value of the corresponding micro-electromechanical chip 30 gradually increases, and the frequency offset value increases by about 1 ppm. Therefore, in one embodiment, the width value of the corresponding integrated circuit chip 20 is selected as 800 μm. It also includes a simulation test on the thickness value of the integrated circuit chip 20, and the thickness value parameters of the integrated circuit chip 20 are selected as 50μm, 100μm, 150μm, and 200μm, and simulations are performed respectively. The simulation results show that the thickness value of the integrated circuit chip 20 is in the range of 50μm to 200μm. As the thickness value of the integrated circuit chip 20 increases, the frequency offset value of the corresponding micro-electromechanical chip 30 gradually decreases, and the frequency offset value decreases by about 3ppm. Therefore, in one embodiment, the corresponding thickness value of the integrated circuit chip 20 is selected as 200μm.

[0061] Furthermore, it can be seen from the above embodiments and the parameter value simulation structure of Table 3 that, as for the degree of influence of the parameter values, the thickness value of the half-etched area 11 and the thickness value of the TSV layer (through silicon via layer) have a greater influence on the frequency offset value of the micro-electromechanical chip 30, followed by the thickness value of the CAP layer, the thickness value of the integrated circuit chip 20 and the width value of the micro-electromechanical chip 30. Among them, the thickness value of the half-etched area 11 has the greatest influence, so for its optimization, the above-mentioned structural dimensions are mainly selected for adjustment and optimization to reduce its influence on the frequency offset of the micro-electromechanical chip 30. In one embodiment, the corresponding parameter values ​​are selected as a width value of 400μm for the micro-electromechanical chip 30, a thickness value of 100μm for the TSV layer (through silicon via layer), a thickness value of 70μm for the CAP layer, a thickness value of 200μm for the integrated circuit chip 20, and a thickness value of 50μm for the half-etched area 11. The width value of the integrated circuit chip 20 is selected within the range of 800μm to 1600. The size scheme in this embodiment can obtain better size optimization results and reduce the impact of frequency offset caused by packaging stress.

[0062] In the above manner, through simulation tests, the corresponding required values ​​are selected according to the degree of influence of different parameter values ​​on the frequency offset value of the micro-electromechanical chip 30, so as to reduce the influence of its packaging stress on its frequency offset, thereby optimizing the result.

[0063] It can be understood that in the above-mentioned multiple embodiments, in addition to the influence on the frequency offset of the micro-electromechanical chip 30, it is also necessary to consider the miniaturization of the corresponding overall structural dimensions. Therefore, in some embodiments, if the influence of some structural dimensions on the frequency offset is relatively small, it can be considered that there is a requirement for smaller structural dimensions, and the size selection and adjustment thereof are biased. It is not necessary to select the minimum value of the influence on the frequency offset. Different size combinations are used for the structure, and the actual corresponding structural dimensions are selected to optimize the packaging size and reduce the influence of the packaging stress during packaging on the frequency offset.

[0064] Through the above method, according to the different degrees of influence of various structural size parameters in the micro-electromechanical system 100 on its frequency deviation, each structural dimension is adjusted to reduce the influence of the frequency deviation of the micro-electromechanical chip 30 caused by the existence of packaging stress during the packaging process, thereby improving the production efficiency and production yield.

[0065] In addition, the MEMS resonator can be formed in or on a semiconductor-on-insulator (SOI) substrate using the lithography, etching, deposition and / or doping techniques of one embodiment. For the sake of brevity, such manufacturing techniques are not discussed herein. However, all techniques for forming or manufacturing MEMS resonator structures, whether now known or later developed, are intended to fall within the scope (e.g., using the formation, lithography, etching and / or deposition techniques of one embodiment of standard or oversized ("thick") wafers (not shown) and / or bonding techniques (i.e., bonding two standard wafers together, wherein the lower / bottom wafer includes a sacrificial layer (e.g., silicon oxide) disposed thereon, and the upper / top wafer is thereafter thinned (ground down or back) and polished to receive mechanical structures therein or thereon).

[0066] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A micro-electromechanical system, characterized in that: The micro-electromechanical system comprises: Lead frame; An integrated circuit chip is arranged on the lead frame, a first pad is arranged on a side of the integrated circuit chip away from the lead frame, and the first pad is coupled to the lead frame through a lead wire; A micro-electromechanical chip is arranged on the integrated circuit chip, a second pad is arranged on a side of the micro-electromechanical chip away from the integrated circuit chip, and the second pad is coupled to the integrated circuit chip through a lead wire; Wherein, the micro-electromechanical chip comprises a CAP layer and a TSV layer, and the thickness of the CAP layer is 20 μm to 70 μm; and / or The TSV layer has a thickness of 50 μm to 100 μm.

2. The micro-electromechanical system according to claim 1, characterized in that: The lead frame comprises a half-etched area facing the side of the integrated circuit chip, and the thickness of the half-etched area is 50 μm to 150 μm; and / or The thickness of the integrated circuit chip is 50 μm to 200 μm.

3. The micro-electromechanical system according to claim 1, characterized in that: The width of the integrated circuit chip is 800 μm to 1600 μm; and / or The width of the micro-electromechanical chip is 400 μm to 700 μm.

4. A micro-electromechanical system, characterized in that: The micro-electromechanical system comprises: Lead frame; An integrated circuit chip is arranged on the lead frame, a third pad is arranged on a side of the integrated circuit chip away from the lead frame, and the third pad is coupled to the lead frame through a lead wire; A micro-electromechanical chip is arranged on the integrated circuit chip, a fourth pad is arranged on a side of the micro-electromechanical chip facing the integrated circuit chip, and the fourth pad is flip-chip coupled to the integrated circuit chip through a conductive bump; The micro-electromechanical chip includes a CAP layer and a TSV layer, and the thickness of the CAP layer is 20 μm to 70 μm.

5. The micro-electromechanical system according to claim 4, characterized in that: The lead frame comprises a half-etched area facing the side of the integrated circuit chip, and the thickness of the half-etched area is 50 μm to 150 μm; and / or The width of the micro-electromechanical chip is 400 μm to 700 μm.

6. The micro-electromechanical system according to claim 4, characterized in that: The thickness of the integrated circuit chip is 50 μm to 200 μm; and / or The width of the integrated circuit chip is 800 μm to 1600 μm; and / or The TSV layer has a thickness of 50 μm to 100 μm.

7. A micro-electromechanical system, characterized in that: The micro-electromechanical system comprises: Lead frame; An integrated circuit chip is arranged on the lead frame, a fifth pad is arranged on a side of the integrated circuit chip facing the lead frame, and the fifth pad is coupled to the lead frame through a conductive bump; A micro-electromechanical chip is arranged on a side of the integrated circuit chip facing the lead frame, a fourth pad is arranged on the side of the micro-electromechanical chip facing the integrated circuit chip, and the fourth pad is flip-chip coupled to the integrated circuit chip through a conductive bump; Wherein, the lead frame comprises a half-etched area facing the side of the integrated circuit chip, and the thickness of the half-etched area is 50 μm to 150 μm.

8. The micro-electromechanical system according to claim 7, characterized in that: The micro-electromechanical chip comprises a CAP layer and a TSV layer, and the thickness of the TSV layer is 50 μm to 100 μm; and / or The thickness of the CAP layer is 20 μm to 70 μm.

9. The micro-electromechanical system according to claim 7, characterized in that: The width of the micro-electromechanical chip is 400 μm to 700 μm.

10. The micro-electromechanical system according to claim 7, characterized in that: The thickness of the integrated circuit chip is 50 μm to 200 μm; and / or The width of the integrated circuit chip is 800 μm to 1600 μm.

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