Integrated chip

Abstract

The utility model relates to an integrated chip. The integrated chip comprises a groove cluster which is arranged on the front surface of a substrate and is provided with a plurality of grooves, the inner wall of each groove is lined with an insulating layer, and each groove is filled with a conductive material. A first doped region, a heavily doped region, a third doped region and a connection region are implanted in the first well region. A second doped region and a fourth doped region are implanted in the second well region. And the third doped region is electrically connected to the heavily doped region, and when a surge signal of the third doped region enables a node between the first doped region and the connection region to be reversely broken down, the bipolar crystal between the first doped region and the substrate and the bipolar transistor between the third doped region and the first well region and the bipolar transistor between the fourth doped region and the first well region are triggered to be conducted so as to discharge surge. And the equivalent voltage of the storage charge of the conductive material in the groove is used for pinching off a current channel flowing to the substrate from a node in a reverse breakdown state.

Description

Technical Field

[0001] The utility model mainly relates to the technical field of storage hard disks, and more specifically, to an integrated chip capable of improving the anti-surge capability of hard disks and a corresponding method capable of improving the anti-surge capability of hard disks. Background Art

[0002] Traditional hard drive hot-swap designs have many shortcomings. After the hard drive motherboard is hot-plugged into the system, the surge voltage generated cannot be suppressed. This instantaneous high voltage and high current will directly impact related electronic components, causing on-the-spot damage to the related components connected to the hard drive or reducing the usable life of the components. Because the hard drive motherboard has board-level capacitors or line parasitic capacitors, after the hard drive is inserted, the storage system connected to the hard drive needs to power the hard drive and its motherboard, and various capacitors are charged, which will transiently lower the system voltage, damaging both the hard drive and the system. How to improve the hard drive's surge resistance is a serious problem that the industry needs to solve urgently. Utility Model Content

[0003] The present application relates to an integrated chip (or integrated chip structure), characterized in that it includes:

[0004] A groove cluster having a plurality of grooves is provided on a front surface of a substrate of a first conductivity type, wherein an inner wall of each groove is provided with an insulating layer and the interior of each groove is filled with a conductive material;

[0005] A first well region of the second conductivity type is implanted on the front side of the substrate, and a second well region of the first conductivity type is implanted on the back side of the substrate, wherein the first well region and the second well region are located at opposite sides of the trench cluster respectively;

[0006] A first doped region of the second conductivity type, a heavily doped region, a third doped region of the first conductivity type, and a connecting region implanted in the first well region, wherein the first doped region and the conductive material in each trench have the same potential;

[0007] A second doping region of the second conductivity type and a fourth doping region of the first conductivity type implanted in the second well region;

[0008] A conductive layer disposed on the back side of the substrate and having a common electrical potential with the second and fourth doped regions;

[0009] Under the condition that the surge signal connected to the heavily doped region and the third doped region causes the node between the first doped region and the junction region to reversely break down, a bipolar transistor between the first and second doped regions and the substrate and another bipolar transistor between the third and fourth doped regions and the first well region are triggered to conduct and discharge the surge signal;

[0010] The equivalent voltage of the stored charges of the conductive material in each trench is used to cut off the current path from the node in the reverse breakdown state to the substrate.

[0011] The above-mentioned integrated chip: further includes a top dielectric layer covering the front side of the substrate and a bottom dielectric layer covering the back side of the substrate; a top electrode layer for receiving the surge signal covers the top dielectric layer, and the top electrode layer passes through a through hole provided in the top dielectric layer and contacts the heavily doped region and the third doped region respectively;

[0012] A bottom electrode layer for connecting to a reference ground covers the bottom dielectric layer. The bottom electrode layer passes through a through hole arranged in the bottom dielectric layer and contacts the second and fourth doping regions and the conductive layer respectively.

[0013] The above-mentioned integrated chip also includes an interconnect electrode layer covering the top dielectric layer, the interconnect electrode layer passes through the through holes provided in the top dielectric layer and contacts the first doped region and the conductive materials in each groove respectively, thereby electrically connecting the first doped region and the conductive materials in each groove.

[0014] The integrated chip mentioned above also includes one or more slots opened on the front side of the substrate, spanning the grooves and extending to the first doping region, each slot having an inner wall liner attached with an isolation layer and each slot filled with a conductor material;

[0015] The slot body is provided with contact holes at the intersection position intersecting with the groove and at the part contacting with the first doping region, so that the conductor material in each slot body is electrically connected to the conductive material in the groove and the first doping region respectively.

[0016] The above-mentioned integrated chip also includes one or more buried regions implanted on the back side of the substrate and between the bottom of the groove and the conductive layer, the buried regions are of the second conductive type (sometimes the first conductive type is allowed), and the buried regions are separated from the conductive layer or directly touch the conductive layer.

[0017] The above-mentioned integrated chip: a channel area for allowing current of a pair of bipolar transistors to flow is reserved at a position of the substrate located between multiple grooves, and the channel area guides the current flowing through the pair of bipolar transistors from one side of the groove cluster through the groove cluster and flows laterally to the other side of the groove cluster.

[0018] The above-mentioned integrated chip: the current channel in the local area of ​​the substrate between a groove located closest to the first well region in the groove cluster and the first well region is cut off by the equivalent voltage; the outline of the connecting region in the first well region is set to be separated from the surface layer of the front side of the substrate; or the outline of the connecting region in the first well region is set to touch the surface layer of the front side of the substrate.

[0019] The above-mentioned integrated chip: the current channel in the local area between the groove of the substrate located closest to the first well area in the groove cluster and the first well area is cut off by the equivalent voltage; the first type of shielding area of ​​the first conductivity type and the second type of shielding area of ​​the second conductivity type are alternately implanted in the local area, and the first and second types of shielding areas reach the surface layer of the front side of the substrate in the local area.

[0020] The above-mentioned integrated chip: a channel area is reserved at a position of the substrate between a plurality of the grooves for allowing current of a pair of bipolar transistors to flow; based on the condition that the current channel is cut off by the equivalent voltage, the first and second types of shielding areas are mutually depleted under the action of the equivalent voltage to lock the channel area between the plurality of grooves, thereby allowing the actual channel for the current flow of a pair of bipolar transistors to move from the initial channel area down to the substrate area at the bottom of the groove.

[0021] The present application relates to a method for improving the surge resistance of a hard disk, using an integrated chip to absorb surge signals (surge voltage / current) injected into a protected line in the hard disk: the integrated chip (or integrated chip structure) includes:

[0022] A groove cluster having a plurality of grooves is provided on a front surface of a substrate of a first conductivity type, wherein an inner wall of each groove is provided with an insulating layer and the interior of each groove is filled with a conductive material;

[0023] A first well region of the second conductivity type is implanted on the front side of the substrate, and a second well region of the first conductivity type is implanted on the back side of the substrate, wherein the first well region and the second well region are located at opposite sides of the trench cluster respectively;

[0024] A first doped region of the second conductivity type, a heavily doped region, a third doped region of the first conductivity type, and a connecting region implanted in the first well region, wherein the first doped region and the conductive material in each trench have the same potential;

[0025] A second doping region of the second conductivity type and a fourth doping region of the first conductivity type implanted in the second well region;

[0026] A conductive layer disposed on the back side of the substrate and having a common electrical potential with the second and fourth doped regions;

[0027] Under the condition that the surge signal applied to the heavily doped region and the third doped region causes the node between the first doped region and the junction region to reversely break down, a bipolar transistor between the first and second doped regions and the substrate and another bipolar transistor between the third and fourth doped regions and the first well region are triggered to conduct and discharge the surge signal;

[0028] The equivalent voltage of the stored charge of the conductive material in each groove is used to cut off the current path from the node to the substrate under the reverse breakdown condition; the method comprises:

[0029] The surge signal injected into the protected circuit in the hard disk is guided to charge the capacitance between the groove cluster and the conductive layer, so as to form storage charge at the conductive material in each groove;

[0030] In the process of using a pair of bipolar transistors that are triggered to conduct to discharge the surge signal, the stored charge at the capacitor is used to reversely discharge and deplete the junction area, thereby locking the current channel at the node.

[0031] The above method: the integrated chip includes a top dielectric layer covering the front side of the substrate and a bottom dielectric layer covering the back side of the substrate; the top electrode layer receiving the surge signal covers the top dielectric layer, and the top electrode layer passes through the through hole of the top dielectric layer to contact the heavily doped region and the third doped region; the bottom electrode layer connected to the reference ground covers the bottom dielectric layer, and the bottom electrode layer passes through the through hole provided in the bottom dielectric layer to contact the second and fourth doped regions and the conductive layer.

[0032] The above method: the integrated chip also includes an interconnect electrode layer covering the top dielectric layer, the interconnect electrode layer passes through the through holes provided in the top dielectric layer and contacts the first doped region and the conductive materials in each groove respectively, thereby electrically connecting the first doped region and the conductive materials in each groove.

[0033] The above method: the integrated chip also includes one or more grooves opened on the front side of the substrate, spanning the grooves and extending to the first doping region, the inner wall of each groove is lined with an isolation layer and the interior of each groove is filled with a conductive material; the grooves are provided with contact holes at the intersection positions intersecting with the grooves and at the partial positions contacting the first doping region, so that the conductive material in each groove is electrically connected to the conductive material in the groove and the first doping region respectively.

[0034] The above method: the integrated chip also includes one or more buried regions implanted on the back side of the substrate and between the bottom of the groove and the conductive layer, the buried regions are of the second conductive type (sometimes the first conductive type is allowed), and the buried regions are spaced apart from the conductive layer or directly touch the conductive layer.

[0035] The above method: In the integrated chip, a channel area for allowing the current of a pair of bipolar transistors to flow is reserved at a position of the substrate located between the plurality of the grooves, and the channel area guides the current flowing through the pair of bipolar transistors from one side of the groove cluster through the groove cluster and flows laterally to the other side of the groove cluster.

[0036] The above method: in the integrated chip, the current channel of the local area of ​​the substrate between the groove located closest to the first well region in the groove cluster and the first well region is cut off by an equivalent voltage; the outline of the connecting region in the first well region is set to be separated from the surface layer of the front side of the substrate; or the outline of the connecting region in the first well region is set to touch the surface layer of the front side of the substrate.

[0037] The above method: in the integrated chip, the current channel of a local area of ​​the substrate between a trench in the trench cluster closest to the first well region and the first well region is cut off by the equivalent voltage;

[0038] The local area is alternately implanted with first-type shielding regions of the first conductivity type and second-type shielding regions of the second conductivity type, and the first and second-type shielding regions reach upward to the surface layer of the front side of the substrate at the local area.

[0039] The above method: in the integrated chip, a channel region is reserved at a position of the substrate between the plurality of the trenches for allowing current of a pair of bipolar transistors to flow;

[0040] Based on the condition that the current channel is cut off by the equivalent voltage, the first and second types of shielding regions deplete each other under the action of the equivalent voltage to lock the channel regions between multiple trenches, thereby allowing the actual channel for current flow of a pair of bipolar transistors to move from the original channel region down to the substrate region at the bottom of the trench.

[0041] The present application relates to an integrated chip (or integrated chip structure), characterized in that it includes:

[0042] A trench cluster having a plurality of trenches is provided on the front surface of a P-type substrate, wherein an insulating layer is provided on the inner wall of each trench and a conductive material is filled inside each trench;

[0043] An N-type first well region is located on the front side of the substrate, and a P-type second well region is located on the back side of the substrate, wherein the first well region and the second well region are located on opposite sides of a trench cluster;

[0044] The N-type first doping region, the heavily doped region, the P-type third doping region, the connecting region, the first doping region and the conductive materials in each trench located in the first well region have the same potential;

[0045] An N-type second doping region and a P-type fourth doping region located in the second well region;

[0046] A conductive layer disposed on the back side of the substrate and having a common electrical potential with the second and fourth doped regions;

[0047] The surge signal applied to the heavily doped region and the third doped region causes the node between the first doped region and the junction region to reversely break down, and the first bipolar transistor between the first and second doped regions and the substrate and the second bipolar transistor between the third and fourth doped regions and the first well region are triggered to conduct and discharge the surge signal (surge voltage / current);

[0048] The equivalent voltage of the stored charges of the conductive material in each trench is used to pinch off the current path from the node that is in (or enters) a reverse breakdown state to the substrate.

[0049] One of the advantages of this application: For hard disks that are frequently hot-plugged, there is a high probability of surge voltage or surge current in the protected circuits in the hard disk, such as metal casings or electronic component solder joints or plug-in terminals or onboard wiring or electronic circuits carrying parasitic resonant circuits. When faced with a surge signal, this application can trigger the integrated chip to generate a surge signal discharge path to release the surge or remove the surge. It can prevent hard disk data loss and avoid damage to the hard disk's electronic circuits. The physical structure of the integrated chip can not only withstand low voltage but also withstand extremely high voltage. Based on current channel latching, the integrated chip can easily cope with extremely high voltage levels applied without being burned by high currents. This means that in addition to the nanosecond or millisecond surges themselves being resisted, the low-frequency pulsating voltage components carried by the surge mixing are also resisted.

[0050] The second advantage of this application: the node breakdown that triggers the integrated chip to turn on and forms a discharge path is only broken down and drained during the triggering stage. The drainage is based on guiding the bipolar transistor to be triggered and turned on. The node itself does not bear a large current after completing the drainage task, which ensures that the relevant functional modules of the node will not be damaged by surges. This mode can cope with recurring and unpredictable ubiquitous surge signals. If the node and the relevant functional modules of the node are completely or partially damaged by a single extremely powerful surge impact, then the subsequent surge will no longer be able to continue to trigger the surge discharge function of the integrated chip, and the circuit protected by the integrated chip will lose protection.

[0051] The third advantage of this application: The integrated chip suppresses surges based on the mode of using large discharge currents. Specifically, it uses a pair of bipolar transistors to unload voltage. It is easy to understand that the bipolar transistor pair is combined into a dual current discharge path. The advantage is that it can offset the high power of the surge more quickly. However, there is also a current mismatch problem between the bipolar transistor pairs. This application is based on solving the current mismatch of the bipolar transistor pair and the concern that the current difference of the mismatched current will flow into the node in large quantities. Unlike the node damage caused by a single extremely powerful surge impact mentioned in the previous article, the current mismatch is that the current difference between the two bipolar transistors is too large and is forced to squeeze the difference current into the position of the series-parallel node diode, thereby damaging the node. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to make the above purposes, features and advantages more understandable, the following text will explain the specific implementation methods in detail in conjunction with the drawings. After reading the following description and referring to the following drawings, the features and advantages of the present application will become apparent.

[0053] Figure 1 The internal physical structure diagram of the integrated chip and the related circuit architecture are shown.

[0054] Figure 2 It is the top electrode layer of the top dielectric layer and the bottom electrode layer of the bottom dielectric layer.

[0055] Figure 3 It is one or more grooves opened on the front side of the substrate and spanning across each groove.

[0056] Figure 4 The interconnection function of the slot body is based on the fact that no interconnection electrode layer is used in the top dielectric layer.

[0057] Figure 5 The first type of shielding area and the second type of shielding area are implanted alternately to cut off the current channel.

[0058] Figure 6 The capacitor is charged to form a stored charge at the conductive material in each trench.

[0059] Figure 7 The stored charge of the capacitor is used to discharge in reverse order to deplete the junction area and latch the node. DETAILED DESCRIPTION

[0060] The technical solutions disclosed in the present application are clearly and completely described below in conjunction with various specific embodiments. However, the described embodiments are only embodiments used for narrative explanation in the present application rather than all embodiments. Based on these embodiments, technicians in this field should realize that any solution obtained without creative work falls within the scope of protection of the present application.

[0061] See also Figure 1 , demonstrated an integrated chip structure, the main purpose of which is to improve the hard disk's surge resistance. The integrated chip is used to absorb the surge signal (surge voltage / current) injected into the protected line of the hard disk, avoiding surge-induced damage to the hard disk and the accompanying data loss.

[0062] See also Figure 1As the main component of the server, the hard disk usually needs to be hot-swapped at high frequency in the disk slot when the storage capacity is expanded or reduced. This will cause surges in various lines of the hard disk with a high probability. For example, the power supply of the server motherboard suddenly surges into the power supply line of the hard disk. In fact, surges have diverse characteristics. The surges attached to the hard disk are mainly reflected in external factors and internal factors. The typical source of external factors is the lightning phenomenon of the power system, while the typical source of internal factors is the start-stop failure of the server. The characteristics of external surges caused by lightning strikes are single-phase pulse type and the energy of pulse surges is huge. The voltage can quickly rise from hundreds of volts to tens of thousands of volts in a few microseconds. Such high energy can be transmitted over a considerable distance. In the power system of the server, the high-frequency operation of the switching power supply and the input and removal of many hard disk loads will cause the voltage and current on the power supply line to fluctuate and introduce noise. The core goal of the integrated chip structure is to eliminate pulse-type transient surges and mixed low-frequency pulsating components.

[0063] See also Figure 1 The surge caused by arc or lightning in the power supply system is very harmful. The protected circuits in the hard disk include the metal shell of the hard disk, the electronic components inside the hard disk and their joints or solder joints, the plug-in terminals of the hard disk or the onboard wiring of the hard disk. The focus of surge protection is to absorb and suppress this part of the surge energy. In addition, due to the parasitic capacitance and inductance of the hard disk's own circuit board and the server motherboard connected to the hard disk, parasitic oscillation characteristics are usually shown in certain frequency bands. Due to the high-frequency components in the surge, resonance and the resulting high overvoltage are generated on the line, which causes secondary damage to the hard disk and related hardware of the server.

[0064] See also Figure 1 , the traditional hot-swap circuit of storage hard disk has many disadvantages: when expanding capacity, for example, after the circuit board carrying the hard disk is hot-plugged into the entire server, the surge voltage generated by hot-plugging cannot be suppressed. This instantaneous high voltage and high current will directly impact the electronic components and hard disks deployed on the circuit board, causing direct damage to the electronic components on the circuit board or shortening the service life of the components. Hard disks basically use flash memory storage particles. At the moment of hot-plugging, the sudden voltage and current surge at the plug-in terminals of the hard disk data port or power port can easily flow into the storage particles through the plug-in terminals and damage storage particles such as NAND and NOR.

[0065] See also Figure 1In an optional embodiment, the preparation of the integrated chip in this article is based on a wafer process such as a power semiconductor preparation process, such as preparation on a substrate PS or an epitaxial layer of a first conductivity type. The first conductivity type is assumed to be a P-type semiconductor or a P conductivity type, the first and second conductivity types are relative or opposite, and the second conductivity type is assumed to be an N-type semiconductor or an N conductivity type. The second and first conductivity types can also be swapped with each other, the first conductivity type is assumed to be an N-type semiconductor or an N conductivity type, the second and first conductivity types are relative or opposite, and the second conductivity type is assumed to be a P-type semiconductor or a P conductivity type. The aforementioned relationship between the first and second conductivity types applies to the context of this application.

[0066] See also Figure 1 In an optional embodiment, the first well region of the second conductivity type implanted on the front side of the substrate PS can be represented by NW, and the implanted dopant can be based on N-type semiconductor material. The front side implantation can adopt a conventional ion implantation process, which shows that the present application can be implemented based on the existing semiconductor process in the industry.

[0067] See also Figure 1 In an optional embodiment, the second well region of the first conductivity type implanted on the back side of the substrate PS can be represented by PW, and the implanted dopant can be based on a P-type semiconductor material. The back side implantation can adopt a conventional ion implantation process, so this application can be implemented based on the existing semiconductor process in the industry.

[0068] See also Figure 1 The integrated chip includes a substrate PS of a first conductivity type, a second well region 20 of the first conductivity type implanted on the back of the substrate PS, and a first well region 10 of the second conductivity type implanted on the front of the substrate PS. In a direction perpendicular to the substrate, i.e., in a vertical direction, the first well region 10 and the second well region 20 do not overlap or overlap each other.

[0069] See also Figure 1 The integrated chip includes a plurality of trenches 50 formed on the front surface of the substrate PS, an insulating layer 51 is attached to the inner wall of the trench 50, and the interior of the trench 50 is filled with a conductive material 52. The insulating layer formed on the inner wall (sidewall) of the trench 50 is, for example, oxide, and the insulating layer 51 is usually made of insulating materials such as silicon dioxide, silicon nitride, or silicate glass.

[0070] See also Figure 1In an optional embodiment, the interior of the originally hollow groove 50 formed by etching is first filled with an insulating material and then the insulating material is etched back, leaving only a thin layer of residual insulating material on the inner wall of the groove 50, and the residual insulating material is regarded as a layer of insulating layer 51 attached to the inner wall of the groove. After that, the conductive material 52 is continuously filled into the groove by deposition and the excess material is removed by etching back and only the conductive material 52 in the groove 50 is retained. The deposition method of the conductive material includes chemical vapor deposition and physical vapor deposition. The conductive material 52 can use, for example, doped semiconductor materials or doped single crystal silicon or polycrystalline silicon or even metal materials. Different grooves 50 are spaced apart, but the conductive materials 52 in each of the different grooves can have an equal potential relationship that is electrically connected to each other. Various implementation examples of electrically connecting the conductive materials in different grooves will be introduced below.

[0071] See also Figure 1 In an alternative embodiment, the sidewalls of the originally hollow groove 50 formed by etching are subjected to high temperature oxidation to form a layer of insulation, for example, a thinner layer of silicon oxide is generated on the inner wall of the groove 50, and the generated silicon oxide is regarded as an insulation layer 51 attached to the inner wall of the groove.

[0072] See also Figure 1 In an alternative embodiment, a thin film is deposited on the sidewalls of the originally hollow groove 50 formed by etching to form an insulating layer, for example, a thinner layer of silicon nitride is deposited on the inner wall of the groove 50, and the deposited silicon nitride is regarded as an insulating layer 51 attached to the inner wall of the groove.

[0073] See also Figure 1 In an optional embodiment, a plurality of grooves 50 are arranged in a designated area or a predetermined area or a delimited area of ​​the substrate PS. The designated area is, for example, a relatively central area or a corner area of ​​the substrate PS. According to the conventional wafer preparation process, the substrate is usually square or rectangular, that is, the shape of the substrate PS after the wafer is diced. If the integrated chip is an independent discrete device and is not integrated with other integrated circuits, then in the optional example, the designated area is preferably the central area of ​​the substrate. If the integrated chip is a sub-functional module of a chip and needs to be integrated with other integrated circuits such as a flash memory with a storage transistor array, for example, the storage transistor array and the integrated chip are prepared on a common chip or wafer, then the designated area is preferably a corner area or an edge area of ​​the substrate, because the storage transistor array and its auxiliary circuits that occupy most of the substrate area usually occupy the central area of ​​the substrate, etc.

[0074] See also Figure 1, the integrated chip has multiple grooves 50 opened on the front side of the substrate PS: the depth of the groove 50 is approximately from the front side of the substrate PS downward to close to the back side of the substrate PS, but not reaching the back side of the substrate. As shown in the figure, the depth of the groove 50 is less than the thickness of the substrate PS, and a certain distance is left between the bottom of the groove and the back side of the substrate. The implantation depth of the first well region and the second well region 10, 20 in the substrate PS is much smaller than the opening depth of the groove 50. It should be noted that it is worth emphasizing that the so-called depth and shallowness are only relative relationships. For example, if they are assumed to use nano-scale processes, the depth or shallowness can also be measured on a nano-scale scale. The size or depth ratio shown in the figure is only a rough auxiliary example for explaining this application, and the figure cannot be directly equated with the actual product.

[0075] See also Figure 1 , the integrated chip includes a conductive layer 44 disposed on the back of the substrate PS. The location of the conductive layer 44 is also approximately the aforementioned designated area or predetermined area or demarcated area of ​​the substrate PS. The locations of the conductive layer 44 and the groove 50 are basically the same location of the substrate PS: the central area or the edge area or the corner area. The material of the conductive layer 44 typically includes metal materials such as copper, aluminum, titanium, or semiconductor materials such as polycrystalline silicon and single crystal silicon, such as silicon alloy materials such as silicon titanium or silicon titanium nitrogen, and metal alloy materials such as aluminum copper alloy. An example of the conductive layer 44 is a mixture of semiconductor materials and metal materials: a metal material such as titanium metal is deposited on the back of the substrate and thermal annealing is performed, and the metal material reacts with the surface silicon on the back of the substrate to generate a metal alloy such as titanium silicide, and then the excess alloy is etched back, leaving only the metal alloy material at the illustrated position as the conductive layer 44, and at this time, it is preferred to implant an N-type dopant such as a second conductive type such as a buried region on the back of the substrate to isolate the conductive layer 44. Alternatively, a buried region is first implanted at the surface silicon on the back side of the substrate, and then a metal material such as copper and aluminum is deposited on the back side of the substrate. Similarly, the excess alloy is then etched back, leaving only the metal alloy material at the position shown in the figure as the conductive layer 44. In addition, although not specifically shown in the figure, the conductive layer 44 is actually preferably insulated and isolated from the back side of the substrate PS using an insulating layer, an isolation layer, or a dielectric layer.

[0076] See also Figure 1, each groove 50 overlaps with the conductive layer 44 in the direction perpendicular to the substrate PS: that is, as shown in the figure, each groove 50 and the conductive layer 44 overlap each other in the direction perpendicular to the substrate PS. Note that capacitance exists between the groove and the conductive layer, and the capacitance is formed by the conductive material 52 in the groove 50 and the conductive layer 44. Ways to increase the capacitance value under less precise adjustment include: reducing the distance between the bottom of the groove 50 and the conductive layer 44, or increasing the tiling area of ​​the conductive layer 44, or increasing the number of grooves 50, or increasing the density of the distribution of the grooves 50 in a specified area, or reducing the thickness of a layer of the insulating layer 51 on the inner wall of the groove 50, and so on. Another way to reduce the aforementioned capacitance value is the opposite, increasing the distance between the bottom of the groove 50 and the conductive layer 44, or reducing the tiling area of ​​the conductive layer 44, or reducing the number of grooves 50, or lowering the density of the distribution of the grooves 50 in a specified area, or raising the thickness of a layer of the insulating layer 51 on the inner wall of the groove 50, and so on.

[0077] See also Figure 1 , the integrated chip includes a trench cluster with multiple trenches opened on the front of a first conductive type such as a P-type substrate PS, the inner wall of the trench 50 is lined with an insulating layer 51 and the interior of the trench 50 is filled with a conductive material 52. The integrated chip also includes a first well region 10 of a second conductive type such as an N conductive type implanted on the front of the substrate PS. In addition, the integrated chip also includes a second well region 20 of a first conductive type such as a P conductive type implanted on the back of the substrate PS, and the first well region 10 and the second well region 20 are respectively located on opposite sides of the trench cluster. With regard to the two well regions being respectively on opposite sides of the trench cluster: for example, if the first well region 10 is located on the left side of the trench cluster, the corresponding second well region 20 is located on the opposite right side of the trench cluster; for example, if the first well region 10 is located on the front side of the trench cluster, the corresponding second well region 20 is located on the opposite back side of the trench cluster. For example, if the first well region 10 is located at the north of the trench cluster, the corresponding second well region 20 is located at the relatively south of the trench cluster; for example, if the first well region 10 is located at the west of the trench cluster, the corresponding second well region 20 is located at the relatively east of the trench cluster.

[0078] See also Figure 1 As mentioned above, a trench cluster is deployed in a designated area of ​​the substrate PS. Therefore, it can also be considered that the first well region and the second well region 10 and 20 are respectively located on opposite sides of the designated area, such as the central area of ​​the substrate PS.

[0079] See also Figure 1, with respect to the first well region 10: a first doping region 11 of a second conductivity type such as an N conductivity type and a heavily doped region 12 implanted in the first well region 10; and a third doping region 13 of a first conductivity type such as a P conductivity type and a connecting region 14 implanted in the first well region 10. It is stipulated that the first doping region 11 and the conductive material 52 filled in each trench 50 have the same potential or the same voltage level.

[0080] See also Figure 1 , for the first well region 10: Optionally, the first doping region 11 has a higher doping concentration than the first well region 10 and the heavily doped region 12 has a higher doping concentration than the first doping region 11, and they are both N-doping type. The reason why the heavily doped region is defined as heavily doped is that the heavily doped region 12 has a much higher doping concentration than the first well region 10. For example, the heavily doped region can provide an ohmic contact with extremely low contact resistance for an integrated chip.

[0081] See also Figure 1 , for the first well region 10: Optionally, the first doped region 11 is implanted at a shallower depth than the first well region 10 and the heavily doped region 12 is implanted at a shallower depth than the first well region 10. The third doped region 13 is implanted at a shallower depth than the first well region 10 and the third doped region 13 uses a P doping type, for example, the third doped region 13 is heavily doped. The optional example in the figure shows that the first doped region, the heavily doped region, and the third doped region 11-13 are implanted in the surface layer of the front side of the substrate PS. In addition, a connection region 14 is implanted separately in the first well region 10, for example, the P-type connection region 14 is lightly doped. Figure 1 The alternative example shows that the outline of the connection region 14 of the first well region 10 is set to be spaced apart from the surface layer of the front side of the substrate PS. Figure 2 The alternative example shows that the outline of the connection region 14 of the first well region 10 is set to touch the surface layer of the front side of the substrate PS.

[0082] See also Figure 1 In an optional embodiment, the outline of the junction region 14 in the first well region 10 is set to be separated from the surface layer on the front side of the substrate. When the dopant is injected into the first well region 10 to form the junction region 14, the ion implantation depth of the dopant is adjusted to be implanted below the surface layer on the front side of the substrate PS but not touching the surface layer, and a small portion of the first well region 10 is still retained between the surface layer on the front side of the substrate PS and the junction region 14. The junction region 14 extends from the first doping region 11 to the substrate PS on the side of the first well region 10. The junction region 14 is adjacent to the first doping region 11 and the adjacent substrate PS.

[0083] See also Figure 2In an optional embodiment, the outline of the junction region 14 in the first well region 10 is set to touch the surface layer on the front side of the substrate. When the dopant is injected into the first well region 10 to form the junction region 14, the ion implantation depth of the dopant is adjusted to be implanted into the surface layer on the front side of the substrate PS and touch the surface layer at the same time. At this time, the first well region 10 no longer has any area left between the surface layer on the front side of the substrate PS and the junction region 14. The junction region 14 extends from the first doping region 11 to the substrate PS on the side of the first well region 10. The junction region 14 is adjacent to the first doping region 11 and the adjacent substrate PS.

[0084] See also Figure 1 In an optional embodiment, the junction region 14 is adjacent to the first doped region 11: as shown in the figure, the former directly intersects with the latter during the ion implantation process. The junction region 14 is also adjacent to the substrate PS. In addition, the figure shows the former during ion implantation: the junction region 14 is adjacent to a local area of ​​the substrate PS between a trench in the trench cluster that is closest to the first well region 10 and the first well region 10. For example, the junction region 14 is adjacent to a local area of ​​the substrate PS between a trench in the trench cluster that is closest to or close to the leftmost side of the first well region 10 and the first well region 10. According to the junction region shown in the figure during ion implantation: in other words, the junction region 14 is adjacent to a local area of ​​the substrate PS between a trench in the trench cluster that is closest to or close to the frontmost side of the first well region 10 and the first well region 10. Therefore, the junction region not only intersects with the first doped region, but also intersects with a local area of ​​the substrate. Can be combined Figure 2 .

[0085] See also Figure 1 , for the second well region 20: a second doping region 22 of a second conductivity type, such as an N conductivity type, implanted in the second well region 20; and at the same time, a fourth doping region 24 of a first conductivity type, such as a P conductivity type, implanted in the second well region 20. For example, it can be provided that the second doping region 22 extends from the second well region 20 to the substrate, such as to the substrate region above the second well region 20. The second doping region 22 is adjacent to the substrate PS, for example, it is provided that the second doping region is adjacent to the substrate region above the second well region 20.

[0086] See also Figure 1 , for the second well region 20: Optionally, the fourth doping region 24 has a higher doping concentration than the second well region 20 and the second well region 20 has a higher doping concentration than the substrate PS, both of which are P doping types. The reason why the fourth doping region is defined as heavily doped is that the fourth doping region 24 has a much higher doping concentration than the second well region 20. For example, the use of heavily doped regions can provide an ohmic contact with extremely low contact resistance for an integrated chip.

[0087] See also Figure 1, for the second well region 20: Optionally, the implantation depth of the fourth doping region 24 is shallower than that of the second well region 20 and the implantation depth of the second doping region 22 is deeper than that of the second well region 20. The figure shows that the second doping region 22 and the fourth doping region 24 are implanted in the surface layer on the back side of the substrate PS.

[0088] See also Figure 1 In an optional embodiment, the doped regions on the front side of the substrate PS (such as the first well region, the first doped region, the heavily doped region, the third doped region, the connecting region, etc.) are based on the front side process of the wafer and the doping depth of these doped regions is the depth seen from the front side of the substrate PS, or the depth of ion implantation from the front side.

[0089] See also Figure 1 In an optional embodiment, the doped regions on the back side of the substrate PS (such as the second well region, the second doped region, the fourth doped region and the buried region mentioned later) are based on the back side process of the wafer and the doping depth of these doped regions is the depth seen from the back side of the substrate PS, or the depth of ion implantation from the back side.

[0090] See also Figure 1 In an optional embodiment, the integrated chip includes the conductive layer disposed on the back of the substrate PS and the conductive layer 44 and the second doping region 22 and the fourth doping region 24 have the same potential or the same voltage level or the same potential. As mentioned above, the optional examples of the conductive layer 44 are semiconductor materials or metal materials or a mixture thereof: for example, the metal material is deposited on the back of the substrate PS and the excess material is etched back, and only a portion of the metal material overlapping with the groove cluster at the illustrated position is retained as the conductive layer 44, and the other metal materials that do not overlap with the groove cluster are etched back. As an optional option: first form a thin film layer such as an insulating layer or an isolation layer or a dielectric layer on the back of the substrate PS, then deposit a metal material on the thin film layer on the back of the substrate PS and then etch back the composite layer of the thin film layer and the metal material, and etch back the excess material of the composite layer on the back of the substrate PS, leaving only a portion of the composite layer overlapping with the groove cluster at the illustrated position, at which time the retained metal material in the portion of the composite layer overlapping with the groove cluster plays a conductive role and can be regarded as a conductive layer 44. Note that although the metal material in the composite layer can be conductive, the metal material in the composite layer is insulated from the substrate through the thin film layer, and the other composite layers that do not overlap with the groove cluster are all etched back. Various embodiments of the conductive layer 44 and the second doping region 22 and the fourth doping region 24 having a common potential will be further explained in detail in the following content.

[0091] See also Figure 1As mentioned above, the surge signal S0 applied to the heavily doped region 12 and the third doped region 13 has both high-frequency components such as single-phase pulses and power-related electromagnetic interference of the power system and low-frequency pulsating components caused by hot plugging of multiple hard disk loads. The generation mechanism of the surge signal S0, such as the extremely high ratio of the sudden change value of its voltage to the sudden change value of time, or the extremely high ratio of the sudden change value of its current to the sudden change value of time. In layman's terms, it means that a huge voltage mutation occurs in a short time or transiently, and a huge current mutation occurs in a short time or transiently. The surge current and peak voltage generated by the voltage mutation or current mutation form a surge interference source. The low-frequency component of the surge signal S0 will be decoupled at the capacitor, that is, at the capacitor group between the groove cluster and the conductive layer 44: it can effectively reduce the voltage fluctuation on the protected line in the hard disk, and realize the decoupling between the output power on the protected line being basically constant but the input power being in a jump fluctuation state. The surge signal S0 can be electrically connected to the heavily doped region 12 and the third doped region 13 through a wire, a conductive strip, a metal conductive strip, a probe, a metal spring, or a bonding wire. Each frequency band component in the surge signal is transmitted to the first doped region 11 and to the capacitor between the groove cluster and the conductive layer 44 through the resistance parasitic on the first well region 10 between the heavily doped region 12 and the first doped region 11, and then to the capacitor between the groove cluster and the conductive layer 44, and charges the capacitor between the groove cluster and the conductive layer, so as to form a stored charge at the conductive material 52 in the groove 50. It has been recorded in the previous text that there will be a capacitor between the conductive material 52 of each groove 50 in the groove cluster and the conductive layer 44, and the first doped region has the same potential as the conductive material in each groove, so when the surge signal is transmitted to the first doped region 11, the capacitors between the groove cluster and the conductive layer will be charged.

[0092] See also Figure 1, the low-frequency components such as the pulsating voltage in the surge signal S0 applied to the heavily doped region 12 and the third doped region 13 are mostly transmitted to the aforementioned capacitor through the well resistance between the heavily doped region 12 and the first doped region 11 and charge the capacitor. The smoothing effect of the capacitor can reduce the surge impact on the integrated chip or reduce the surge impact on the protected circuit. The high-frequency components such as the single-phase pulse or the extremely narrow pulse in the surge signal S0 applied to the heavily doped region 12 and the third doped region 13 are mostly transmitted to the node (PN-junction) between the aforementioned first doped region 11 and the junction region 14 through the well resistance between the heavily doped region 12 and the first doped region 11. The node will undergo reverse breakdown under the impact of the surge signal. If the actual voltage applied to the node (PN-junction) by the transient voltage or transient current of the surge signal S0 exceeds the reverse breakdown voltage of the PN junction, the node will be reversely broken down. The opposite situation to the reverse breakdown is that if the actual voltage of the transient voltage or transient current of the surge signal S0 applied to the node (PN-junction) does not exceed the reverse breakdown voltage of the PN junction, the node between the first doped region and the junction region will not experience reverse breakdown.

[0093] See also Figure 1 , under the condition that the node between the first doping region 11 and the connection region 14 is reversely broken down, a bipolar transistor such as the NPN transistor shown in the figure is triggered to be turned on and is located between the first doping region 11, the second doping region 22 and the substrate PS to release the surge signal S0. The current generated when the aforementioned node is reversely broken down will flow to the base of the bipolar transistor NPN and generate a voltage drop at the base to trigger the NPN transistor to turn on. The doping concentration of the substrate is usually lower than that of the well region and the parasitic resistance of the substrate is often much larger than the parasitic resistance of the well region.

[0094] See also Figure 1When the surge signal S0 applied to the heavily doped region 12 and the third doped region 13 causes the node between the first doped region and the junction region to reversely break down, the bipolar transistor between the first doped region 11, the second doped region 22 and the substrate PS is triggered to turn on to release the surge signal S0. If the bipolar transistor NPN between the first and second doped regions 11-22 and the substrate PS enters a triggered turn-on state, the current under the turn-on condition of the bipolar transistor NPN causes another PNP type bipolar transistor between the third doped region 13, the fourth doped region 24 and the first well region 10 to be triggered by the bipolar transistor NPN and turn on. The current under the condition that the bipolar transistor NPN is turned on flows through the aforementioned first well region 10, such as the current of the bipolar transistor NPN flows through the resistance parasitic on the first well region 10 between the heavily doped region 12 and the first doped region 11. During this period, the voltage drop generated on the equivalent resistance of the first well region 10 due to the conduction of the NPN will be applied to the base of the PNP, thereby triggering the PNP bipolar transistor to turn on. Positive feedback is generated between the bipolar transistor pair and each promotes the conduction of the other to generate a larger pressure relief current path, that is, the discharge path.

[0095] See also Figure 1 For example, when the NPN transistor (between the first doping region, the substrate, and the second doping region) is turned on, the collector current laterally penetrates the gap region (or space region) between the plurality of trenches 50 of the substrate PS. At this time, when the bipolar transistor is turned on, the current, such as the collector current, has a lateral path that flows laterally through the gap region between the plurality of trenches 50 of the substrate PS. The current path shown in the figure, i.e., the channel region ch, is an example of a lateral path for the collector current to flow through the gap region between the trenches 50 when the NPN bipolar transistor is turned on.

[0096] See also Figure 1 For example, when the PNP transistor (third doping region, first well region, fourth doping region) is turned on, the collector current laterally penetrates the gap region (or space region) between the plurality of trenches 50 of the substrate PS. At this time, when the bipolar transistor is turned on, the current, such as the collector current, has a lateral path that flows laterally through the gap region between the plurality of trenches 50 of the substrate PS. The current path shown in the figure, i.e., the channel region ch, is an example of a lateral path for the collector current to flow through the gap region between the trenches 50 when the PNP bipolar transistor is turned on.

[0097] See also Figure 1In summary, under the condition that the surge signal S0 causes the node between the first doping region 11 and the connection region 14 to reversely break down, an NPN type bipolar transistor between the first doping region 11, the second doping region 22 and the substrate PS and another PNP bipolar transistor between the third doping region 13, the fourth doping region 24 and the first well region 10 are triggered to conduct, thereby discharging the surge signal S0. The pressure relief effect or current discharge function of the bipolar transistor in the on state on the NPN and PNP can reduce the surge impact on the integrated chip or reduce the surge impact on the protected circuit.

[0098] See also Figure 1 , the conduction state of the bipolar transistor pair NPN and PNP can release surge signals, but at the same time it has a negative impact on the node between the first doped region 11 and the junction region 14, that is, the reverse conducting diode, because the large current during leakage not only flows through the bipolar transistor pair NPN and PNP, but also flows through the reverse conducting diode. It is noted that the reverse current of the reverse conducting diode under the current semiconductor technology conditions has a maximum reverse current extreme value. If the actual value of the reverse current exceeds the reverse current extreme value, the node will be damaged. Of course, if the actual voltage on the node exceeds the maximum withstand voltage of the node, it will also damage the node, such as causing the node to avalanche. Adjusting the doping concentration of the junction region 14 can easily change the critical voltage, that is, the breakdown voltage, when the node is reversely broken down, without affecting the operation of the bipolar transistor. Usually, the well region can be used to reasonably configure the required parasitic resistance value. After configuring the parameters of a pair of bipolar transistors, if you simply want to change the critical voltage of the node reverse breakdown, when trying to change the doping area related to the bipolar transistor to adjust the critical voltage of the node, such as the impurities in the first doping area, this will also change the intrinsic parameters of the bipolar transistor. However, adjusting the doping concentration of the junction area to modify the critical voltage of the node reverse breakdown does not change the parameters of the bipolar transistor. Adjusting the critical voltage of the node is only an optional solution before the product is put on the market. However, the better solution to protect the node from damage and make the node reusable is as described below. The node can be locked at the right time after being used to trigger the transistor pair to turn on.

[0099] See also Figure 1In an optional embodiment, under the condition of reverse breakdown of the node between the first doping region 11 and the connection region 14, the bipolar transistor NPN between the first and second doping regions and the substrate and the bipolar transistor PNP between the third and fourth doping regions and the first well region are triggered to conduct and discharge the surge signal. At this time, the equivalent voltage of the stored charge of the conductive material 52 filled in each groove 50 is used to pinch off the current channel flowing from the node under the reverse breakdown condition or state to the substrate PS. There will be a capacitor between the conductive material 52 of each groove 50 and the conductive layer 44. The surge signal S0 mentioned above will charge this type of capacitor. The characteristic of the capacitor after charging is that the conductive material 52 will be injected with carriers or charges to form its own stored charge. The accumulation of stored charge will generate voltage and the stored charge will also generate a transfer path in the integrated chip synchronously, thereby consuming the charge, so the equivalent voltage of the stored charge is not constant, but dynamically changing.

[0100] See also Figure 1 In an optional embodiment, the bipolar transistor triggers the conduction of the NPN and PNP nodes that are reversely broken down to discharge the surge, and the equivalent voltage of the stored charge of the conductive material 52 pinches off the current channel flowing from the node (PN-junction) in the reverse breakdown state to the substrate: for example, an equivalent voltage is used to reverse bias the PN junction between the junction region 14 and the first doping region 11 and the first well region 10, and an equivalent voltage is used to deplete the junction region 14 by the first doping region 11 and the first well region 10. The reverse bias of the PN junction will form a depletion layer, and based on the formed depletion layer and under the reverse pressure of the equivalent voltage, the junction region 14 will be depleted. This depletion region has a high blocking voltage, so that the integrated chip has an extremely high actual withstand voltage level. If the surge is completely discharged or the voltage level of the surge is too low, the surge is not enough to form a higher equivalent voltage at the capacitor between the conductive material 52 in the groove 50 and the conductive layer 44, then the reverse bias state of the PN junction between the junction region 14 and the first doped region 11 and the first well region 10 will be cancelled, and the depleted junction region 14 will be restored, essentially restoring the characteristic that the node between the first doped region and the junction region can be reversely broken down again, waiting for the next surge.

[0101] See also Figure 1In an optional embodiment, the junction region 14 is known to be spaced apart from the surface layer of the front side of the substrate at the contour of the first well region 10. The equivalent voltage of the stored charge of the conductive material 52 in the groove 50 pinches off the current path of the node in the reverse breakdown state to the substrate: because the junction region 14 does not touch the surface layer of the substrate, and a small portion of the first well region 10 is still retained between the surface layer of the front side of the substrate PS and the junction region 14, the equivalent voltage depletes the junction region 14 in a manner including forming a reverse biased PN junction and a depletion layer with the junction region 14 by a small portion of the first well region between the surface layer of the front side of the substrate and the junction region 14, a small portion of the first well region below the junction region 14, and the first doping region 11, and depleting the junction region 14 based on the formed depletion layer and under the reverse pressure of the equivalent voltage. The first doping region adjacent to the junction region and some small portions of the first well region at different positions are used to deplete the junction region. Figure 1 The example allows the use of Figure 2 Lower equivalent voltage to deplete the junction area, Figure 1 It can be performed based on a small capacitor. It should be noted that the equivalent voltage will only actively deplete the junction area when the node enters the reverse breakdown state and triggers the PNP and NPN transistors to generate the discharge path of the surge signal, because the larger charging current for the capacitor at this stage is sufficient to charge the stored charge of the capacitor to a sufficiently high level and provide a sufficiently large equivalent voltage. Therefore, the equivalent voltage can pinch off the current channel from the node in the reverse breakdown state to the substrate, see Figure 1 shown.

[0102] See also Figure 2 In an optional embodiment, the junction region 14 is known to be configured to touch the surface layer on the front side of the substrate at the contour of the first well region 10. The equivalent voltage of the stored charge of the conductive material 52 in the groove 50 pinches off the current path from the node in the reverse breakdown state to the substrate: because the junction region 14 touches the surface layer of the substrate, and no part of the first well region 10 is left between the surface layer on the front side of the substrate PS and the junction region 14, the equivalent voltage depletes the junction region 14 in a manner that includes forming a so-called PN junction with a reverse bias and forming a depletion layer with the junction region 14 by a small part of the first well region 10 below the junction region, the first doping region 11, etc., and depleting the junction region 14 based on the formed depletion layer and under the reverse pressure of the equivalent voltage. The first doping region and the first well region adjacent to the junction region can deplete the junction region. Figure 2 The example needs to be compared Figure 1 A higher equivalent voltage is used to deplete the junction area. Figure 2 It needs to be executed based on large capacitors. It is worth emphasizing that the relative size relationship between the so-called large capacitors and small capacitors is Figure 1 and Figure 2It should be noted that the equivalent voltage will only actively deplete the junction area when the node enters the reverse breakdown state and triggers the PNP and NPN transistors to generate the discharge path of the surge signal, because the larger charging current to the capacitor at this stage is sufficient to charge the stored charge of the capacitor to a sufficiently high level and provide a sufficiently large equivalent voltage. Therefore, the equivalent voltage can cut off the current channel from the node in the reverse breakdown state to the substrate, see Figure 2 shown.

[0103] See also Figure 1 In summary, compared with the traditional solution to surge, the first advantage is that the silicon-based structure of the integrated chip can not only withstand low voltage but also extremely high voltage. Based on the current channel latch, the integrated chip can easily cope with the extremely high voltage level applied without being burned by the large current. The resulting discharge path can easily cope with nanosecond or millisecond surges. The capacitor between the groove cluster and the conductive layer can smooth the low-frequency pulsating voltage components mixed by the high-frequency surge. That is, the negative signals of each frequency band of the surge can be effectively resisted by the integrated chip. The high-frequency surge is often a high-energy component of a single-phase pulse type such as an arc or lightning, and the low-frequency surge is often a pulsating voltage and current component caused by frequent heating and plugging of multiple hard disks or the start and stop of servers.

[0104] See also Figure 1 In summary, compared with the traditional solution to surge, the second advantage is that the node that triggers the integrated chip to conduct and forms the reverse breakdown of the discharge path is only broken down and drained during the triggering stage. This drainage is based on guiding the bipolar transistors to trigger the PNP and NPN to conduct, but the node itself does not serve as a discharge path after completing the drainage task and does not need to bear large currents. After the drainage is triggered, the current channel of the node is cut off, ensuring that the relevant components of the node itself will not be damaged by the surge. The node exit mechanism can cope with recurring and unpredictable ubiquitous surge signals in this mode. Imagine that if the node and its related components are completely destroyed or partially damaged by a single extremely powerful surge, then other subsequent surges will no longer be able to continue to trigger the discharge function of the integrated chip, and the circuits protected by the integrated chip will lose protection.

[0105] See also Figure 1As mentioned above, compared with the traditional solution to surge, the third advantage is that the intermediate current mismatch problem of the bipolar transistor pair PNP and NPN can be solved during the surge discharge stage. The integrated chip suppresses surges based on the mode of using large discharge current, and a pair of bipolar transistors are used for discharge during the conduction stage. It is easy to understand that the bipolar transistor pair is combined into a dual current discharge path, which has the advantage of being able to offset the high power of the surge more quickly, but there is also a current mismatch problem between the bipolar transistor pairs. Unlike the node damage caused by high-power surge impact, the current mismatch problem is that the current difference between the two bipolar transistors is too large, and the difference current between the two bipolar transistors is forced to be transferred to the diode of the node connected in series and parallel with the bipolar transistor, so that the excess overcurrent phenomenon damages the node. The equivalent voltage pinches off the current channel from the node in the reverse breakdown state to the substrate, which can suppress the node from receiving high difference current.

[0106] See also Figure 2 The integrated chip also includes a top dielectric layer 30 covering the front side of the substrate and a bottom dielectric layer 40 covering the back side of the substrate. The above-mentioned surge signal S0 is electrically connected to the heavily doped region 12 and the third doped region 13 through a wire, a conductive strip, a metal conductive strip, a probe, a metal spring, or a bonding wire. Here, an alternative top electrode layer 31 for receiving the surge signal S0 is covered on the top dielectric layer 30, and the top electrode layer 31 passes through a via provided in the top dielectric layer 30 to contact the heavily doped region 12 and the third doped region 13 respectively. The example in the figure is that a via is formed in the top dielectric layer 30 at a position aligned with the heavily doped region 12 and the third doped region 13, and the via is defined as a common or shared via, so when part of the electrode material of the top electrode layer 31 is filled in the common or shared via, it will ohmically contact the heavily doped region 12 and the third doped region 13. In other examples, it is necessary to separately form a sub-through hole in the top dielectric layer 30 that can be aligned with the heavily doped region 12, and another sub-through hole in the top dielectric layer 30 that is aligned with the third doped region 13. Then, when part of the electrode material of the top electrode layer 31 is filled in these two sub-through holes, they will separately ohmically contact the heavily doped region 12 and the third doped region 13.

[0107] See also Figure 2In an optional embodiment, the top dielectric layer 30 is prepared, for example, by depositing a thin insulating dielectric layer on the front side of the substrate PS. The insulating dielectric layer is then patterned and etched, and the small partition of the insulating dielectric layer on the front side of the substrate PS that overlaps with the heavily doped region 12 and the third doped region 13 needs to be etched and removed. The heavily doped region 12 and the third doped region 13 can be exposed at the small partition by preparing the insulating dielectric layer and etching. A through hole that aligns with and exposes the heavily doped region 12 and the third doped region 13 is formed on the insulating dielectric layer at the position where the small partition is removed. When the top electrode layer 31 is subsequently prepared, part of the electrode material of the top electrode layer 31 is filled in these through holes. The front insulating dielectric layer can use insulating films such as silicon oxide, silicon nitride, borophosphosilicate glass, and non-doped silicate glass. The top electrode layer can use metal materials such as copper or aluminum, or copper-aluminum alloys. The top electrode layer can also first deposit a titanium liner layer and then cover other metal materials on titanium. The material selection of the top electrode layer is diverse.

[0108] See also Figure 2 , the reference ground such as GND can be electrically connected to the second doping region 22 and the fourth doping region 24 through a wire, a conductive strip, a metal conductive strip, a probe, a metal spring, or a bonding wire. Here, the bottom electrode layer 41 alternatively used to connect to the reference ground such as GND covers the bottom dielectric layer 40, and the bottom electrode layer 41 passes through a via provided in the bottom dielectric layer 40 to contact the second doping region 22 and the fourth doping region 24 respectively. The example in the figure is that a via is formed in the bottom dielectric layer 40 at a position aligned with the second doping region 22 and the fourth doping region 24, and this via is defined as a common or shared via, so when part of the electrode material of the bottom electrode layer 41 is filled in the common or shared via, it will ohmically contact the second doping region 22 and the fourth doping region 24. In other examples, it is necessary to form a sub-through hole aligned with the second doping region 22 in the bottom dielectric layer 40 and another sub-through hole aligned with the fourth doping region 24 in the bottom dielectric layer 40. Then, when part of the electrode material of the bottom electrode layer 41 is filled in these two sub-through holes, it will ohmically contact the second doping region 22 and the fourth doping region 24 respectively. In other examples, it is necessary to form a sub-through hole aligned with the so-called conductive layer 44 in the bottom dielectric layer 40. When part of the electrode material of the bottom electrode layer 41 is filled in this sub-through hole, it will ohmically contact the so-called conductive layer 44 at the same time. According to the context, a bottom electrode layer 41 for connecting to the reference ground covers the bottom dielectric layer 40, and the bottom electrode layer 41 passes through a plurality of through holes provided in the bottom dielectric layer to contact the second doping region 22, the fourth doping region 44 and the conductive layer 44 respectively. The reference ground can also be electrically connected to the conductive layer 44 through a wire or a conductive strip or a metal conductive strip or a probe or a metal spring or a bonding wire. No matter which of the above embodiments is used, the conductive layer 44 and the second doping region 22 and the fourth doping region 24 can share a common electrical potential.

[0109] See also Figure 2 In an optional embodiment, the bottom dielectric layer 40 is prepared, for example, by depositing a thin insulating dielectric layer on the back of the substrate PS. The insulating dielectric layer is then patterned and etched, and the small partition of the insulating dielectric layer on the back of the substrate PS that overlaps with the second doping region 22 and the fourth doping region 24 needs to be etched and removed. The second doping region 22 and the fourth doping region 24 can be exposed at the small partition by preparing the insulating dielectric layer and etching. A through hole that aligns with and exposes the second doping region 22 and the fourth doping region 24 is formed on the insulating dielectric layer due to the removal of the small partition. When the bottom electrode layer 41 is subsequently prepared, part of the electrode material of the bottom electrode layer 41 is filled in these through holes. The back insulating dielectric layer can use insulating films such as silicon oxide, silicon nitride, borophosphosilicate glass, and non-doped silicate glass. The bottom electrode layer can use metal materials such as copper or aluminum, or copper-aluminum alloys. The bottom electrode layer can also first deposit a titanium liner layer and then cover other metal materials on titanium. The material selection of the bottom electrode layer is diverse.

[0110] See also Figure 2 , NPN is recorded as the first bipolar transistor, and PNP is recorded as the second bipolar transistor. The chip includes an interconnection electrode layer 32 covering the top dielectric layer 30, and the interconnection electrode layer 32 passes through the through hole provided in the top dielectric layer 30 and contacts the first doped region 11 and the conductive material 52 in the groove 50 respectively, so that the first doped region 11 and the conductive material 52 in each groove are electrically connected by the interconnection electrode layer 32 and have the same potential.

[0111] See also Figure 2 , a sub-through hole aligned with the first doped region 11 is formed in the top dielectric layer 30, and a plurality of sub-through holes are also formed in the top dielectric layer 30: each sub-through hole is aligned with the conductive material 52 of a groove 50, so when part of the electrode material of the top electrode layer 31 is filled in these plurality of sub-through holes, the top electrode layer 31 will separately ohmically contact the first doped region 11 and ohmically contact the conductive material 52 in each groove 50. A conductive wire, a conductive strip, a metal conductive strip, a probe, a metal spring, or a bonding wire can also be used to electrically connect the conductive material 52 and the first doped region 11.

[0112] See also Figure 2If the interconnection electrode layer 32 and the top electrode layer 31 use the same conductive material, their preparation method is, for example, to generate a thin metal cover layer on the top dielectric layer 30 by deposition, and then the metal cover layer is patterned and etched to retain the two reserved parts on the top dielectric layer 30, the first reserved part of the metal cover layer is regarded as the interconnection electrode layer 32, and the second reserved part of the metal cover layer is regarded as the top electrode layer 31. It is worth noting that the interconnection electrode layer 32 and the top electrode layer 31 are separated and not directly electrically connected.

[0113] See also Figure 2 In an optional embodiment, the advantage of the interconnect electrode layer 32 being exposed outside the top dielectric layer 30 is that the capacitor can be regarded as a normalized power supply: low-frequency pulsation in surge signals is always present, so the charge of the conductive material 52 inside each groove will continue to exist. The capacitor is regarded as the external power supply of the integrated chip, and can replace the onboard battery in low power demand situations, such as replacing the button battery used in the motherboard. The onboard power supply can provide continuous power to the storage server to maintain the storage of some important information, such as BIOS settings, date and time, etc. In this way, this information will not be lost when the computer is restarted, which can ensure the normal operation of the system.

[0114] See also Figure 2 , the onboard power supply can power the CMOS memory. The CMOS memory is where the computer's basic input and output system (BIOS) settings are stored, including hardware configuration, boot sequence, etc. The power supply from the onboard power supply ensures the persistence of these settings, even when the power is off or the computer is turned off. This is critical to the stability and reliability of the computer. As shown in the figure, power is taken from the interconnect electrode layer 32.

[0115] See also Figure 2 , the onboard power supply can power the real-time clock function. The onboard power supply also provides power to the real-time clock on the server or computer motherboard. The presence of an onboard power supply ensures that the computer can keep accurate time records even in the event of a power outage, which is very important for operations such as time stamping files, logging, etc.

[0116] See also Figure 2 , the onboard power supply can provide power for BIOS update and recovery. The onboard power supply on the server or computer motherboard can also be used to update and recover the BIOS firmware. When updating the BIOS, the onboard power supply can also provide stable power to ensure a smooth update process.

[0117] See also Figure 3In an optional embodiment, the integrated chip includes one or more channels 57 opened on the front side of the substrate PS and spanning each trench 50 and extending to the first doping region 11. In the embodiment shown in the figure, the channel 57 is much shallower than the opening depth of the trench 50. The preparation time of the channel 57 can be after the trench 50 completes the filling process of the conductive material. The inner wall of each channel 57 is lined with an isolation layer 57b and the interior of each channel 57 is filled with a conductor material 57a. The isolation layer 57b makes the conductor material 57a insulated and isolated.

[0118] See also Figure 3 The integrated chip includes a plurality of grooves 57 opened on the front surface of the substrate PS, the inner wall of the groove 57 is attached with an isolation layer 57b and the groove 57 is filled with a conductive material 57a. The isolation layer formed on the inner wall (sidewall) of the groove 57 is, for example, oxide, and the isolation layer 57b is usually made of insulating materials such as silicon dioxide, silicon nitride or silicate glass.

[0119] See also Figure 3 In an optional embodiment, the interior of the originally hollow slot body 57 formed by etching is first filled with an insulating material and then the insulating material is etched back, leaving only a thin layer of residual insulating material on the inner wall of the slot body 57, and the residual insulating material is regarded as a layer of isolation layer 57b attached to the inner wall of the slot body. After that, the conductor material 57a is continuously filled into the slot body by deposition and the excess material is removed by etching back and only the conductor material 57a in the slot body 57 is retained. The deposition method of the conductor material includes chemical vapor deposition and physical vapor deposition. The conductor material 57a can be, for example, doped semiconductor material or doped single crystal silicon or polycrystalline silicon or even metal material. Different slot bodies 57 are spaced apart, but the conductor materials 57a in each of the different slot bodies can have an equal potential relationship that is electrically connected to each other.

[0120] See also Figure 3 In an optional embodiment, the main purpose of the groove 50 relative to the groove body 57 is to produce dense capacitor devices, so the groove 50 has a wider width than the groove body 57, and the groove body 57 is narrower. In addition, the conductor material 57a is required to produce a low-resistance electrical connection relative to the conductive material 52. In contrast, the conductive material 52 is used for storing charges and charging and discharging. The conductive material 57a is more likely to use a metal material, while the conductive material 52 is more likely to use a doped semiconductor material such as doped single crystal silicon or polycrystalline silicon.

[0121] See also Figure 3In an alternative embodiment, the side walls of the originally hollow groove body 57 formed by etching are subjected to high-temperature oxidation to form a layer of insulation, such as generating a thinner layer of silicon oxide on the inner wall of the groove body 57, and the generated silicon oxide is regarded as an isolation layer 57b attached to the inner wall of the groove body 57.

[0122] See also Figure 3 In an alternative embodiment, a thin film is deposited on the sidewalls of the originally hollow groove body 57 formed by etching to form an insulating layer, such as depositing a thinner layer of silicon nitride on the inner wall of the groove body 57, and the deposited silicon nitride is regarded as an isolation layer 57b attached to the inner wall of the groove body 57.

[0123] See also Figure 3 In an optional embodiment, combined with the schematic diagram of cross-section BB taken from the intersection of the slot body 57 and the groove 50 as shown in the figure, the slot body 57 has a contact hole at the intersection with the groove 50, for example, the contact hole is located at the bottom (or side) of the slot body 57, and the cross-section BB shows that the conductor material 57a in the slot body 57 is in contact or electrically connected to the conductive material 52 inside the groove 50 at the contact hole at the bottom of the slot body, for example, it is an ohmic contact.

[0124] See also Figure 3 In an optional embodiment, in combination with the schematic diagram of the cross section AA taken from the position where the groove body 57 intersects or contacts the first doped region 11, a contact hole is opened at the position where the groove body 57 intersects or contacts the first doped region 11, for example, the contact hole is located at the bottom (or side) of the groove body 57, and the cross section AA shows the contact hole of the groove body 57 that goes down to the first doped region 11, such as the conductor material 57a in the groove body 57 is in contact or electrically connected to the first doped region 11 at the contact hole at the bottom of the groove body, such as ohmic contact. The first doped region 11 and the conductive material 52 in each groove have the same potential, and the conductive material 57a connects the first doped region 11 and the conductive material 52, so they have the same potential. This example does not require Figure 2 The interconnect electrode layer 32 is shown.

[0125] See also Figure 4 In an optional embodiment, in combination with Figure 3 The groove body 57 has a contact hole at the intersection position where it intersects with the groove 50, and the groove body 57 has a contact hole at the part where it intersects or contacts with the first doped region 11, as shown in the figure, so that the conductor material 57a in each groove body 57 is electrically connected to the conductive material 52 in the groove 50 and the first doped region 11. The integrated chip also includes a top dielectric layer 30 covering the front side of the substrate PS. The groove bodies 57 opened on the front side of the substrate, crossing each groove 50 and extending to the first doped region 11, are all covered by the top dielectric layer 30 and are not exposed from the top dielectric layer 30. See Figure 3 , the groove body 57 and the conductive material 57a will be completely covered by the top dielectric layer 30 disposed on the front side of the substrate. Figure 4 The groove body 57 and the conductive material 57a are completely covered by the top dielectric layer 30 disposed on the front side of the substrate.

[0126] See also Figure 4 , in an optional embodiment, Figure 4 The capacitance and Figure 2 different, Figure 2 The capacitor is regarded as a normalized power supply and the interconnect electrode layer 32 can be used as a power supply port of the power supply. Figure 4 Since the capacitor device lacks a power supply port similar to that provided by the interconnect electrode layer 32, the capacitor cannot be used as an external power supply.

[0127] See also Figure 5 In an optional embodiment, the integrated chip also includes one or more buried regions 59 implanted on the back side of the substrate PS and between the bottom of the groove 50 and the conductive layer 44. The buried region 59 is preferably of the second conductivity type, such as N-doped type. The buried region 59 and the surrounding substrate PS region will produce junction capacitance. The conductive layer 44 is then allowed to have electrical contact with the buried region 59, for example, they produce ohmic contact. Even if the conductive layer 44 uses an insulating layer, an isolation layer, or a dielectric layer to insulate and isolate the back side of the substrate PS, the buried region 59 may be of the second conductivity type, such as N-doped type, but the buried region 59 is also allowed to be of the first conductivity type, such as P-doped type. The junction capacitance between the buried region and the substrate is a variable capacitance. Figure 5 In the example of FIG. 5 , the buried region 59 is designed to directly contact the conductive layer 44 and in other subsequent examples, such as Figure 6 In the example of , the buried region 59 is designed to be spaced apart from the conductive layer 44. Therefore, it is possible to choose to use the buried region or not to use the buried region. If the buried region is used to influence the capacitance value, the buried region is spaced apart from the conductive layer or in contact with the conductive layer; or, a portion of the buried region is spaced apart from the conductive layer and the remaining portion of the buried region is in direct contact with the conductive layer. The contact mentioned here includes ohmic contact, etc.

[0128] See also Figure 5 In an optional embodiment, in combination with Figure 1, a channel region ch for the current of a pair of bipolar transistors NPN and PNP to flow is reserved at a position between the plurality of trenches 50 of the substrate PS. As shown in the figure, these channel regions ch guide the current flowing through the pair of bipolar transistors NPN and PNP from one side of the trench cluster through the trench cluster and flow laterally to the other side of the trench cluster. For example, the current flowing through the pair of bipolar transistors is guided from the left side of the trench cluster through the channel region ch through the trench cluster and flows laterally to the right side of the trench cluster. For another example, the current flowing through the pair of bipolar transistors is guided from the front side of the trench cluster through the channel region ch through the trench cluster and flows laterally to the back side of the trench cluster. The so-called lateral current path is relative to the longitudinal current path. The lateral direction of the current path is, for example, along the plane direction of the substrate or silicon wafer (i.e., wafer or chip), and the longitudinal direction of the current path is, for example, along the direction perpendicular to the plane of the substrate or silicon wafer. In this article, the lateral direction can be defined as the plane direction of the substrate and the longitudinal direction can be defined as the direction perpendicular to the substrate. It can be seen that the layout of the groove cluster affects the direction of the current path.

[0129] See also Figure 5 In an optional embodiment, in combination with Figure 1 , such as the channel region ch guiding the current flowing through a pair of bipolar transistors from one side of the trench cluster through the trench cluster and laterally flowing to the other side of the trench cluster. The current path shown in the figure, such as the channel region ch, allows the collector current of the NPN bipolar transistor to flow through the gap position between the trenches 50 when it is turned on, and the so-called gap position or gap area can be regarded as the channel region ch where the collector current flows. The current path shown in the figure, i.e., the channel region ch, allows the collector current of the PNP bipolar transistor to flow through the gap position between the trenches 50 when it is turned on, and the so-called gap position or gap area can be regarded as the channel region ch where the collector current flows.

[0130] See also Figure 1 , the current path of the local area between a trench 50 located in the trench cluster closest to the first well region 10 and the so-called first well region 10 of the substrate PS is cut off by the equivalent voltage. For example, at this time, the contour of the connection region 14 in the so-called first well region 10 (i.e., the ion implantation contour or the doping contour) is set to be separated from the surface of the front side of the substrate PS or the surface layer of the front side of the substrate. As mentioned above, the connection region 14 is depleted by the equivalent voltage, so that the current path of the local area between the trench located in the trench cluster closest to the first well region and the first well region is cut off. The trench 50 closest to the first well region is the outermost trench in the trench cluster close to the first well region 10. This is one of the embodiments of using the equivalent voltage of the stored charge of the conductive material in each trench to pinch off the current path flowing from the node in the reverse breakdown state to the substrate. In this example, the channel region ch between the trenches 50 cannot be locked.

[0131] See also Figure 2 , the current channel of the local area between a trench 50 located in the trench cluster closest to the first well region 10 and the so-called first well region 10 of the substrate PS is cut off by the equivalent voltage. For example, at this time, the profile of the connection region 14 in the so-called first well region 10 (i.e., the ion implantation profile or the doping profile) is set to touch the surface of the front side of the substrate PS or touch the surface layer of the front side of the substrate. As mentioned above, the connection region 14 is depleted by the equivalent voltage, so that the current channel of the local area between the trench located in the trench cluster closest to the first well region and the first well region is cut off. The trench 50 closest to the first well region is the outermost trench in the trench cluster close to the first well region 10. This is the second embodiment of using the equivalent voltage of the stored charge of the conductive material in each trench to pinch off the current channel flowing from the node in the reverse breakdown state to the substrate. This example cannot lock the channel region ch between the trenches 50.

[0132] See also Figure 2 In an optional embodiment, regarding the use of an equivalent voltage of stored charges in the conductive material in each groove to pinch off the node under reverse breakdown: when the equivalent voltage is applied to the junction region 14, the reverse bias voltage rev_c1 represents the use of an equivalent voltage to reverse bias the PN junction between the junction region 14 and the first doping region 11 and the first well region 10, and the use of an equivalent voltage to deplete the junction region 14 by the first doping region 11 and the first well region 10. The reverse bias voltage rev_c1, for example, represents the voltage value of the capacitor so that the PN junction associated with the junction region 14 is reverse biased under a non-high-frequency surge signal, a depletion layer is formed, and the junction region 14 is depleted under reverse pressure based on the formed depletion layer. At this time, there is almost no current or only a very small and negligible reverse saturation current flows through the PN junction and the current channel.

[0133] See also Figure 1 In an optional embodiment, the equivalent voltage of the stored charge of the conductive material in each groove is used to pinch off the current channel from the node in the reverse breakdown state to the substrate. The node is reversely broken down only in the triggering stage of a pair of bipolar transistors to implement current diversion. The diversion is based on guiding a pair of bipolar transistors to be triggered and turned on, but after completing the diversion task, the current channel of the node itself is pinched off. Figure 2 . To ensure that the node itself is not damaged.

[0134] See also Figure 1In an optional embodiment, the equivalent voltage of the stored charge of the conductive material in each groove is used to pinch off the current path from the node in the reverse breakdown state to the substrate, thereby preventing the current difference between a pair of bipolar transistors, i.e., the differential current, from being transferred to the diode at the node, and preventing the differential current caused by the current mismatch between the pair of bipolar transistors from flowing to the diode at the node and damaging the diode at the node. As mentioned above, the current mismatch problem is that the current difference between a pair of bipolar transistors is too large, and the differential current between the two bipolar transistors is forced to be transferred to the diode at the node connected in series and parallel with the bipolar transistor. Combined with Figure 2 This can prevent excessive overcurrent, i.e., the difference current from damaging the node. It also protects the node itself from being damaged.

[0135] See also Figure 5 , the current channel in the local area of ​​the substrate PS between a trench in the trench cluster closest to the first well region 10 (for example, the outermost trench 50 close to the first well region 10 in the trench cluster) and the first well region 10 is cut off by the equivalent voltage. Figure 5 Pinch-off and Figures 1 to 4 The pinch-off is slightly different. Although the junction area is still allowed to be depleted and pinch off the current channel flowing from the node to the substrate in the reverse breakdown state, the biggest difference at this time is that the local area is alternately implanted with the first type of shielding area of ​​the first conductivity type, such as the p-region, and the second type of shielding area of ​​the second conductivity type, such as the n-region. The p-region and the n-region are arranged alternately, and multiple p-regions and multiple n-regions are represented by the alternating region ALS in this local area as shown in the figure. The alternating region ALS characterizes that the local area of ​​the substrate PS located between the trench closest to the first well region in the trench cluster and the first well region is implanted with P dopants and N dopants in turn. It can be considered that an n-region is inserted between any two adjacent p-regions, and a p-region is inserted between any two adjacent n-regions, that is, the first type of shielding area (p-region) and the second type of shielding area (n-region) are implanted alternately in the local area. As an option, the first type of shielding area and the second type of shielding area reach upward to the surface layer on the front side of the substrate PS at the local area.

[0136] See also Figure 5 Optionally, both the first type of shielding region (p region) and the second type of shielding region (n region) extend from a position deeper than the connection region 14 in the local area upward to the surface or surface layer of the front side of the substrate PS.

[0137] See also Figure 5 Optionally, both the first type of shielding region (p region) and the second type of shielding region (n region) extend from a position shallower than the connection region 14 in the local area upward to the surface or surface layer of the front side of the substrate PS.

[0138] See also Figure 5Optionally, both the first type of shielding region (p region) and the second type of shielding region (n region) extend from a position deeper than the first well region 10 in the local area upward to the surface or surface layer of the front side of the substrate PS.

[0139] See also Figure 5 Optionally, both the first type of shielding region (p region) and the second type of shielding region (n region) extend from a position shallower than the first well region 10 in the local area upward to the surface or surface layer of the front side of the substrate PS.

[0140] See also Figure 5 , optionally, the junction region 14 contacts the first type shielding region (p region) or does not contact the first type shielding region (p region) in a local area. The first well region 10 may contact the second type shielding region (n region) or does not contact the second type shielding region (n region) in a local area. Note that the junction region 14 is of P conductivity type and the first well region 10 is of N conductivity type.

[0141] See also Figure 5 , as previously recorded, Figure 5 Pinch-off and Figures 1 to 4 The pinch-off is slightly different. Although the junction area is still allowed to be depleted and pinch off the current channel from the node to the substrate in the reverse breakdown state, the biggest difference at this time is that the depletion conditions generated in the local p-region and n-region will further or strengthen the pinch-off of the current channel from the node to the substrate in the reverse breakdown state. The equivalent voltage of the stored charge of the conductive material in each groove 50 reverse biases the PN junction between the first type of shielding area such as the p-region and the second type of shielding area such as the n-region, and uses an equivalent voltage to deplete the first type of shielding area such as the p-region and the second type of shielding area such as the n-region from each other. The reverse bias of the PN junction will form a depletion layer and deplete the p-region and n-region based on the formed depletion layer under the reverse pressure of the equivalent voltage. This depletion region has a higher blocking voltage, so that the integrated chip has a higher actual withstand voltage level. Compared with the case where only the junction area is depleted, the local area depletion undoubtedly has a higher voltage resistance level, and the main reason is that the current channel from the node to the substrate is locked to a higher degree, for example, the depletion of the alternating area ALS will also lock the current. Based on the above content, it can be known that because the current channel of the reverse breakdown PN junction is locked, the reverse breakdown state of the PN junction is ended, and the diode at the node is prevented from being damaged, for example, the difference current of the current mismatch of the transistor pair is prevented from flowing to the PN junction.

[0142] See also Figure 5It is worth noting that if the surge is completely discharged or the voltage level of the surge is too low, the surge is not enough to form a higher equivalent voltage at the capacitor between the conductive material 52 in the groove 50 and the conductive layer 44. Then, the reverse bias of the PN junction between the connection area 14 and the first doping area 11 and the first well area 10 will be cancelled, and the reverse bias of the PN junction between the first type of shielding area such as the p area and the second type of shielding area such as the n area will also be cancelled, which means that the depleted connection area 14 and the p area and the n area are restored, which essentially restores the characteristic that the node between the first doping area and the connection area can be reversely broken down again, waiting for the next surge.

[0143] See also Figure 6 In an optional embodiment, the capacitor between the conductive material 52 in the groove 50 and the conductive layer 44 is charged by the forward current for_c2 as shown in the figure, and the source of the forward current for_c2 is relatively diverse. For example, before the bipolar transistor pair is triggered to turn on, the low-frequency pulsating voltage of the surge signal will charge the capacitor, and even after the bipolar transistor pair is triggered to turn on, the low-frequency pulsating voltage of the surge will still charge the capacitor. It should be noted that after the bipolar transistor pair is triggered to turn on, the discharge current, that is, the current flowing through the bipolar transistor pair, will also charge the aforementioned capacitor at the same time. This is beneficial to promote depletion and pinch off the current channel flowing from the node to the substrate.

[0144] See also Figure 6 In an optional embodiment, the local area is alternately implanted with a first type of shielding area of ​​the first conductivity type and a second type of shielding area of ​​the second conductivity type. Before the first type of shielding area, such as the p-area, and the second type of shielding area, such as the n-area, are mutually depleted, the first type of shielding area, such as the p-area, allows the current flowing from the node in the reverse breakdown state to the substrate PS to pass through the local area, and the first type of shielding area, such as the p-area, is now regarded as a part of the current channel for the current flowing from the node in the reverse breakdown to the substrate PS. The forward current for_c1 flows from the current channel of the first type of shielding area, such as the p-area, to the substrate PS or flows through the channel area ch. If the first type of shielding area, such as the p-area, is depleted, it is considered that the current channel of the local area of ​​the substrate between a trench 50 closest to the first well area 10 in the trench cluster and the first well area 10 (i.e., the first type of shielding area, such as the p-area) is cut off by the equivalent voltage, resulting in a current shielding effect, and another effect is that the reserved channel area ch between multiple trenches 50 is cut off synchronously.

[0145] See also Figure 7In an optional embodiment, according to the foregoing, the alternating region ALS is alternately implanted with a first type of shielding region of the first conductivity type, such as a p region, and a second type of shielding region of the second conductivity type, such as an n region, and an equivalent voltage is applied to the first type of shielding region (p region) and the second type of shielding region (n region) in the local area, and the reverse bias voltage rev_c1 represents that the first type of shielding region, such as the p region, and the second type of shielding region, such as the n region, are mutually depleted by the equivalent voltage. The heavily doped region 12 is also called a contact region, a contact doping region, or a heavily doped contact region.

[0146] See also Figure 7 In an optional embodiment, in combination with Figure 6 , a channel region ch for the current of a pair of bipolar transistors NPN and PNP to flow is reserved at the position where the substrate PS is located between the plurality of trenches 50. Based on the condition that the current channel is cut off by the equivalent voltage, such as the depletion of the junction region 14 and the depletion of the p region and the n region, the first type of shielding region and the second type of shielding region (p region and n region) are mutually depleted under the action of the equivalent voltage to lock the aforementioned channel region ch between the plurality of trenches 50, so that the actual channel for the current flow of the pair of bipolar transistors NPN and PNP (or the channel for the current flow) moves from the initial channel region ch down to the substrate region at the bottom of the trench 50. This is because the equivalent voltage depletes the first type of shielding region, such as the p region, and the current channel (i.e., the p region) of the local region between the trench closest to the first well region 10 in the trench cluster and the first well region 10 of the substrate PS is cut off by the equivalent voltage, and the reserved channel region ch between the trenches is further cut off by the depleted p region.

[0147] See also Figure 7 In an optional embodiment, in combination with Figure 6 , based on the condition that the current channel is cut off by the equivalent voltage, the first and second types of shielding regions (p region and n region) are depleted under the action of the equivalent voltage, which is sufficient to lock the channel region ch between the multiple trenches 50, so that the actual channel for the current flow of a pair of bipolar transistors NPN and PNP moves from the initial channel region ch down to the substrate region at the bottom of the trench 50. It is used to increase the lateral resistance of the base of a bipolar transistor NPN between the first doping region and the second doping region and the substrate, thereby expanding the discharge current of the bipolar transistor NPN between the first doping region and the second doping region and the substrate, and further expanding the discharge current of another bipolar transistor PNP between the third doping region and the fourth doping region and the first well region. The reason is that the actual channel for the transistor current to flow moves from the initial channel region ch down to the substrate region at the bottom of the trench 50, which will dramatically increase the actual resistance of the transistor current flow: for example, the original based on the Figure 6The multi-forked channel region ch has more paths or shorter paths, so that the current can easily pass through the trench cluster from one side of the trench cluster and flow laterally to the other side of the trench cluster. However, once the multi-forked channel region ch in the figure is locked or shielded, the actual channel for the current flow of the bipolar transistor has to move down from the original channel region to the substrate region at the bottom of the trench. This means that the lateral resistance of the base of the bipolar transistor NPN is significantly increased, and the base voltage drop of the bipolar transistor NPN will be increased accordingly, and the current of NPN will increase sharply. The sharp increase in the current of NPN will in turn increase the voltage drop between the emitter and base of PNP, and cause the current of PNP to increase sharply. This is equivalent to increasing the discharge current of the bipolar transistors NPN and PNP, and discharging the surge signal faster and faster. The discharge current refers to the current flowing through the bipolar transistor NPN or PNP to discharge the surge signal S0. It should be noted that once the multi-forked channel region ch in the figure is locked or shielded, the forward current for_c1 no longer exists.

[0148] See also Figure 7 In an optional embodiment, in combination with Figure 6 As mentioned above, the equivalent voltage of the stored charge of the conductive material in each trench is used to cut off the current channel from the node in the reverse breakdown state to the substrate, thereby preventing the current difference between the pair of bipolar transistors, i.e., the differential current, from being transferred to the diode at the node, and preventing the differential current caused by the current mismatch between the pair of bipolar transistors from flowing to the diode at the node and damaging the diode at the node. One of the situations in which a pair of bipolar transistors produce the current mismatch between them: the actual channel for the current flow of the pair of bipolar transistors moves down from the initial channel region ch to the substrate region at the bottom of the trench, then the current of the first bipolar transistor, i.e., NPN, will increase transiently first, and the current of the second bipolar transistor, i.e., PNP, will increase relatively later, thereby causing the first bipolar transistor and the second bipolar transistor (NPN and PNP) to produce current mismatch.

[0149] See also Figure 7 In an optional embodiment, in combination with Figure 6If the doping profile of the first well region 10 is small, such as the doped well region occupies a small volume, the charge of the groove 50 can largely cut off the current channel of the node diode. However, the first well region occupies a small volume, and it is usually impossible to establish a good discharge path for the bipolar transistor. The surge signal S0 cannot be discharged smoothly and quickly, so this is a contradiction. Conversely, if the doping profile of the first well region 10 is large, such as the doped well region occupies a large volume, although the surge signal S0 can be discharged more efficiently and quickly, the current channel of the node diode is difficult to be cut off by the stored charge of the groove 50. The excessive current of the diode at the node will damage it. Since the diode at the node and the bipolar transistor NPN share a doping region, it is obvious that the damage of the diode at the node will also damage the bipolar transistor NPN, causing the chip to fail. Therefore, the current flowing through the node is controlled. If the first and second types of shielding regions are used, no matter the doping profile of the first well region 10 is small or large, the current channel of the diode at the node is controlled by the current channel of the shielding region (i.e., the alternating region ALS), and the diode at the node is easily cut off by the stored charge. Therefore, the doping requirements for the node and the first well region 10 are reduced.

[0150] See also Figure 7 , the present application also discloses a method for improving the surge resistance of a hard disk, using an integrated chip to absorb the surge signal S0 injected into the protected circuit in the hard disk: the surge signal injected into the protected circuit in the hard disk is guided to charge the capacitor between the groove cluster and the conductive layer 44, so as to form a stored charge at the conductive material 52 in the groove 50. In the process of discharging the surge signal by a pair of bipolar transistors NPN and PNP that are triggered to conduct, the stored charge at the capacitor is used to reversely discharge and deplete the connection area 14, thereby locking the current channel at the node. The present method can also use the equivalent voltage to cut off the current channel in the local area between a groove 50 of the substrate PS that is located in the groove cluster and is closest to the first well area 10 and the first well area 10 mentioned above: the first type of shielding area of ​​the first conductivity type and the second type of shielding area of ​​the second conductivity type are alternately implanted in the local area, and the first type of shielding area and the second type of shielding area are mutually depleted under the action of the equivalent voltage. Combined with Figures 1 to 6 , such as reverse pressure effect.

[0151] The above description and drawings provide typical embodiments of specific structures of specific embodiments. The above application proposes existing preferred embodiments, but these contents are not intended to be limiting. For those skilled in the art, various changes and modifications will undoubtedly be obvious after reading the above description. Therefore, the attached claims should be regarded as covering all changes and modifications to the true intention and scope of the present application. Any and all equivalent scopes and contents within the scope of the claims should be considered to still be within the intention and scope of the present application.

Claims

1. An integrated chip, characterized in that: include: A groove cluster having a plurality of grooves is provided on a front surface of a substrate of a first conductivity type, wherein an inner wall of each groove is provided with an insulating layer and the interior of each groove is filled with a conductive material; A first well region of the second conductivity type is implanted on the front side of the substrate, and a second well region of the first conductivity type is implanted on the back side of the substrate, wherein the first well region and the second well region are located at opposite sides of the trench cluster respectively; A first doped region of the second conductivity type, a heavily doped region, a third doped region of the first conductivity type, and a connecting region implanted in the first well region, wherein the first doped region and the conductive material in each trench have the same potential; A second doping region of the second conductivity type and a fourth doping region of the first conductivity type implanted in the second well region; A conductive layer disposed on the back side of the substrate and having a common electrical potential with the second and fourth doped regions; Under the condition that the surge signal connected to the heavily doped region and the third doped region causes the node between the first doped region and the connection region to reversely break down, a bipolar transistor between the first and second doped regions and the substrate and another bipolar transistor between the third and fourth doped regions and the first well region are triggered to conduct and discharge the surge signal; The equivalent voltage of the stored charges of the conductive material in each trench is used to cut off the current path from the node in the reverse breakdown state to the substrate.

2. The integrated chip according to claim 1, characterized in that: Also included is a top dielectric layer covering the front side of the substrate and a bottom dielectric layer covering the back side of the substrate; A top electrode layer for receiving the surge signal covers the top dielectric layer, and the top electrode layer passes through a through hole provided in the top dielectric layer to contact the heavily doped region and the third doped region respectively; A bottom electrode layer for connecting to a reference ground covers the bottom dielectric layer. The bottom electrode layer passes through a through hole arranged in the bottom dielectric layer and contacts the second and fourth doping regions and the conductive layer respectively.

3. The integrated chip according to claim 2, characterized in that: It also includes an interconnect electrode layer covering the top dielectric layer. The interconnect electrode layer passes through the through holes provided in the top dielectric layer and contacts the first doped region and the conductive materials in each groove respectively, thereby electrically connecting the first doped region and the conductive materials in each groove.

4. The integrated chip according to claim 1, characterized in that: It also includes one or more slots opened on the front side of the substrate, spanning the grooves and extending to the first doping region, each slot having an inner wall lined with an isolation layer and the interior of each slot filled with a conductor material; The slot body is provided with contact holes at the intersection position intersecting with the groove and at the part contacting with the first doping region, so that the conductor material in each slot body is electrically connected to the conductive material in the groove and the first doping region respectively.

5. The integrated chip according to claim 1, characterized in that: It also includes one or more buried regions implanted on the back side of the substrate and between the bottom of the trench and the conductive layer, wherein the buried regions are of the second conductivity type and are spaced apart from the conductive layer or directly touch the conductive layer.

6. The integrated chip according to claim 1, characterized in that: A channel region for allowing current of a pair of bipolar transistors to flow is reserved at a position of the substrate between the plurality of trenches. The channel region guides the current flowing through the pair of bipolar transistors to flow from one side of the trench cluster through the trench cluster and laterally to the other side of the trench cluster.

7. The integrated chip according to claim 1, characterized in that: The current channel of a local area of ​​the substrate located between a trench in the trench cluster closest to the first well region and the first well region is cut off by the equivalent voltage; The junction region is arranged at a contour of the first well region to be spaced apart from a surface layer of the front side of the substrate; or The outline of the junction region in the first well region is arranged to touch the surface layer of the front side of the substrate.

8. The integrated chip according to claim 1, characterized in that: The current channel of a local area of ​​the substrate located between a trench in the trench cluster closest to the first well region and the first well region is cut off by the equivalent voltage; The local area is alternately implanted with first-type shielding regions of the first conductivity type and second-type shielding regions of the second conductivity type, and the first and second-type shielding regions reach upward to the surface layer of the front side of the substrate at the local area.

9. The integrated chip according to claim 8, characterized in that: A channel region for allowing current of a pair of bipolar transistors to flow is reserved at a position of the substrate between the plurality of trenches; Based on the condition that the current channel is cut off by the equivalent voltage, the first and second types of shielding regions deplete each other under the action of the equivalent voltage to lock the channel regions between multiple trenches, thereby allowing the actual channel for current flow of a pair of bipolar transistors to move from the original channel region down to the substrate region at the bottom of the trench.

10. The integrated chip according to claim 1, characterized in that: The first conductivity type is a P conductivity type and the second conductivity type is an N conductivity type.

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