Chip test equipment and chip test system

Abstract

The utility model provides a chip testing device and a chip testing system, and relates to the technical field of semiconductor testing. Each chip testing mechanism comprises a rotating disc, a testing station and a plurality of testing jigs distributed along the circumferential direction of the rotating disc, and the testing jigs are used for adsorbing tested chips and rotate along with the rotating disc so as to be matched with the corresponding testing stations, so that performance testing is carried out on the tested chips. All the test fixtures of the at least one chip test mechanism are used for heating the tested chip to a high-temperature state, and all the test fixtures of the at least one chip test mechanism are used for heating the tested chip to a low-temperature state; and the transfer mechanism is used for transferring the tested chip on the test fixture of one chip test mechanism to the other chip test mechanism. According to the technical scheme, the at least two chip testing mechanisms are adopted to carry out high-temperature testing and low-temperature testing on the tested chip respectively, the tested chip does not need to be switched between a high-temperature state and a low-temperature state on the same rotating disc, and the productivity of equipment is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor testing, in particular to a chip testing device and a chip testing system. Background Art

[0002] The electrical performance test of silicon carbide grains requires measuring the electrical performance of silicon carbide grains at different temperatures, such as high temperature around 200°C or low temperature around 20°C, and it is also necessary to measure DC, AC, avalanche and other electrical performance parameters under different temperature states.

[0003] In the prior art, the electrical performance detection device of silicon carbide grains mainly adopts the following two methods:

[0004] The first method is to use a linear method. First, the die to be tested is placed on the test fixture. After the test is completed, the tested die is removed and then the next die to be tested is placed.

[0005] The second type: using a turntable; when one station on the turntable is loading materials, other stations can be testing, unloading, etc. at the same time.

[0006] For the first method, since placing the die to be tested, testing the electrical properties, and removing the tested die are all done on a test fixture, it takes a long time, resulting in low equipment productivity.

[0007] For the second method, because the same turntable can load, unload and test at the same time, although the time required is less than the linear method, it can improve the equipment's production capacity. However, when there are different temperature tests such as high temperature and low temperature, the same test fixture must be switched between high temperature and low temperature. At this time, it takes a long time to cool from high temperature to low temperature, or to heat from low temperature to high temperature, which will also lead to lower equipment production capacity. Utility Model Content

[0008] One purpose of the utility model is to provide a chip testing device to solve the technical problem in the prior art that the device production capacity is low when a test fixture on a turntable is used to perform high temperature and low temperature tests on a chip.

[0009] Another object of the utility model is to provide a chip having the above chip testing device.

[0010] In particular, the utility model provides a chip testing device, comprising:

[0011] A plurality of chip testing mechanisms, each of which comprises a turntable, at least one testing station and a plurality of testing fixtures distributed along the circumference of the turntable, wherein the testing fixture is used to absorb the chip under test and rotate with the turntable to cooperate with the corresponding testing station, so as to perform performance testing on the chip under test; among the plurality of chip testing mechanisms, all the testing fixtures of at least one chip testing mechanism are used to heat the chip under test to a high temperature state, and all the testing fixtures of at least one chip testing mechanism are used to heat the chip under test to a low temperature state;

[0012] At least one transfer mechanism, the transfer mechanism is used to transfer the chip under test on the test fixture of one of the chip testing mechanisms to another chip testing mechanism.

[0013] Optionally, a first adsorption component for adsorbing the chip under test is provided at the bottom of the test fixture, and an air channel for vacuuming is provided inside the first adsorption component.

[0014] Optionally, the chip testing mechanism further includes:

[0015] A heating plate is arranged at the first adsorption component and is used to heat the first adsorption component so as to heat the chip under test to a high temperature state or a low temperature state.

[0016] Optionally, the chip testing mechanism further includes:

[0017] The testing machine is arranged below the turntable, and a plurality of circumferentially distributed testing stations are installed on the top.

[0018] Optionally, a plurality of the test fixtures are evenly distributed on the turntable, and an angle between two adjacent test fixtures is the same as an angle between two adjacent test stations.

[0019] Optionally, the number of the test fixtures is greater than the number of the test stations.

[0020] Optionally, the multiple test stations of the chip testing mechanism close to the feeding component are located downstream of the feeding component. After the previous test fixture among the multiple test fixtures absorbs the chip under test from the feeding component and rotates a preset angle with the turntable, it cooperates with the first test station to perform a performance test on the chip under test, and at the same time, the next test fixture absorbs the next chip under test from the feeding component.

[0021] Optionally, the transfer mechanism comprises: a first slide rail extending along a first direction, the first direction being an arrangement direction of the plurality of chip testing mechanisms;

[0022] A second slide rail extending along a second direction perpendicular to the first direction and connected to the first slide rail;

[0023] The second adsorption assembly is installed on the second slide rail, and is used for adsorbing the chip under test and sliding along the first slide rail and the second slide rail, so as to transfer the chip under test from one chip testing mechanism to another chip testing mechanism.

[0024] Optionally, a suction nozzle is provided on the top of the second adsorption component, and the top of the suction nozzle has a mounting position for placing the chip under test. A vacuum adsorption air channel is provided inside the suction nozzle, and the vacuum adsorption air channel is connected to the mounting position to adsorb the chip under test on the mounting position when vacuuming.

[0025] In particular, the utility model also provides a chip testing system, comprising:

[0026] A feeding mechanism, used for providing the chip to be tested;

[0027] The chip testing device as mentioned above is located near the loading mechanism, and is used to receive the chip under test at the loading mechanism and perform performance testing on the chip under test;

[0028] The unloading mechanism is located at a side of the chip testing device away from the loading mechanism, and is used to remove the chip under test after the performance test on the chip testing device is completed.

[0029] According to the solution of the utility model, each chip testing mechanism includes a turntable, at least one test station and a plurality of test fixtures distributed along the circumference of the turntable. The test fixture is used to absorb the chip under test and rotate with the turntable to cooperate with the corresponding test station to perform functional testing on the chip under test. All test fixtures in at least one chip testing mechanism are used to heat the chip under test to a high temperature state, and all test fixtures in at least one chip testing mechanism are used to heat the chip under test to a low temperature state. The transfer mechanism is used to transfer the chip under test on the test fixture of one of the chip testing mechanisms to another chip testing mechanism. In other words, the above technical solution uses at least two chip testing mechanisms to perform high temperature testing and low temperature testing on the chip under test, respectively. There is no need to heat the chip under test from low temperature to high temperature and cool from high temperature to low temperature on the same turntable, which saves test time and improves the production capacity of the equipment.

[0030] Based on the detailed description of the specific embodiments of the present invention in combination with the accompanying drawings below, those skilled in the art will become more aware of the above and other purposes, advantages and features of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Hereinafter, some specific embodiments of the present invention will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the accompanying drawings:

[0032] Figure 1 is a schematic structural diagram of a chip testing device according to an embodiment of the utility model;

[0033] Figure 2 yes Figure 1 A schematic structural diagram of a chip testing mechanism and a transfer mechanism in the chip testing device shown;

[0034] Figure 3 yes Figure 1 A schematic top view of a chip testing mechanism and a transfer mechanism in the chip testing device shown;

[0035] Figure 4 is a schematic structural diagram of a testing machine according to an embodiment of the utility model;

[0036] Figure 5 yes Figure 2 A schematic structural diagram of a test fixture and a test station in a chip testing mechanism shown in FIG.

[0037] Figure 6 is a schematic structural diagram of a test fixture according to an embodiment of the utility model;

[0038] Figure 7 is a schematic cross-sectional view of a second adsorption assembly according to an embodiment of the utility model;

[0039] Figure 8 is a schematic structural diagram of a transfer mechanism according to an embodiment of the utility model;

[0040] Fig. 9 yes Figure 8 A schematic structural diagram of the suction nozzle of the intermediate transfer mechanism;

[0041] Fig.10 It is a schematic connection block diagram of a chip testing system according to an embodiment of the utility model.

[0042] Reference numerals:

[0043] 1000-chip testing system, 100-chip testing equipment, 200-chip under test, 300-loading mechanism, 400-unloading mechanism, 10-chip testing mechanism, 20-turntable, 30-testing station, 40-testing fixture, 50-transfer mechanism, 60-testing machine, 70-feeding component, 41-first adsorption component, 51-first slide rail, 52-second slide rail, 53-second adsorption component, 411-air nozzle, 412-first air channel, 413-second air channel, 531-suction nozzle, 532-vacuum adsorption air channel. DETAILED DESCRIPTION

[0044] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0045] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0046] In the description of the present invention, it should be understood that the terms "up", "down", "left", "right", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0047] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features, that is, include one or more of the features. In the description of the present utility model, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. When a feature "includes or contains" one or some of the features it covers, unless otherwise specifically described, this indicates that other features are not excluded and may further include other features.

[0048] Unless otherwise clearly specified and limited, the terms "connection", "installation" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. A person skilled in the art should be able to understand the specific meanings of the above terms in the present utility model according to the specific circumstances.

[0049] Unless otherwise defined, all terms (including technical terms and scientific terms) used in the description of this embodiment have the same meanings as commonly understood by ordinary technicians in the technical field to which this application belongs.

[0050] Figure 1 is a schematic structural diagram of a chip testing device 100 according to an embodiment of the present utility model. Figure 2 yes Figure 1 The schematic structural diagram of the chip testing mechanism 10 and the transfer mechanism 50 in the chip testing device 100 is shown. Figure 3 yes Figure 1 FIG. 1 is a schematic top view of a chip testing mechanism 10 and a transfer mechanism 50 in a chip testing device 100. Figures 1 to 3 As shown, in this embodiment, the chip testing device 100 includes multiple chip testing mechanisms 10 and at least one transfer mechanism 50. Each chip testing mechanism 10 includes a turntable 20, at least one test station 30, and multiple test fixtures 40 distributed along the circumference of the turntable 20. The test fixture 40 is used to absorb the chip 200 under test and rotate with the turntable 20 to cooperate with the corresponding test station 30, so as to perform performance testing on the chip 200 under test. Among the multiple chip testing mechanisms 10, all the test fixtures 40 of at least one chip testing mechanism 10 are used to heat the chip 200 under test to a high temperature state, and all the test fixtures 40 of at least one chip testing mechanism 10 are used to heat the chip 200 under test to a low temperature state. The transfer mechanism 50 is used to transfer the chip 200 under test on the test fixture 40 of one chip testing mechanism 10 to another chip testing mechanism 10. It can be understood that the test fixtures 40 on the same turntable 20 are heated to the same temperature, and the test fixtures 40 on the same turntable 20 do not need to be heated from a low temperature to a high temperature or cooled from a high temperature to a low temperature when testing the chip 200 under test.

[0051] This embodiment uses at least two chip testing mechanisms 10 to perform high temperature testing and low temperature testing on the chip 200 under test, respectively. There is no need to heat the chip 200 under test from low temperature to high temperature and cool it from high temperature to low temperature on the same turntable 20, which saves testing time and improves the production capacity of the equipment.

[0052] In some embodiments, the number of chip testing mechanisms 10 is two, one of which is used to perform a high temperature test on the chip under test 200, and the other is used to perform a low temperature test on the chip under test 200. In other embodiments, the number of chip testing mechanisms 10 can also be designed according to specific design requirements, for example, four chip testing mechanisms 10 are designed, two of which are used to perform a high temperature test on the chip under test 200, and the other two are used to perform a low temperature test on the chip under test 200.

[0053] Figure 4 FIG. 6 is a schematic structural diagram of a testing machine 60 according to an embodiment of the present invention. Figure 4 As shown, and see Figure 1 , Figure 1 The test machine 60 is not shown, only the test station 30 is shown. In this embodiment, the chip testing mechanism 10 also includes a test machine 60, which is arranged below the turntable 20, and a plurality of circumferentially distributed test stations 30 are installed on the top. It can be understood that the test machine 60 is located below the turntable 20 and is used to perform performance testing on the chip 200 under test.

[0054] Figure 5 yes Figure 2 The schematic structural diagram of the test fixture 40 and the test station 30 in the chip testing mechanism 10 is shown in FIG. Figure 6 is a schematic structural diagram of a test fixture 40 according to an embodiment of the present utility model. Figure 7 FIG. 5 is a schematic cross-sectional view of a second adsorption assembly 53 according to an embodiment of the present invention. Figures 5 to 7 As shown, in some embodiments, the bottom of the test fixture 40 is provided with a first adsorption component 41 for adsorbing the chip under test 200, and the first adsorption component 41 is provided with an air channel for vacuuming. The first adsorption component 41 is provided with a first air channel 412 arranged in the horizontal direction and a second air channel 413 arranged in the vertical direction, and the first air channel 412 is connected to the second air channel 413. An air nozzle 411 is provided at one end of the first air channel 412, and the air nozzle 411 is connected to the vacuuming device. The chip under test 200 is located below the second air channel 413. The vacuuming device vacuums through the air nozzle 411, the first air channel 412 and the second air channel 413 in sequence to adsorb the chip under test 200. Here, the functional surface of the chip under test 200 faces downward, and the test station 30 has a test probe, which contacts the functional surface of the chip under test 200 to perform performance testing on the chip under test 200.

[0055] In this embodiment, the chip testing mechanism 10 further includes a heating plate, which is disposed at the first adsorption component 41 and is used to heat the first adsorption component 41 to heat the chip 200 under test to a high temperature state or a low temperature state. Here, the heating plate is disposed on the top of the first adsorption component 41.

[0056] In some embodiments, each test station 30 of the chip testing mechanism 10 is configured to perform different functional tests on the chip under test 200. That is, when each test fixture 40 cooperates with any test station 30 to test the chip under test 200, different performances of the chip under test 200 are tested respectively. However, the temperature of the test fixtures 40 on the same turntable 20 is the same, that is, different functions of the chip under test 200 are tested at the same temperature. Preferably, the test station 30 located in the middle performs AC performance tests on the chip under test 200, and the other test stations 30 can perform DC and avalanche tests on the chip under test 200.

[0057] In some embodiments, multiple test fixtures 40 are evenly distributed on the turntable 20, and the angle between two adjacent test fixtures 40 is the same as the angle between two adjacent test stations 30, so that the test fixture 40 can be aligned with the next test station 30 after rotating a certain angle, and multiple chips under test 200 can be simultaneously tested for performance. If only one test station 30 is provided, the angle between two adjacent test fixtures 40 can be designed according to specific design requirements, and then the turntable 20 is controlled to rotate, driving multiple test fixtures 40 to cooperate with the test stations 30 in turn.

[0058] In some embodiments, the number of test fixtures 40 is greater than the number of test stations 30. For example, the number of test fixtures 40 can be set to six, and the number of test stations 30 can be set to three. In other embodiments, the number of test fixtures 40 and test stations 30 can also be selected according to specific design requirements.

[0059] In some embodiments, a plurality of test stations 30 of the chip testing device 100 close to the feeding component 70 are located downstream of the feeding component 70. After the previous test fixture 40 of the plurality of test fixtures 40 absorbs the chip under test 200 from the feeding component 70 and rotates by a preset angle with the turntable 20, it performs a functional test on the chip under test 200 together with the first test station 30. At the same time, the next test fixture 40 absorbs the next chip under test 200 from the feeding component 70. See Figure 2 Here, the preset angle is designed according to the number of the test fixtures 40. The greater the number of the test fixtures 40, the greater the preset angle. A motor is provided in the middle of the turntable 20, and the turntable 20 is driven to rotate by the motor.

[0060] In this embodiment, the number of test fixtures 40 is six, and the number of test stations 30 is three chips under test. The angle between two adjacent test fixtures 40 is 60°, and the angle between two adjacent test stations 30 is also 60°. Each test station 30 corresponds to a test fixture 40, see Figure 2 . Figure 2 The leftmost test fixture 40 is named as test fixture 1, and in the counterclockwise direction, they are named as test fixture 2, test fixture 3, test fixture 4, test fixture 5 and test fixture 6. The leftmost test station 30 is named as test station 1, and in the counterclockwise direction, they are named as test station 2 and test station 3. The feeding component 70 is located below the test fixture 1. When testing the chip 200 under test, the test fixture 1 absorbs the chip 200 under test from the feeding component 70, and then the turntable 20 rotates 60° counterclockwise. At this time, the test fixture 1 is located above the test station 1, and the test fixture 6 is located above the feeding component 70. The test fixture 1 is driven by the driving mechanism to move downward to cooperate with the test station 1 to perform performance testing on the chip 200 under test. At the same time, the test fixture 6 absorbs the chip 200 under test on the feeding component 70. Then the turntable 20 continues to rotate 60° counterclockwise, at which time the test fixture 1 is located above the test station 2, the test fixture 6 is located above the test station 1, and the test fixture 1 moves downward under the drive of the drive mechanism to cooperate with the test station 2 to perform a performance test on the chip 200 under test. The test fixture 6 moves downward under the drive of the drive mechanism to cooperate with the test station 1 to perform a performance test on the chip 200 under test. At the same time, the test fixture 5 adsorbs the chip 200 under test on the feeding component 70. Then the turntable 20 continues to rotate 60° counterclockwise, at which time the test fixture 1 is located above the test station 3, the test fixture 6 is located above the test station 2, and the test fixture 5 is located above the test station 1. The test fixture 3 moves downward under the drive of the drive mechanism to cooperate with the test station 3 to perform a performance test on the chip 200 under test. The test fixture 6 moves downward under the drive of the drive mechanism to cooperate with the test station 2 to perform a performance test on the chip 200 under test. The test fixture 5 is driven by the driving mechanism to move downward to cooperate with the test station 1 to perform performance tests on the chip 200 under test. That is to say, this embodiment can perform performance tests on three chips 200 under test at the same time. Then the turntable 20 continues to rotate 60°, the test fixture 1 rotates to the unloading position, the test fixture 6 is located above the test station 3, the test fixture 5 is located above the test station 2, and the test fixture 4 is located above the test fixture 1 to continue the performance test. The transfer mechanism 50 moves to the bottom of the test fixture 1 to receive the chip 200 under test at the test fixture 1, and moves the chip 200 under test to the loading position of the next turntable 20, so that the test fixture 40 on another turntable 20 continues to perform performance tests on the chip 200 under test. Figure 2In the figure, the chip testing mechanism 10 on the left is used to perform high temperature testing on the chip under test 200, and the chip testing mechanism 10 on the right is used to perform low temperature testing on the chip under test 200. The driving mechanism is a motor, and each test fixture 40 is equipped with a driving mechanism, which is used to drive the corresponding test fixture 40 to move downward and dock with the corresponding test station 30, so that the test probe on the test station 30 contacts the chip under test 200 on the test fixture 40, so that the test machine 60 performs performance testing on the chip under test 200.

[0061] Figure 8 is a schematic structural diagram of a transfer mechanism 50 according to an embodiment of the utility model. Fig. 9 yes Figure 8 Schematic structural diagram of the suction nozzle 531 of the transfer mechanism 50. The transfer mechanism 50 includes a first slide rail 51, a second slide rail 52, and a second adsorption component 53. The first slide rail 51 extends along a first direction, and the first direction is the arrangement direction of multiple chip testing mechanisms 10. The second slide rail 52 extends along a second direction perpendicular to the first direction and is connected to the first slide rail 51. The second adsorption component 53 is installed on the second slide rail 52, and is used to adsorb the chip 200 under test, and slides with the first slide rail 51 and the second slide rail 52, so as to transfer the chip 200 under test from one chip testing mechanism 10 to another chip testing mechanism 10.

[0062] In this embodiment, a suction nozzle 531 is provided at the top of the second adsorption component 53, and the top of the suction nozzle 531 has a mounting position for placing the chip under test 200. A vacuum adsorption airway 532 is provided inside the suction nozzle 531, and the vacuum adsorption airway 532 is connected to the mounting position to adsorb the chip under test 200 on the mounting position when vacuuming. Here, the second adsorption component 53 uses a linear rotary actuator, i.e., a ZR actuator, which can rotate to align with the chip under test 200, so as to better receive the chip under test 200.

[0063] Fig.10 FIG. 1 is a schematic connection block diagram of a chip testing system 1000 according to an embodiment of the present invention. Fig.10As shown, this embodiment also provides a chip testing system 1000, and the chip testing system 1000 includes a loading mechanism 300, a unloading mechanism 400, and a chip testing device 100 as in any of the above embodiments. The chip testing device 100 is not described in detail here. The loading mechanism 300 is used to provide the chip under test 200. The chip testing device 100 is located at a position close to the loading mechanism 300, and is used to receive the chip under test 200 at the loading mechanism 300, and perform performance tests on the chip under test 200. The unloading mechanism 400 is located on the side of the chip testing device 100 away from the loading mechanism 300, and is used to remove the chip under test 200 after the performance test on the chip testing device 100. Here, the loading mechanism 300 is used to transfer the chip under test 200 to the feeding component 70. When the chip under test 200 has passed all performance tests, the unloading mechanism 400 will transfer the chip under test 200 after the test is completed from the test fixture 40 to the blue film, and then unload it.

[0064] This embodiment uses two chip testing mechanisms 10, which can realize simultaneous loading, multiple different performance tests and unloading of the chip 200 under test. Two turntables 20 are used. The temperature of the test fixture 40 on the same turntable 20 is the same, and no additional heating or cooling time is required. The temperature of the test fixture 40 on different turntables 20 is different, and the electrical performance parameters of the chip 200 under test at different temperatures can be tested.

[0065] At this point, those skilled in the art should recognize that, although multiple exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications that conform to the principles of the present invention can still be directly determined or derived from the contents disclosed in the present invention without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be understood and recognized as covering all such other variations or modifications.

Claims

1. A chip testing device, characterized in that: include: A plurality of chip testing mechanisms, each of which comprises a turntable, at least one testing station and a plurality of testing fixtures distributed along the circumference of the turntable, wherein the testing fixture is used to absorb the chip under test and rotate with the turntable to cooperate with the corresponding testing station, so as to perform performance testing on the chip under test; among the plurality of chip testing mechanisms, all the testing fixtures of at least one chip testing mechanism are used to heat the chip under test to a high temperature state, and all the testing fixtures of at least one chip testing mechanism are used to heat the chip under test to a low temperature state; At least one transfer mechanism, the transfer mechanism is used to transfer the chip under test on the test fixture of one of the chip testing mechanisms to another chip testing mechanism.

2. The chip testing device according to claim 1, characterized in that: A first adsorption component for adsorbing the chip under test is disposed at the bottom of the test fixture, and an air channel for vacuuming is disposed inside the first adsorption component.

3. The chip testing device according to claim 2, characterized in that: The chip testing mechanism also includes: A heating plate is arranged at the first adsorption component and is used to heat the first adsorption component so as to heat the chip under test to a high temperature state or a low temperature state.

4. The chip testing device according to claim 1, characterized in that: The chip testing mechanism also includes: The testing machine is arranged below the turntable, and a plurality of circumferentially distributed testing stations are installed on the top.

5. The chip testing device according to claim 4, characterized in that: The plurality of test jigs are evenly distributed on the turntable, and the angle between two adjacent test jigs is the same as the angle between two adjacent test stations.

6. The chip testing device according to claim 5, characterized in that: The number of the test fixtures is greater than the number of the test stations.

7. The chip testing device according to claim 6, characterized in that: The multiple test stations of the chip testing mechanism close to the feeding component are located downstream of the feeding component. After the previous test fixture among the multiple test fixtures absorbs the chip under test from the feeding component and rotates with the turntable at a preset angle, it cooperates with the first test station to perform a performance test on the chip under test, while the next test fixture absorbs the next chip under test from the feeding component.

8. The chip testing device according to any one of claims 1 to 7, characterized in that: The transfer mechanism comprises: A first slide rail extending along a first direction, wherein the first direction is an arrangement direction of the plurality of chip testing mechanisms; A second slide rail extending along a second direction perpendicular to the first direction and connected to the first slide rail; The second adsorption assembly is installed on the second slide rail, and is used for adsorbing the chip under test and sliding along the first slide rail and the second slide rail, so as to transfer the chip under test from one chip testing mechanism to another chip testing mechanism.

9. The chip testing device according to claim 8, characterized in that: A suction nozzle is provided on the top of the second adsorption component, and the top of the suction nozzle has a mounting position for placing the chip under test. A vacuum adsorption air channel is provided inside the suction nozzle, and the vacuum adsorption air channel is connected with the mounting position to adsorb the chip under test on the mounting position when vacuuming.

10. A chip testing system, characterized in that: include: A feeding mechanism, used for providing the chip to be tested; The chip testing device according to any one of claims 1 to 9, located near the loading mechanism, for receiving the chip under test at the loading mechanism and performing a performance test on the chip under test; The unloading mechanism is located at a side of the chip testing device away from the loading mechanism, and is used to remove the chip under test after the performance test on the chip testing device is completed.

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