Multi-channel clock source, quantum computing measurement and control system and quantum computer

Abstract

The utility model discloses a multi-channel clock source, a quantum computing measurement and control system and a quantum computer. The multi-channel clock source comprises a case; the clock source is positioned in the case and is used for providing a reference clock signal; the first power divider is positioned in the case and is used for dividing the reference clock signal into a plurality of first clock signals; the first signal connectors are integrated on the case, each first signal connector is electrically connected with a signal transmission line, the other end of each signal transmission line is electrically connected with one output end of the first power divider, and the lengths of the signal transmission lines are equal. A reference clock signal output by a clock source is divided into a plurality of first clock signals by a first power divider, so that the homology of the plurality of first clock signals is ensured, and the synchronism of the first clock signals output by the first power divider is ensured; the multiple signal transmission lines are equal in length, and it is guaranteed that the multiple first clock signals are still kept synchronous when transmitted to the first signal connector through the signal transmission lines.

Description

Technical Field

[0001] The utility model relates to the technical field of quantum computers, in particular to a multi-channel clock source, a quantum computing measurement and control system and a quantum computer. Background Art

[0002] Quantum computers are physical devices that follow the laws of quantum mechanics to perform high-speed mathematical and logical operations, store and process quantum information, including quantum chips and quantum measurement and control systems. Quantum chips are the core components for running quantum computing. When performing quantum computing tasks, quantum chips need to be executed strictly according to the timing, so clock signals are required. As the number of quantum bits integrated on the quantum chip increases, more clock signals are required, and the synchronization of clock signals is difficult to ensure, which makes the synchronization of the control signals output by the quantum control system poor. Therefore, there is an urgent need for a clock source that can provide multiple clock signals with good synchronization.

[0003] It should be noted that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Utility Model Content

[0004] The utility model aims to provide a multi-channel clock source with good synchronization, a quantum computing measurement and control system and a quantum computer.

[0005] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0006] The utility model provides a multi-channel clock source in a first aspect, comprising: a chassis; a clock source located in the chassis, used to provide a reference clock signal; a first power divider located in the chassis, used to divide the reference clock signal into multiple first clock signals; multiple first signal connectors integrated on the chassis, each first signal connector is electrically connected to a signal transmission line, the other end of the signal transmission line is electrically connected to an output end of the first power divider, and the multiple signal transmission lines are equal in length.

[0007] As the multi-channel clock source described above, further, a second signal connector is provided at the place where each of the signal transmission lines is electrically connected to the first signal connector; and the torque when any one of the first signal connectors is electrically connected to any one of the second signal connectors is the same.

[0008] The multi-channel clock source as described above further includes a plurality of second power dividers located in the chassis, each second power divider being used for dividing the power of one channel of the first clock signal into a plurality of second clock signals.

[0009] As described above, the multi-channel clock source, further, each of the signal transmission lines is composed of a first cable and a second cable that are electrically connected; the first cable is used to electrically connect an output end of the first power divider with an input end of the second power divider; the second cable is used to electrically connect an output end of the second power divider with a first signal connector; the lengths of the multiple first cables are equal, and the lengths of the multiple second cables are equal.

[0010] The multi-channel clock source as described above further includes a first PCB board arranged in the chassis, and a first voltage stabilizing circuit is integrated on the first PCB board; the first voltage stabilizing circuit is used to stabilize the received external voltage and output it to the first power divider and the second power divider.

[0011] The multi-channel clock source as described above further includes a heat-insulating shell located in the chassis, and the clock source is encapsulated in the heat-insulating shell.

[0012] As the multi-channel clock source as described above, further, the first side panel and the second side panel arranged opposite to each other in the chassis are both provided with ventilation holes, and the ventilation holes are arranged away from the heat preservation shell and close to the first PCB board.

[0013] As the multi-channel clock source described above, further, a second voltage stabilizing circuit is provided in the heat-insulating shell, and the second voltage stabilizing circuit is used for stabilizing the received external voltage and outputting the voltage to the clock source.

[0014] The second aspect of the utility model provides a quantum computing measurement and control system, comprising the above-mentioned multi-channel clock source and a signal generation module, wherein the signal generation module outputs a measurement and control signal based on a clock signal provided by the multi-channel clock source.

[0015] The third aspect of the utility model provides a quantum computer, comprising the above-mentioned quantum computing measurement and control system and a quantum chip, wherein the quantum chip performs quantum computing tasks according to the measurement and control signals provided by the quantum computing measurement and control system.

[0016] The beneficial effects of the utility model are:

[0017] The present application uses a first power divider to divide the reference clock signal output by a clock source into multiple first clock signals, ensuring that the multiple first clock signals have the same source, thereby ensuring the consistency of the first clock signals output from the first power divider. At the same time, the length of the signal transmission line between each output end of the first power divider and each first signal connector is equal, ensuring that the multiple first clock signals are transmitted to the first signal connector via the signal transmission line and maintain synchronization.

[0018] The quantum computing measurement and control system and quantum computer provided by the utility model include the above-mentioned multi-channel clock source, and therefore have the same beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the first structure of a multi-channel clock source provided by an embodiment of the utility model;

[0020] Figure 2 A second structural diagram of a multi-channel clock source provided by an embodiment of the utility model;

[0021] Figure 3 A schematic diagram of the structure in which a clock source provided in an embodiment of the utility model is encapsulated in a heat-insulating shell.

[0022] In the reference numerals:

[0023] 1. Chassis; 2. First power divider; 3. Second power divider; 4. Clock source; 5. First cable; 6. Second cable; 7. First signal connector; 8. First PCB board; 9. Third PCB board; 10. Ventilation port; 11. Insulation shell; 12. Fan; 13. Power adapter. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limitations on the present application.

[0025] In the description of the present invention, it should be understood that the terms "center", "up", "down", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0026] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0027] Figure 1 A first structural diagram of a multi-channel clock source provided by an embodiment of the utility model; Figure 1 As shown: An embodiment of the present application discloses a multi-channel clock source, comprising: a chassis 1; a clock source 4 located in the chassis 1, for providing a reference clock signal; a first power divider 2 located in the chassis 1, for dividing the reference clock signal into multiple first clock signals; multiple first signal connectors 7 integrated on the chassis 1, each first signal connector 7 is electrically connected to a signal transmission line, the other end of the signal transmission line is electrically connected to an output end of the first power divider 2, and the multiple signal transmission lines are equal in length.

[0028] In this embodiment, the reference clock signal output by the clock source 4 is divided into multiple first clock signals by the first power divider 2, thereby ensuring that the multiple first clock signals have the same source, thereby ensuring the consistency of the first clock signals output from the first power divider 2. At the same time, the length of the signal transmission line between each output end of the first power divider 2 and each first signal connector 7 is equal, thereby ensuring that the multiple first clock signals are transmitted to the first signal connector 7 via the signal transmission line and maintain synchronization.

[0029] In the present embodiment, there is no specific restriction on the type of signal transmission line, which may be a semi-rigid line, a semi-flexible line, or a flexible line. A semi-rigid line is preferably used because the semi-rigid line has lower transmission loss, good high-frequency characteristics, strong anti-interference ability and higher reliability. Therefore, the semi-rigid line is used here to ensure the stability of the signal. In addition, the semi-rigid line is convenient for regular wiring in the chassis 1.

[0030] In this embodiment, the clock source 4 uses a constant temperature crystal oscillator, which has the characteristics of high stability and low phase noise, so that the clock signal has the characteristics of high stability and low phase noise.

[0031] In some implementations of this embodiment, a second signal connector is provided at the electrical connection between each of the signal transmission lines and the first signal connector 7; the torque when any one of the first signal connectors 7 is electrically connected to any one of the second signal connectors is the same, which further improves the synchronization of the clock signal. In this implementation, the types of the first signal connector 7 and the second signal connector are not specifically limited. For example, when the first signal connector 7 is one of an SMA male, an SMP male, and an SMPM male, the second signal connector is one of an SMA female, an SMP female, and an SMPM female; when the first signal connector 7 is one of an SMA female, an SMP female, and an SMPM female, the second signal connector is one of an SMA male, an SMP male, and an SMPM male.

[0032] Figure 2 A second structural diagram of a multi-channel clock source provided by an embodiment of the utility model; Figure 2 As shown: In some implementations of this embodiment, the multi-channel clock source further includes a plurality of second power dividers 3 located in the chassis 1, each second power divider 3 being used to power divide one channel of the first clock signal into a plurality of second clock signals. By arranging a plurality of second power dividers 3, one channel of the first clock signal is power divided into a plurality of second clock signals to meet the needs of a quantum chip with a higher number of bits. In order to facilitate wiring, the second power dividers 3 are arranged symmetrically about the first power divider 2, so as to facilitate equal-length wiring.

[0033] Two arrangements of the second power divider 3 are given below.

[0034] The first type: a plurality of second power dividers 3 can be arranged along the length direction of the chassis 1 and symmetrically arranged with respect to the first power divider 2 .

[0035] Second type: multiple second power dividers 3 can also be arranged in layers, with multiple layers arranged along the height direction of the chassis 1 , and multiple second power dividers 3 in each layer can be arranged along the length direction of the chassis 1 and symmetrically arranged about the first power divider 2 .

[0036] In some implementations of this embodiment, each of the signal transmission lines is composed of a first cable 5 and a second cable 6 that are electrically connected; the first cable 5 is used to electrically connect an output end of the first power divider 2 and an input end of the second power divider 3; the second cable 6 is used to electrically connect an output end of the second power divider 3 and a first signal connector 7; a plurality of the first cables 5 are equal in length, and a plurality of the second cables 6 are equal in length; such an arrangement improves the synchronization of multiple second clock signals. Further, a third signal connector is provided at one end of any first cable 5, and a fourth signal connector is provided at any output end of the first power divider 2. The third signal connector and the fourth signal connector are electrically connected to realize the electrical connection between the first cable 5 and the first power divider 2. In order to improve the synchronization of the clock signal, the torque when any third signal connector and any fourth signal connector are electrically connected is the same. A fifth signal connector is provided at the other end of any first cable 5, a sixth signal connector is provided at the input end of any second power divider 3, the fifth signal connector and the sixth signal connector are electrically connected to realize the electrical connection between the first cable 5 and the second power divider 3, and in order to improve the synchronization of the signal, the torque when any fifth signal connector and any sixth signal connector are electrically connected is the same. A seventh signal connector is provided at any output end of any second power divider 3, an eighth signal connector is provided at one end of any second cable 6, the seventh signal connector and the eighth signal connector are electrically connected to realize the electrical connection between the second cable 6 and the second power divider 3, and in order to improve the synchronization of the signal, the torque when any seventh signal connector and any eighth signal connector are electrically connected is the same. A tenth signal connector is provided at the other end of any second cable 6, the tenth signal connector and the first signal connector 7 are electrically connected to realize the electrical connection between the second cable 6 and the first signal connector 7, and in order to improve the synchronization of the signal, the torque when any tenth signal connector and any first signal connector 7 are electrically connected is the same.

[0037] In some implementations of this example, continue as Figure 2 As shown: the multi-channel clock source also includes a first PCB board 8 arranged in the chassis 1, and the first PCB board 8 is integrated with a first voltage stabilizing circuit; the first voltage stabilizing circuit is used to stabilize the received external voltage and output it to the first power divider 2 and the second power divider 3.

[0038] By setting the first voltage stabilizing circuit, the first power divider 2 and the second power divider 3 work under a stable voltage, which can ensure that the first power divider 2 and the second power divider 3 can operate under the best working conditions, thereby providing a high-precision and stable clock signal. Further, the external voltage is provided by an external power supply, and a power adapter 13 is also electrically connected between the first PCB board 8 and the external power supply; the power adapter 13 is used to process the external power supply.

[0039] In this embodiment, the first voltage stabilizing circuit is integrated on the first PCB board 8, and the first PCB board 8 is installed in the chassis 1. Compared with arranging the first voltage stabilizing circuit inside the first power divider 2 and the second power divider 3, the arrangement of this embodiment facilitates the heat dissipation of the first voltage stabilizing circuit and improves the integration. In addition, in order to further improve the heat dissipation effect of the first PCB board 8, a heat sink can be arranged on the first PCB board 8. Preferably, a heat conductive adhesive layer is arranged between the first PCB board 8 and the heat sink. By arranging the heat conductive adhesive layer, the heat of the first PCB board 8 is fully transferred to the heat sink.

[0040] In this embodiment, the first power divider 2 and the second power divider 3 both include a box body and a second PCB board encapsulated in the box body, and a plurality of power division circuits are integrated on the second PCB board; in order to further improve the synchronization of the signal after power division, a plurality of isolation plates are arranged in the box body, and the box body is divided into a plurality of cavities to isolate the signal transmission channels of the plurality of power division circuits, increase the isolation between the signal transmission channels, reduce the interference in the signal transmission process, and ensure the synchronization of the signal after power division.

[0041] Figure 3 A schematic diagram of the structure of the clock source 4 provided in the embodiment of the utility model is encapsulated in the heat-insulating housing 11; Figure 3 As shown: In some implementations of this embodiment, the multi-channel clock source also includes a heat-insulating shell 11 located in the chassis 1, and the clock source 4 is encapsulated in the heat-insulating shell 11. By providing the heat-insulating shell 11, the influence of the external environment temperature change on the clock source 4 can be reduced, and at the same time, the electromagnetic interference of the external environment on the clock source 4 can be reduced, thereby improving the stability and accuracy of the clock source 4. This is conducive to the synchronization of the final signal.

[0042] Continue as Figure 3 As shown: In some implementations of this embodiment, a second voltage stabilizing circuit is further provided in the heat-insulating shell 11 , and the second voltage stabilizing circuit is used to stabilize the received external voltage and output it to the clock source 4 .

[0043] By setting the second voltage stabilizing circuit, the stability of the working voltage of the clock source 4 is improved, thereby improving the stability and accuracy of the clock source 4, which is beneficial to the synchronization of the final signal. Exemplarily, the second voltage stabilizing circuit includes a filter circuit to reduce the fluctuation and noise of the input voltage and ensure the stable working condition of the clock source 4.

[0044] Continue as Figure 3As shown: In some implementations of the present embodiment, the second voltage stabilizing circuit is integrated on the third PCB board 9, and the pins on the clock source 4 are electrically connected to the second voltage stabilizing circuit on the third PCB board 9; in the present implementation, the arrangement of the third PCB board 9 in the heat preservation shell 11 is not specifically limited. For example, the two ends of the third PCB board 9 are detachably mounted on the heat preservation shell 11. For example, the heat preservation shell 11 is provided with limiting grooves for placing the two ends of the third PCB board 9, and the two ends of the third PCB board 9 are placed on the limiting grooves, and then the third PCB board 9 is detachably mounted on the heat preservation shell 11 by screws; Figure 3 It can be seen that in this example, the clock source 4 is indirectly installed in the heat-insulating shell 11 through the third PCB board 9. At this time, a gap is arranged between the outer wall of the clock source 4 and the inner wall of the heat-insulating shell 11. In order to improve the anti-seismic effect of the clock source 4, a rubber sleeve can be set on the outer wall of the clock source 4.

[0045] In some implementations of the present embodiment, ventilation holes 10 are provided on the first side panel and the second side panel which are arranged relatively to each other in the chassis 1, and the ventilation holes 10 are arranged away from the thermal insulation shell 11 and close to the first PCB board 8; by providing the ventilation holes 10, the heat generated by the components in the chassis 1 when working can be dissipated in time, and the ventilation holes 10 are arranged away from the thermal insulation shell 11 and close to the first PCB board 8, firstly, to avoid the influence of the external environment on the temperature of the clock source 4, and secondly, to facilitate the heat dissipation of the first PCB board 8.

[0046] Based on the same application concept, the embodiment of the present application also proposes a quantum computing measurement and control system, including the above-mentioned multi-channel clock source, and a signal generation module, wherein the signal generation module outputs a measurement and control signal based on the multi-channel clock source for providing a plurality of clock signals to the quantum chip. The quantum computing measurement and control system of the present application includes the above-mentioned multi-channel clock source, and therefore has the same beneficial effects as the above-mentioned multi-channel clock source, which will not be repeated here.

[0047] Based on the same application concept, the embodiment of the present application also proposes a quantum computer, including the above-mentioned quantum computing measurement and control system and a quantum chip, wherein the quantum chip performs quantum computing tasks according to the measurement and control signal provided by the quantum computing measurement and control system. The quantum computer of the present application includes the above-mentioned quantum computing measurement and control system, and therefore has the same beneficial effects as the above-mentioned quantum computing measurement and control system, which will not be repeated here.

[0048] In the description of this specification, the description with reference to the terms "some embodiments" or "examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0049] The above are only preferred embodiments of the present invention and do not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, may make any equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which shall be deemed as the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A multi-channel clock source, characterized in that: include: Chassis; A clock source located in the chassis, for providing a reference clock signal; A first power divider located in the chassis, used for dividing the reference clock signal into a plurality of first clock signals; A plurality of first signal connectors are integrated on the chassis, each of which is electrically connected to a signal transmission line, the other end of the signal transmission line is electrically connected to an output end of the first power divider, and the plurality of signal transmission lines are of equal length.

2. The multi-channel clock source according to claim 1, characterized in that: A second signal connector is provided at the place where each of the signal transmission lines is electrically connected to the first signal connector; and the torque when any one of the first signal connectors is electrically connected to any one of the second signal connectors is the same.

3. The multi-channel clock source according to claim 1, characterized in that: It also includes a plurality of second power dividers located in the chassis, each second power divider is used to divide the power of one channel of the first clock signal into a plurality of second clock signals.

4. The multi-channel clock source according to claim 3, characterized in that: Each of the signal transmission lines is composed of a first cable and a second cable that are electrically connected; The first cable is used to electrically connect an output end of the first power divider and an input end of the second power divider; The second cable is used to electrically connect an output end of the second power divider with one of the first signal connectors; The first cables have the same length, and the second cables have the same length.

5. The multi-channel clock source according to claim 3, characterized in that: It also includes a first PCB board arranged in the chassis, and a first voltage stabilizing circuit is integrated on the first PCB board; The first voltage stabilizing circuit is used for stabilizing the received external voltage and outputting the voltage to the first power divider and the second power divider.

6. The multi-channel clock source according to claim 5, characterized in that: It also includes a heat-insulating shell located in the chassis, and the clock source is packaged in the heat-insulating shell.

7. The multi-channel clock source according to claim 6, characterized in that: The first side plate and the second side plate which are arranged opposite to each other in the chassis are both provided with ventilation holes, and the ventilation holes are arranged away from the heat-insulating shell and close to the first PCB board.

8. The multi-channel clock source according to claim 6, characterized in that: A second voltage stabilizing circuit is also provided in the heat-insulating shell, and the second voltage stabilizing circuit is used for stabilizing the received external voltage and outputting the voltage to the clock source.

9. A quantum computing measurement and control system, characterized in that: It comprises a multi-channel clock source as described in any one of claims 1 to 8, and a signal generating module, wherein the signal generating module outputs a measurement and control signal based on a clock signal provided by the multi-channel clock source.

10. A quantum computer, characterized in that: It includes the quantum computing measurement and control system and quantum chip as described in claim 9, and the quantum chip performs quantum computing tasks according to the measurement and control signals provided by the quantum computing measurement and control system.

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