Multilayer chip package substrate

Abstract

The utility model discloses a multilayer chip packaging substrate. The multilayer chip packaging substrate comprises a first ceramic layer and a first chip. A first conductive circuit is formed on the upper surface of the first ceramic layer, and a first bonding pad is arranged on the first conductive circuit; the first chip is arranged on the upper surface of the first ceramic layer and is welded and conducted with the first bonding pad; an external bonding pad is formed on the lower surface of the first ceramic layer, and the external bonding pad is connected with the first conducting circuit through a first vertical conducting column in a conducting mode. The second ceramic layer is fixedly attached to the upper surface of the first ceramic layer, and each ceramic layer is provided with the conductive circuit, so that chip packaging can be performed on each ceramic layer, multi-chip three-dimensional packaging is realized, the area of the ceramic packaging substrate does not need to be increased during multi-chip packaging, and the cost is reduced. Therefore, the area of the ceramic packaging substrate is reduced, the occupied area is small, and the development of miniaturization of equipment is facilitated.

Description

Technical Field

[0001] The utility model relates to the field of packaging substrate technology, in particular to a multi-layer chip packaging substrate. Background Art

[0002] The packaging substrate is Substrate (abbreviated as SUB). The packaging substrate can provide electrical connection, protection, support, heat dissipation, assembly and other functions for the chip to achieve multi-pin, reduce the size of the packaged product, improve electrical performance and heat dissipation, ultra-high density or multi-chip modularization. The packaging substrate should be an interdisciplinary technology, which involves knowledge of electronics, physics, chemical engineering, etc. Ceramic packaging substrate refers to copper foil directly bonded to alumina (Al2O3) at high temperature. 2 O 3 ) or aluminum nitride (AlN) ceramic substrate surface (single or double sides). The ultra-thin composite substrate has excellent electrical insulation performance, high thermal conductivity, excellent soft solderability and high adhesion strength, and can be etched with various patterns like PCB boards, with great current carrying capacity. Therefore, ceramic packaging substrates have become the basic materials for high-power power electronic circuit structure technology and interconnection technology.

[0003] The main structure of the current ceramic packaging substrate includes a ceramic layer and a chip; the upper surface of the ceramic layer is formed with a conductive circuit, and the conductive circuit has a pad; the chip is arranged on the upper surface of the ceramic layer and is welded to the pad. However, the ceramic packaging substrate in the prior art is generally a single-layer structure. When more chips need to be packaged, the area of ​​the ceramic packaging substrate needs to be increased, resulting in a large area occupied by the ceramic packaging substrate, which is not conducive to the development of miniaturization of equipment. Therefore, it is necessary to study a solution to solve the above problems. Utility Model Content

[0004] In view of this, the present invention aims to improve the deficiencies of the prior art, and its main purpose is to provide a multi-layer chip packaging substrate, which can effectively solve the problem that the existing ceramic packaging substrate needs to increase the area when performing multi-chip packaging, resulting in a large occupied area and being unfavorable for the miniaturization of equipment.

[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0006] A multi-layer chip packaging substrate includes a first ceramic layer and a first chip; a first conductive circuit is formed on the upper surface of the first ceramic layer, and a first solder pad is provided on the first conductive circuit; the first chip is arranged on the upper surface of the first ceramic layer and is welded and connected with the first solder pad; an external solder pad is formed on the lower surface of the first ceramic layer, and the external solder pad is conductively connected with the first conductive circuit through a first vertical conductive column; a second ceramic layer is adhered and fixed to the upper surface of the first ceramic layer, and a first concave cavity is recessed on the lower surface of the second ceramic layer, the first chip is adapted to the first concave cavity and is located in the first concave cavity; a second conductive circuit is formed on the upper surface of the second ceramic layer, and a second solder pad is provided on the second conductive circuit, and the second conductive circuit is conductively connected with the first conductive circuit through a second vertical conductive column; a second chip is arranged on the upper surface of the second ceramic layer, and the second chip is welded and connected with the second solder pad.

[0007] As a preferred solution, a third ceramic layer is bonded and fixed to the upper surface of the second ceramic layer, a second cavity is recessed on the lower surface of the third ceramic layer, the second chip is adapted to and located in the second cavity, a third conductive circuit is formed on the upper surface of the third ceramic layer, a third solder pad is provided on the third conductive circuit, the third conductive circuit is conductively connected to the second conductive circuit through a third vertical conductive column, a third chip is arranged on the upper surface of the third ceramic layer, and the third chip is welded and conductively connected to the third solder pad to achieve the packaging of more chips.

[0008] As a preferred solution, the lower surface of the second ceramic layer and the upper surface of the first ceramic layer are bonded and fixed by a first thermally conductive adhesive, and the first cavity is filled with the first thermally conductive adhesive, so that the second ceramic layer and the first ceramic layer are firmly combined, the production is simple and easy, and the thermal conductivity is good, which greatly improves the heat dissipation performance of the first chip.

[0009] As a preferred solution, the lower surface of the third ceramic layer and the upper surface of the second ceramic layer are bonded and fixed by a second thermally conductive adhesive, and the second cavity is filled with the first thermally conductive adhesive, so that the third ceramic layer and the second ceramic layer are firmly combined, the production is simple and easy, and the thermal conductivity is good, which greatly improves the heat dissipation performance of the second chip.

[0010] As a preferred solution, the peripheries of the first ceramic layer, the second ceramic layer and the third ceramic layer are covered with a reinforced frame to prevent the first ceramic layer, the second ceramic layer and the third ceramic layer from being easily separated, thereby effectively enhancing the overall structural strength of the product.

[0011] As a preferred solution, the reinforced frame is made of carbon fiber material, which has a stable structure and is light in weight.

[0012] Compared with the prior art, the utility model has obvious advantages and beneficial effects. Specifically, it can be seen from the above technical solution that:

[0013] By bonding and fixing the second ceramic layer on the upper surface of the first ceramic layer and providing a conductive circuit on each ceramic layer, chips can be packaged on each ceramic layer, thereby realizing three-dimensional packaging of multiple chips. When packaging multiple chips, there is no need to increase the area of ​​the ceramic packaging substrate, which is beneficial to reducing the area of ​​the ceramic packaging substrate, occupying a small area, and facilitating the development of miniaturization of equipment.

[0014] In order to more clearly illustrate the structural features and functions of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a cross-sectional view of a preferred embodiment of the utility model.

[0016] Description of the accompanying drawings:

[0017] 10. First ceramic layer 11. First conductive circuit

[0018] 111, first pad 12, external pad

[0019] 13. First vertical conductive column 101, first embedded groove

[0020] 20. First chip 21. First recess

[0021] 22. First patch solder foot 30. Second ceramic layer

[0022] 31. Second conductive circuit 311. Second pad

[0023] 32. Second vertical conductive column 301. First cavity

[0024] 302, second embedding groove 40, second chip

[0025] 41. Second concave position 42. Second patch solder foot

[0026] 50. third ceramic layer 51. third conductive circuit

[0027] 511, third pad 52, third vertical conductive column

[0028] 501, second concave cavity 502, third embedded groove

[0029] 60. third chip 61. third recess

[0030] 62. Third patch soldering foot 71. First thermal conductive adhesive

[0031] 72. Second thermal conductive adhesive 73. Strengthen the frame. DETAILED DESCRIPTION

[0032] Please refer to Figure 1 As shown, it shows the specific structure of a preferred embodiment of the utility model, including a first ceramic layer 10, a first chip 20, a second ceramic layer 30, a second chip 40, a third ceramic layer 50 and a third chip 60.

[0033] The first conductive circuit 11 is formed on the upper surface of the first ceramic layer 10, and the first conductive circuit 11 has a first pad 111; the lower surface of the first ceramic layer 10 is formed with an external pad 12, and the external pad 12 is conductively connected to the first conductive circuit 11 through a first vertical conductive column 13. In this embodiment, the upper surface of the first ceramic layer 10 is concavely provided with a first embedding groove 101, and the first wire circuit 11 is located in the first embedding groove 101, and the first pad 111 protrudes from the upper surface of the first ceramic layer 10, so that the first wire circuit 11 is firmly combined with the first ceramic layer 10 to prevent falling off, and at the same time, the first pad 111 is more stably and reliably in contact with the first chip 20.

[0034] The first chip 20 is disposed on the upper surface of the first ceramic layer 10 and is welded and connected to the first pad 111. In this embodiment, the bottom surface of the first chip 20 has a first recess 21, and the first recess 21 has a first chip solder foot 22. The first pad 111 is embedded in the first recess 21 and is welded and connected to the first chip solder foot 22, so that the structure is more stable and reliable.

[0035] The second ceramic layer 30 is attached and fixed on the upper surface of the first ceramic layer 10, and the lower surface of the second ceramic layer 30 is concavely provided with a first concave cavity 301. The first chip 20 is adapted to and located in the first concave cavity 301. The upper surface of the second ceramic layer 30 is formed with a second conductive circuit 31, and the second conductive circuit 31 has a second pad 311. The second conductive circuit 31 is conductively connected to the first conductive circuit 11 through a second vertical conductive column 32. In this embodiment, the upper surface of the second ceramic layer 30 is concavely provided with a second embedding groove 302, and the second wire circuit 31 is located in the second embedding groove 302. The second pad 311 protrudes from the upper surface of the second ceramic layer 30, so that the second wire circuit 31 is firmly combined with the second ceramic layer 30 to prevent it from falling off, and also makes the second pad 311 more stably and reliably contacting with the second chip 40.

[0036] The second chip 40 is disposed on the upper surface of the second ceramic layer 30, and the second chip 40 is welded and connected to the second pad 311. In this embodiment, the bottom surface of the second chip 40 has a second recess 41, and the second recess 41 has a second patch solder foot 42. The second pad 311 is embedded in the second recess 41 and welded and connected to the second patch solder foot 42, so that the structure is more stable and reliable.

[0037] The third ceramic layer 50 is attached and fixed to the upper surface of the second ceramic layer 30, and the lower surface of the third ceramic layer 50 is concavely provided with a second concave cavity 501, and the second chip 40 is adapted to and located in the second concave cavity 501. The upper surface of the third ceramic layer 50 is formed with a third conductive circuit 51, and the third conductive circuit 51 has a third pad 511, and the third conductive circuit 51 is conductively connected with the second conductive circuit 31 through a third vertical conductive column 52. In this embodiment, the upper surface of the third ceramic layer 50 is concavely provided with a third embedding groove 502, and the third wire circuit 51 is located in the third embedding groove 502, and the third pad 511 protrudes from the upper surface of the third ceramic layer 50, so that the third wire circuit 51 is firmly combined with the third ceramic layer 50 to prevent falling off, and also makes the contact between the third pad 511 and the third chip 60 more stable and reliable.

[0038] The third chip 60 is disposed on the upper surface of the third ceramic layer 50, and the third chip 60 is welded and connected to the third pad 511. In this embodiment, the bottom surface of the third chip 60 has a third recess 61, and the third recess 61 has a third patch solder foot 62. The third pad 511 is embedded in the third recess 61 and is welded and connected to the third patch solder foot 62, so that the structure is more stable and reliable.

[0039] Furthermore, the lower surface of the second ceramic layer 30 is bonded and fixed to the upper surface of the first ceramic layer 10 by the first thermally conductive adhesive 71, and the first cavity 301 is filled with the first thermally conductive adhesive 71, so that the second ceramic layer 30 is firmly bonded to the first ceramic layer 10, the manufacturing is simple and easy, and the thermal conductivity is good, which greatly improves the heat dissipation performance of the first chip 20. The lower surface of the third ceramic layer 50 is bonded and fixed to the upper surface of the second ceramic layer 30 by the second thermally conductive adhesive 72, and the second cavity 501 is filled with the first thermally conductive adhesive 72, so that the third ceramic layer 50 is firmly bonded to the second ceramic layer 30, the manufacturing is simple and easy, and the thermal conductivity is good, which greatly improves the heat dissipation performance of the second chip 40.

[0040] In addition, the periphery of the first ceramic layer 10, the second ceramic layer 30 and the third ceramic layer 50 is covered with a reinforcing frame 73 to prevent the first ceramic layer 10, the second ceramic layer 30 and the third ceramic layer 50 from being easily separated, thereby effectively enhancing the overall structural strength of the product. Moreover, the reinforcing frame 73 is made of carbon fiber material, has a stable structure and is light in weight.

[0041] When in use, the external solder pad 12 is welded and connected to the external circuit. The first chip 20 is connected to the external circuit through the first conductive circuit 11, the first vertical conductive column 13 and the external solder pad 12. The second chip 40 is connected to the external circuit through the second wire circuit 31, the second vertical conductive column 32, the first conductive circuit 11, the first vertical conductive column 13 and the external solder pad 12. The third chip 60 is connected to the external circuit through the third wire circuit 51, the third vertical conductive column 52, the second wire circuit 31, the second vertical conductive column 32, the first conductive circuit 11, the first vertical conductive column 13 and the external solder pad 12. In this way, multiple chips are distributed on multi-layer circuits and are connected to external circuits, reducing the area occupied by the circuit board.

[0042] The design focus of the utility model is that a second ceramic layer is fixed on the upper surface of the first ceramic layer, and a conductive circuit is provided on each ceramic layer, so that chips can be packaged on each ceramic layer, thereby realizing three-dimensional packaging of multiple chips. When packaging multiple chips, there is no need to increase the area of ​​the ceramic packaging substrate, which is conducive to reducing the area of ​​the ceramic packaging substrate, occupying a small area, and is conducive to the development of miniaturization of equipment.

[0043] The above description is only a preferred embodiment of the present invention and does not limit the technical scope of the present invention. Therefore, any slight modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A multi-layer chip packaging substrate, comprising a first ceramic layer and a first chip; a first conductive circuit is formed on the upper surface of the first ceramic layer, and a first pad is provided on the first conductive circuit; the first chip is arranged on the upper surface of the first ceramic layer and is welded and connected to the first pad; characterized in that: An external soldering pad is formed on the lower surface of the first ceramic layer, and the external soldering pad is conductively connected to the first conductive circuit through a first vertical conductive column. A second ceramic layer is adhered and fixed to the upper surface of the first ceramic layer, and a first concave cavity is recessed on the lower surface of the second ceramic layer. The first chip is adapted to and located in the first concave cavity. A second conductive circuit is formed on the upper surface of the second ceramic layer, and a second soldering pad is provided on the second conductive circuit. The second conductive circuit is conductively connected to the first conductive circuit through a second vertical conductive column. A second chip is arranged on the upper surface of the second ceramic layer, and the second chip is conductively connected to the second soldering pad by welding.

2. The multi-layer chip packaging substrate according to claim 1, characterized in that: A third ceramic layer is bonded and fixed to the upper surface of the second ceramic layer, a second cavity is recessed on the lower surface of the third ceramic layer, the second chip is adapted to and located in the second cavity, a third conductive circuit is formed on the upper surface of the third ceramic layer, a third solder pad is provided on the third conductive circuit, the third conductive circuit is conductively connected to the second conductive circuit through a third vertical conductive column, a third chip is arranged on the upper surface of the third ceramic layer, and the third chip is soldered and conductively connected to the third solder pad.

3. The multi-layer chip packaging substrate according to claim 2, characterized in that: The lower surface of the second ceramic layer is bonded and fixed to the upper surface of the first ceramic layer by means of a first heat-conducting adhesive, and the first cavity is filled with the first heat-conducting adhesive.

4. The multi-layer chip packaging substrate according to claim 2, characterized in that: The lower surface of the third ceramic layer is bonded and fixed to the upper surface of the second ceramic layer by means of a second heat-conducting adhesive, and the second cavity is filled with the first heat-conducting adhesive.

5. The multi-layer chip packaging substrate according to claim 2, characterized in that: The peripheries of the first ceramic layer, the second ceramic layer and the third ceramic layer are covered with a reinforced frame.

6. The multi-layer chip packaging substrate according to claim 5, characterized in that: The reinforced frame is made of carbon fiber material.

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