Isolation protection circuit for level conversion of I2C burning read-write

Abstract

The utility model discloses an isolation protection circuit for level conversion of I2C (Inter-Integrated Circuit) burning read-write, which belongs to the technical field of isolation protection circuits and comprises an I2C data line level isolation circuit, an IO (Input / Output) control circuit, a step-down circuit, a switching circuit, a first interface circuit and a second interface circuit, the output end of the step-down circuit is connected with the input end of the I2C data line level isolation circuit, the output end of the I2C data line level isolation circuit is connected with the input end of the switching circuit, and the output end of the switching circuit is connected with the input end of the I2C data line level isolation circuit; according to the utility model, real-time control is carried out through IO instructions of external equipment, and high voltage of the outside and high voltage of the burning module are isolated through the IO control circuit, the switching circuit, the I2C data line isolation circuit and the voltage reduction circuit, so that the working level of a circuit board configured with an I2C protocol chip by burning read-write is prevented from being damaged by overvoltage due to level difference between an external power supply and the burning module.

Description

Technical Field

[0001] The utility model belongs to the technical field of isolation protection circuits, and in particular relates to an isolation protection circuit for level conversion of I2C burning, reading and writing. Background Art

[0002] Currently, when reading and writing I2C protocol type chips, it is necessary to directly connect the burning module interface and the I2C port or test point of the circuit board equipped with the I2C protocol chip through a data line or PCB wiring, and then read and write the I2C protocol chip on the circuit board.

[0003] However, different I2C protocol chips have different working power supplies, including 1.8V, 2.5V, 3.3V, and 5V working voltages, and the burning module is a universal working power chip. The voltage of the I2C port data line (SDA / SCL / WP) is fixed to the highest level (5V) when reading and writing, and the highest level data line is also used for reading chips with low working power. Therefore, the high-level data line is easy to cause overvoltage damage to the low-level chip and the related circuits of the chip. In order to prevent the high-level overvoltage of the burning module from damaging the low-level chip and the related circuits of the chip, an isolation protection circuit for level conversion of I2C burning, reading and writing is needed to solve the above problem. Utility Model Content

[0004] The utility model aims to provide an isolation protection circuit for level conversion of I2C burning, reading and writing, so as to solve the problems raised in the above-mentioned background technology.

[0005] To achieve the above-mentioned purpose, the utility model provides the following technical solutions: an isolation protection circuit for level conversion of I2C burning and reading and writing, comprising an I2C data line level isolation circuit, an IO control circuit, a step-down circuit, a switch circuit, a first interface circuit and a second interface circuit, the I2C data line level isolation circuit, the output end of the step-down circuit is connected to the input end of the I2C data line level isolation circuit, the output end of the I2C data line level isolation circuit is connected to the input end of the switch circuit, the output end of the switch circuit is connected to the input end of the I2C data line level isolation circuit, and the output end of the IO control circuit is connected to the input end of the switch circuit.

[0006] As a preferred implementation, the input end of the I2C data line level isolation circuit is connected to the burning module IO instruction via the I2C data line.

[0007] As a preferred implementation manner, the input end of the IO control circuit is connected to the burning module power supply in the burning module IO instruction, and the input end of the IO control circuit is connected to the multi-channel IO control port in the burning module IO instruction.

[0008] As a preferred embodiment, the step-down circuit includes IC24 chip, IC25 chip and IC26 chip, wherein pin 1 of the IC24 chip, IC25 chip and IC26 chip are all grounded, pin 2 of the IC24 chip, IC25 chip and IC26 chip are all connected to the placeholder, pin 3 of the IC24 chip is connected to pin 1 of C26, pin 1 of C27 and VDD_IO, pin 4 of the IC24 chip is respectively connected to pin 1 of C23, pin 1 of C24 and pin 2 of C25. 1 and O3V3 are connected, the C23, C24, C25, C26 and C27 are set to 10U_16V5X5R, 10U_16V5X5R, 1U_16V3X7R, 10U_16V5X5R and 1U_16V3X7R respectively, the pins 2 of the C23, C24, C25, C26 and C27 are all grounded, the pin 3 of the IC25 chip is connected to the pin 1 of C31, the pin 1 of C32 and VDD_IO, the pin 4 of the IC25 chip is connected to the pin 1 of C28 respectively, 1. Pin 1 of C29, pin 1 of C30 are connected to O1V8, C28, C29, C30, C31 and C32 are set to 10U_16V5X5R, 10U_16V5X5R, 1U_16V3X7R, 10U_16V5X5R and 1U_16V3X7R respectively, pin 2 of C28, C29, C30, C31 and C32 are all grounded, pin 3 of IC26 chip is connected to pin 1 of C36, pin 1 of C37 and VCC, and IC26 chip Pin 4 is connected to pin 1 of C33, pin 1 of C34, pin 1 of C35 and O2V5 respectively, and C33, C34, C35, C36 and C37 are set to 10U_16V5X5R, 10U_16V5X5R, 1U_16V3X7R, 10U_16V5X5R and 1U_16V3X7R respectively, and pin 2 of C28, C29, C30, C31 and C32 are all grounded, and the input end of the step-down circuit is connected to the burning module power supply in the burning module IO instruction.

[0009] As a preferred embodiment, the switch circuit includes IC27 chip, IC28 chip, IC29 chip and IC30 chip, the pin 1, pin 2 and pin 3 of the IC27 chip are respectively connected to the pin 1 of R21, C38 and R22, the pin 4 of the IC27 chip is connected to the pin 1 of C39, the pin 1 of C49 and VCC_O, the pin 2 of R21 and R22 are respectively connected to VDD_O and 3V3, the pin 2 of C38, C39 and C49 are grounded, and the R21, R22, C38, C39 and C49 are respectively set to 47OR_2J2, 4K7R_2J2, 1U_16V3X7R, 1U_1 6V3X7R and 1OU_16V5X5R, pin 1, pin 2 and pin 3 of the IC28 chip are connected to pin 1 of R23, C40 and R29 respectively, pin 4 of the IC28 chip is connected to pin 1 of C50, pin 1 of C51 and WP_O, pin 2 of R23 is connected to VDD_IO, pin 2 of R29 is grounded, pin 2 of C40, C50 and C51 are all grounded, R23, R29, C40, C50 and C51 are set to 47OR_2J2, OR_5F4, 1U_16V3X7R, 1OU_16V5X5R and 1U_16V3X7R respectively, pin 1 of the IC29 chip is connected to WP_O, pin 2 of the R23 is connected to VDD_IO, pin 2 of the R29 is grounded, pin 2 of the C40, C50 and C51 are all grounded, R23, R29, C40, C50 and C51 are set to 47OR_2J2, OR_5F4, 1U_16V3X7R, 1OU_16V5X5R and 1U_16V3X7R respectively, pin 2 of the IC29 chip is connected to WP_O, pin 1 of the C50, C51 is connected to WP_O, pin 2 of the R23 is connected to VDD_IO, pin 2 of the R29 is grounded, pin 2 of the C40, C50 and C51 are all grounded, R23, R29, C40, C50 and C51 are set to 47OR_2J2, OR_5F4, 1U_16V3X7R, 1OU_16V5X5R and 1U_16V3X7R respectively, pin 1, pin 2 and pin 3 are connected to pin 1 of R25, C42 and R26 respectively, pin 4 of the IC29 chip is connected to pin 1 of C54, pin 1 of C55 and SCL_O, pin 2 of R25 and R26 are connected to VDD_IO and 1V8 respectively, pin 2 of C42, C54 and C55 are grounded, R25, R26, C42, C54 and C55 are set to 47OR_2J2, 4K7R_2J2, 1U_16V3X7R, 1OU_16V5X5R and 1U_16V3X7R respectively, pin 1, pin 2 and pin 3 of the IC30 chip are connected to pin 1 of R27, C44 and R28 respectively The IC30 chip is connected to the pin 1 of C52, the pin 1 of C53 and SDA_O, the pin 2 of R27 and R28 are connected to VDD_IO and 1V8 respectively, the pin 2 of C44, C52 and C53 are all grounded, the R27, R28, C44, C52 and C53 are set to 47OR_2J2, 4K7R_2J2, 1U_16V3X7R, 1OU_16V5X5R and 1U_16V3X7R respectively, the output end of the switch circuit is connected to the circuit board configured with the I2C protocol chip through the I2C data line output, and the I2C data line input and the I2C data line output are set to SDA, SCL and WP.

[0010] As a preferred implementation, the IC24 chip, the IC25 chip and the IC26 chip are all configured as LDO1 chips.

[0011] As a preferred implementation, the IC27 chip, IC28 chip, IC29 chip and IC30 chip are all configured as KAQY212 chips.

[0012] As a preferred implementation, the IO control circuit includes an IC23 chip and F1, wherein the pin 1 of the F1 is respectively connected to VCC_IO_IN and the pin Z of DT1, the pin P of the DT1 is grounded, the pin 2 of the F1 is respectively connected to the pin 1 of C58, the pin 1 of C59, the pin 1 of C60 and VCC_IO, the pins 2 of C58, C59 and C60 are all grounded, the C58, C59 and C60 are respectively set to 1OU_16V5X5R, 1OU_16V5X5R and 1U_16V3X7R, and the pins 1, 2, 3, 4, 5, 6, 7 and 8 are connected to IO1, IO2, IO3, IO4, IO5, IO6, IO7 and IO8 respectively, pin 10 of the IC23 chip is connected to pin 1 of C56, pin 1 of C57 and VDD_IO, pin 2 of C56 and pin 2 of C57 are both grounded, pins 11, 12, 13, 14 and 15 of the IC23 chip are all connected to placeholders, pins 16, 17 and 18 of the IC23 chip are connected to VCC, IC and WP respectively, pin 19 of the IC23 chip is grounded, and the IC23 chip is set to be a ULN2803A chip.

[0013] As a preferred embodiment, the isolation circuit includes an IC31 chip, pin 1 of the IC31 chip is connected to pin 1 of R30, pin 2 of the R30 is connected to 1V8, pin 2 and pin 3 of the IC31 chip are connected to 1V8_1 and 1V8_2 respectively, pins 4, 5, 6, 10 and 11 of the IC31 chip are connected to placeholders, pins 7 and 15 of the IC31 chip are grounded, pins 8 and 9 of the IC31 chip are connected to pin 1 of C46, ​​C47, C48, R31 and R32, pin 2 of C46, ​​C47 and C48 are grounded, pin 2 of R31 and R32 are connected to 3V3 and VDD_IO respectively, pins 12, 13 and 14 of the IC31 chip are connected to SDA, SCL and VCC_O respectively, and the IC31 is set as an IC4 chip.

[0014] As a preferred embodiment, the first interface circuit includes a U2 chip, pins 1, 2, 3, 4, 5, 6, 7, 8 and 9 of the U2 chip are connected to VCC_IO_IN, IO1, IO2, IO3, IO4, IO5, IO6, IO7 and IO8 respectively, pins 10, 13 and 36 of the U2 chip are grounded, pins 11, 12, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 and 28 of the U2 chip are connected to placeholders, pins 29, 31, 33, 35 and 36 of the U2 chip are grounded, pins 37, 38, 39 and 40 of the U2 chip are connected to VDD, pins 30, 32 and 34 of the U2 chip are connected to SDA, SCL and WP respectively. The U2 chip is set to be a CON1 chip, the second interface circuit includes a CON5 chip, R18, R19 and R20, pins 1, 3 and 5 of the CON5 chip are respectively connected to WP_O, SCL_O and SDA_O, pins 11 and 12 of the CON5 chip are both connected to VDD, pins 13 and 14 of the CON5 chip are both connected to BN, pins 15 and 16 of the CON5 chip are both connected to PVM, pins 2, 4, 6, 7 and 8 of the CON5 chip are all grounded, pins 9 and 10 of the CON5 chip are both connected to the placeholder, pins 1 of the R19 and R20 are connected to VDD, pin 2 of the VDD is respectively connected to VDD_O and BN, pin 1 of the R18 is connected to 2V5O, and pin 2 of the R18 is connected to PVM.

[0015] Compared with the prior art, the beneficial effects of the utility model are:

[0016] The utility model is provided with an I2C data line level isolation circuit, an IO control circuit, a voltage reduction circuit and a switch circuit, and performs real-time control through an external device IO instruction, and isolates the high voltage of the external and the burning module through the IO control circuit, the switch circuit, the I2C data line isolation circuit and the voltage reduction circuit. When the burning module performs a read and write operation on an I2C chip of the same level, the isolation protection circuit can isolate the external abnormally large voltage, and when the burning module performs a read and write operation on an I2C chip of a low level, the isolation protection circuit can convert the level of the I2C data line, so that the working level of the circuit board configured with the I2C protocol chip for the burning read and write operation is not damaged by overvoltage due to the level difference between the external power supply and the burning module. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a block diagram of the isolation protection circuit of the utility model;

[0018] Figure 2 This is a step-down circuit diagram of the utility model;

[0019] Figure 3 This is a switch circuit diagram of the utility model;

[0020] Figure 4 This is the isolation circuit diagram of the utility model;

[0021] Figure 5 This is the IO control circuit diagram of the utility model;

[0022] Figure 6 This is a circuit diagram of the first interface of the utility model;

[0023] Figure 7 This is a circuit diagram of the second interface of the utility model. DETAILED DESCRIPTION

[0024] The present invention will be further described below in conjunction with the embodiments.

[0025] The following examples are used to illustrate the present invention, but cannot be used to limit the scope of protection of the present invention. The conditions in the examples can be further adjusted according to specific conditions, and simple improvements to the method of the present invention under the premise of the concept of the present invention are all within the scope of protection claimed by the present invention.

[0026] See also Figure 1-7 The utility model provides an isolation protection circuit for level conversion of I2C burning, reading and writing, including an I2C data line level isolation circuit, an IO control circuit, a step-down circuit, a switch circuit, a first interface circuit and a second interface circuit. The I2C data line level isolation circuit, the output end of the step-down circuit is connected to the input end of the I2C data line level isolation circuit, the output end of the I2C data line level isolation circuit is connected to the input end of the switch circuit, the output end of the switch circuit is connected to the input end of the I2C data line level isolation circuit, the output end of the IO control circuit is connected to the input end of the switch circuit, the input end of the I2C data line level isolation circuit is connected to the burning module IO instruction through the I2C data line, the input end of the IO control circuit is connected to the burning module power supply in the burning module IO instruction, and by setting the burning module power supply, the burning module power supply can provide power for the step-down circuit and the I2C data line level isolation circuit;

[0027] The input end of the IO control circuit is connected to the multi-channel IO control port in the IO instruction of the burning module, and the input end of the step-down circuit is connected to the burning module power supply in the IO instruction of the burning module. By setting the IO instruction of the burning module, the burning module can control the rhythm and timing of burning, reading and writing in real time according to the operation requirements through the IO instruction;

[0028] The output end of the switch circuit is connected to a circuit board configured with an I2C protocol chip through an I2C data line output, and both the I2C data line input and the I2C data line output are set to SDA, SCL and WP.

[0029] The step-down circuit includes IC24, IC25 and IC26 chips. IC24, IC25 and IC26 chips are all set as LDO1 chips. Pin 1 of IC24, IC25 and IC26 chips are all grounded. Pin 2 of IC24, IC25 and IC26 chips are all connected to the placeholder. Pin 3 of IC24 chip is connected to pin 1 of C26, pin 1 of C27 and VDD_IO. Pin 4 of IC24 chip is connected to pin 1 of C23, pin 1 of C24 and pin 2 of C25 respectively. Pin 1 is connected to O3V3, C23, C24, C25, C26 and C27 are set to 10U_16V5X5R, 10U_16V5X5R, 1U_16V3X7R, 10U_16V5X5R and 1U_16V3X7R respectively, Pin 2 of C23, C24, C25, C26 and C27 are all grounded, Pin 3 of IC25 chip is connected to Pin 1 of C31, Pin 1 of C32 and VDD_IO, Pin 4 of IC25 chip is connected to Pin 1 of C28, Pin 1 of C29, Pin 1 of C30 respectively 1 and O1V8, C28, C29, C30, C31 and C32 are set to 10U_16V5X5R, 10U_16V5X5R, 1U_16V3X7R, 10U_16V5X5R and 1U_16V3X7R respectively, pin 2 of C28, C29, C30, C31 and C32 are all grounded, pin 3 of IC26 chip is connected to pin 1 of C36, pin 1 of C37 and VCC, pin 4 of IC26 chip is connected to pin 1 of C33, pin 1 of C34, pin 1 of C35 and O2V respectively 5 connections, C33, C34, C35, C36 and C37 are set to 10U_16V5X5R, 10U_16V5X5R, 1U_16V3X7R, 10U_16V5X5R and 1U_16V3X7R respectively, and pin 2 of C28, C29, C30, C31 and C32 are all grounded. By setting a step-down circuit, the step-down circuit can isolate the high voltage of the external and the burning module, so that the working level of the I2C protocol chip circuit board configured during burning and reading will not be damaged due to the overvoltage of the level difference between the external power supply and the burning module.

[0030] The switch circuit includes IC27 chip, IC28 chip, IC29 chip and IC30 chip. IC27 chip, IC28 chip, IC29 chip and IC30 chip are all set to KAQY212 chip. Pin 1, pin 2 and pin 3 of IC27 chip are respectively connected to pin 1 of R21, C38 and R22, pin 4 of IC27 chip is connected to pin 1 of C39, pin 1 of C49 and VCC_O, pin 2 of R21 and R22 are respectively connected to VDD_O and 3V3, pin 2 of C38, C39 and C49 are all grounded, and R21, R22, C38, C39 and C49 are respectively set to 47OR_2J2, 4K7R_2J2, 1U_16 V3X7R, 1U_16V3X7R and 1OU_16V5X5R, pin 1, pin 2 and pin 3 of IC28 chip are connected to pin 1 of R23, C40 and R29 respectively, pin 4 of IC28 chip is connected to pin 1 of C50, pin 1 of C51 and WP_O, pin 2 of R23 is connected to VDD_IO, pin 2 of R29 is grounded, pin 2 of C40, C50 and C51 are all grounded, R23, R29, C40, C50 and C51 are set to 47OR_2J2, OR_5F4, 1U_16V3X7R, 1OU_16V5X5R and 1U_16V3X7R respectively, pin 1, pin 2 and pin 3 of IC29 chip are ... The pins 1, 2 and 3 of IC30 are connected to R27, C44 and R28 respectively. The pin 4 of IC30 is connected to the pin 1 of C52, the pin 1 of C53 and SCL_O respectively. The pins 2 of R25 and R26 are connected to VDD_IO and 1V8 respectively. The pins 2 of C42, C54 and C55 are grounded. R25, R26, C42, C54 and C55 are set to 47OR_2J2, 4K7R_2J2, 1U_16V3X7R, 1OU_16V5X5R and 1U_16V3X7R respectively. The pins 1, 2 and 3 of IC30 are connected to R27, C44 and R28 respectively. The pin 4 of IC30 is connected to the pin 1 of C52, the pin 1 of C53 and the pin 2 of C54. Pin 1 is connected to SDA_O, pin 2 of R27 and R28 is connected to VDD_IO and 1V8 respectively, pin 2 of C44, C52 and C53 are all grounded, R27, R28, C44, C52 and C53 are set to 47OR_2J2, 4K7R_2J2, 1U_16V3X7R, 1OU_16V5X5R and 1U_16V3X7R respectively. By setting the switching circuit, the switching circuit can output instructions to various circuit boards configured with the I2C protocol chip through the I2C data lines SDA, SCL, WP. The switching circuit can control the switching state of the I2C data line level isolation circuit. When in the closed state, the I2C data lines SDA, SCL, WP cannot be output.

[0031] The IO control circuit includes IC23 chip and F1. The IC23 chip is set to ULN2803A chip. Pin 1 of F1 is respectively connected to VCC_IO_IN and pin Z of DT1, pin P of DT1 is grounded, pin 2 of F1 is respectively connected to pin 1 of C58, pin 1 of C59, pin 1 of C60 and VCC_IO, pin 2 of C58, C59 and C60 are all grounded, C58, C59 and C60 are respectively set to 1OU_16V5X5R, 1OU_16V5X5R and 1U_16V3X7R, and pins 1, 2, 3, 4, 5, 6, 7 and 8 of the IC23 chip are respectively connected to IO1, IO2, IO3, IO4, IO5, IO6, IO7 and IO8 Connection, pin 10 of IC23 chip is connected to pin 1 of C56, pin 1 of C57 and VDD_IO, pin 2 of C56 and pin 2 of C57 are both grounded, pins 11, 12, 13, 14 and 15 of IC23 chip are all connected to placeholders, pins 16, 17 and 18 of IC23 chip are connected to VCC, IC and WP respectively, pin 19 of IC23 chip is grounded, by setting up IO control circuit, IO control circuit uses a Darlington transistor array (ULN2803A) for IO control, IO control circuit can control the opening and closing of switch circuit, IO control circuit can receive IO instruction of burning module transmitted by multiple IO control ports, circuit is simple, reliable and low price.

[0032] The isolation circuit includes an IC31 chip, which is set as an IC4 chip. Pin 1 of the IC31 chip is connected to pin 1 of R30, pin 2 of R30 is connected to 1V8, pin 2 and pin 3 of the IC31 chip are connected to 1V8_1 and 1V8_2 respectively, pins 4, 5, 6, 10 and 11 of the IC31 chip are all connected to placeholders, pins 7 and 15 of the IC31 chip are grounded, pins 8 and 9 of the IC31 chip are connected to pin 1 of C46, ​​C47, C48, R31 and R32, pin 2 of C46, ​​C47 and C48 is grounded, pin 2 of R31 and R32 is connected to 3V3 and VDD_IO respectively, pins 12, 13 and 14 of the IC31 chip are connected to SDA, SCL and VCC_O respectively, and an isolation circuit is set up. The isolation circuit adopts a 4-bit bidirectional multi-voltage level converter (TXS0104E) for main data line level isolation.

[0033] The first interface circuit includes a U2 chip, which is set to a CON1 chip. Pins 1, 2, 3, 4, 5, 6, 7, 8 and 9 of the U2 chip are connected to VCC_IO_IN, IO1, IO2, IO3, IO4, IO5, IO6, IO7 and IO8 respectively, pins 10, 13 and 36 of the U2 chip are grounded, pins 11, 12, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 and 28 of the U2 chip are connected to placeholders, pins 29, 31, 33, 35 and 36 of the U2 chip are grounded, pins 37, 38, 39 and 40 of the U2 chip are connected to VDD, and pins 30, 32 and 34 of the U2 chip are connected to SDA, SCL and WP respectively. By setting the first interface circuit, the first interface circuit is used for external instruments or devices.

[0034] The second interface circuit includes a CON5 chip, R18, R19 and R20. Pins 1, 3 and 5 of the CON5 chip are connected to WP_O, SCL_O and SDA_O respectively. Pins 11 and 12 of the CON5 chip are connected to VDD. Pins 13 and 14 of the CON5 chip are connected to BN. Pins 15 and 16 of the CON5 chip are connected to PVM. Pins 2, 4, 6, 7 and 8 of the CON5 chip are grounded. Pins 9 and 10 of the CON5 chip are connected to placeholders. Pin 1 of R19 and R20 is connected to VDD. Pin 2 of VDD is connected to VDD_O and BN respectively. Pin 1 of R18 is connected to 2V5O. Pin 2 of R18 is connected to PVM. By setting the second interface circuit, the second interface circuit is an output interface for connecting the back-end load to be tested.

[0035] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An isolation protection circuit for level conversion of I2C burning, reading and writing, comprising an I2C data line level isolation circuit, an IO control circuit, a step-down circuit, a switch circuit, a first interface circuit and a second interface circuit, characterized in that: The I2C data line level isolation circuit, the output end of the step-down circuit is connected to the input end of the I2C data line level isolation circuit, the output end of the I2C data line level isolation circuit is connected to the input end of the switch circuit, the output end of the switch circuit is connected to the input end of the I2C data line level isolation circuit, and the output end of the IO control circuit is connected to the input end of the switch circuit.

2. The isolation protection circuit for level conversion of I2C burning, reading and writing according to claim 1 is characterized in that: The input end of the I2C data line level isolation circuit is connected to the burning module IO instruction through the I2C data line.

3. The isolation protection circuit for level conversion of I2C burning, reading and writing according to claim 1 is characterized in that: The input end of the IO control circuit is connected to the burning module power supply in the burning module IO instruction, and the input end of the IO control circuit is connected to the multi-channel IO control port in the burning module IO instruction.

4. The isolation protection circuit for level conversion of I2C burning, reading and writing according to claim 1 is characterized in that: The step-down circuit includes IC24 chip, IC25 chip and IC26 chip, wherein pin 1 of the IC24 chip, IC25 chip and IC26 chip are all grounded, pin 2 of the IC24 chip, IC25 chip and IC26 chip are all connected to the placeholder, pin 3 of the IC24 chip is connected to pin 1 of C26, pin 1 of C27 and VDD_IO, pin 4 of the IC24 chip is respectively connected to pin 1 of C23, pin 1 of C24, pin 1 of C25 and O3V3, The C23, C24, C25, C26 and C27 are set to 10U_16V5X5R, 10U_16V5X5R, 1U_16V3X7R, 10U_16V5X5R and 1U_16V3X7R respectively, the pins 2 of the C23, C24, C25, C26 and C27 are all grounded, the pin 3 of the IC25 chip is connected to the pin 1 of C31, the pin 1 of C32 and VDD_IO, the pin 4 of the IC25 chip is connected to the pin 1 of C28, the pin 2 of C29 and VDD_IO respectively. Pin 1 of C30 is connected to O1V8, C28, C29, C30, C31 and C32 are set to 10U_16V5X5R, 10U_16V5X5R, 1U_16V3X7R, 10U_16V5X5R and 1U_16V3X7R respectively, pin 2 of C28, C29, C30, C31 and C32 are all grounded, pin 3 of IC26 chip is connected to pin 1 of C36, pin 1 of C37 and VCC, pin 2 of IC26 chip is connected to VCC, pin 3 of IC26 chip is connected to VCC, pin 1 of IC26 chip is connected to VCC, pin 2 of IC26 chip is connected to VCC, pin 1 of IC26 chip is connected to VCC, pin 2 of IC26 chip is connected to VCC, pin 2 of IC26 chip is connected to VCC, pin 1 of C36 is connected to VCC, pin 1 of C37 is connected to VCC, pin 2 of IC26 chip is connected to VCC, pin 2 of C ... 4 are respectively connected to pin 1 of C33, pin 1 of C34, pin 1 of C35 and O2V5, and the C33, C34, C35, C36 and C37 are set to 10U_16V5X5R, 10U_16V5X5R, 1U_16V3X7R, 10U_16V5X5R and 1U_16V3X7R respectively, and the pin 2 of C28, C29, C30, C31 and C32 are all grounded, and the input end of the step-down circuit is connected to the burning module power supply in the burning module IO instruction.

5. The isolation protection circuit for level conversion of I2C burning, reading and writing according to claim 1 is characterized in that: The switch circuit comprises IC27 chip, IC28 chip, IC29 chip and IC30 chip, wherein pin 1, pin 2 and pin 3 of the IC27 chip are respectively connected to pin 1 of R21, C38 and R22, pin 4 of the IC27 chip is connected to pin 1 of C39, pin 1 of C49 and VCC_O, pin 2 of R21 and R22 are respectively connected to VDD_O and 3V3, pin 2 of C38, C39 and C49 are all grounded, and R21, R22, C38, C39 and C49 are respectively set to 47OR_2J2, 4K7R_2J2, 1U_16V3X7R, 1U_16V3X7R and 1O U_16V5X5R, pin 1, pin 2 and pin 3 of the IC28 chip are connected to pin 1 of R23, C40 and R29 respectively, pin 4 of the IC28 chip is connected to pin 1 of C50, pin 1 of C51 and WP_O, pin 2 of R23 is connected to VDD_IO, pin 2 of R29 is grounded, pin 2 of C40, C50 and C51 are all grounded, R23, R29, C40, C50 and C51 are set to 47OR_2J2, OR_5F4, 1U_16V3X7R, 1OU_16V5X5R and 1U_16V3X7R respectively, pin 1, pin 2 and Pin 3 is connected to pin 1 of R25, C42 and R26 respectively, pin 4 of the IC29 chip is connected to pin 1 of C54, pin 1 of C55 and SCL_O, pin 2 of R25 and R26 is connected to VDD_IO and 1V8 respectively, pin 2 of C42, C54 and C55 is grounded, R25, R26, C42, C54 and C55 are set to 47OR_2J2, 4K7R_2J2, 1U_16V3X7R, 1OU_16V5X5R and 1U_16V3X7R respectively, pin 1, pin 2 and pin 3 of the IC30 chip are connected to pin 1 of R27, C44 and R28 respectively, Pin 4 of the IC30 chip is connected to pin 1 of C52, pin 1 of C53 and SDA_O, pin 2 of the R27 and R28 are connected to VDD_IO and 1V8 respectively, pin 2 of the C44, C52 and C53 are all grounded, and the R27, R28, C44, C52 and C53 are set to 47OR_2J2, 4K7R_2J2, 1U_16V3X7R, 1OU_16V5X5R and 1U_16V3X7R respectively. The output end of the switching circuit is connected to the circuit board configured with the I2C protocol chip through the I2C data line output, and the I2C data line input and the I2C data line output are set to SDA, SCL and WP.

6. The isolation protection circuit for level conversion of I2C burning, reading and writing according to claim 4 is characterized in that: The IC24 chip, the IC25 chip and the IC26 chip are all configured as LDO1 chips.

7. The isolation protection circuit for level conversion of I2C burning, reading and writing according to claim 5, characterized in that: The IC27 chip, IC28 chip, IC29 chip and IC30 chip are all set as KAQY212 chips.

8. The isolation protection circuit for level conversion of I2C burning, reading and writing according to claim 1, characterized in that: The IO control circuit includes an IC23 chip and F1, wherein the pin 1 of the F1 is connected to VCC_IO_IN and the pin Z of DT1 respectively, the pin P of the DT1 is grounded, the pin 2 of the F1 is connected to the pin 1 of C58, the pin 1 of C59, the pin 1 of C60 and VCC_IO respectively, the pin 2 of C58, C59 and C60 are all grounded, the C58, C59 and C60 are set to 1OU_16V5X5R, 1OU_16V5X5R and 1U_16V3X7R respectively, the pins 1, 2, 3, 4, 5, 6, 7 and 8 are connected to IO1, IO2, IO3, IO4, IO5, IO6, IO7 and IO8 respectively, pin 10 of the IC23 chip is connected to pin 1 of C56, pin 1 of C57 and VDD_IO, pin 2 of C56 and pin 2 of C57 are both grounded, pins 11, 12, 13, 14 and 15 of the IC23 chip are all connected to placeholders, pins 16, 17 and 18 of the IC23 chip are connected to VCC, IC and WP respectively, pin 19 of the IC23 chip is grounded, and the IC23 chip is set to be a ULN2803A chip.

9. The isolation protection circuit for level conversion of I2C burning, reading and writing according to claim 1, characterized in that: The isolation circuit includes an IC31 chip, pin 1 of the IC31 chip is connected to pin 1 of R30, pin 2 of the R30 is connected to 1V8, pin 2 and pin 3 of the IC31 chip are connected to 1V8_1 and 1V8_2 respectively, pins 4, 5, 6, 10 and 11 of the IC31 chip are all connected to placeholders, pins 7 and 15 of the IC31 chip are both grounded, pins 8 and 9 of the IC31 chip are both connected to pin 1 of C46, ​​C47, C48, R31 and R32, pin 2 of C46, ​​C47 and C48 are both grounded, pin 2 of R31 and R32 are respectively connected to 3V3 and VDD_IO, pins 12, 13 and 14 of the IC31 chip are respectively connected to SDA, SCL and VCC_O, and the IC31 is set to be an IC4 chip.

10. The level conversion isolation protection circuit for I2C burning, reading and writing according to claim 1, characterized in that: The first interface circuit includes a U2 chip, wherein pins 1, 2, 3, 4, 5, 6, 7, 8 and 9 of the U2 chip are connected to VCC_IO_IN, IO1, IO2, IO3, IO4, IO5, IO6, IO7 and IO8 respectively, pins 10, 13 and 36 of the U2 chip are grounded, pins 11, 12, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 and 28 of the U2 chip are connected to placeholders, pins 29, 31, 33, 35 and 36 of the U2 chip are grounded, pins 37, 38, 39 and 40 of the U2 chip are connected to VDD, pins 30, 32 and 34 of the U2 chip are connected to SDA, SCL and WP respectively, and the U2 The chip is set to be a CON1 chip, and the second interface circuit includes a CON5 chip, R18, R19 and R20, pins 1, 3 and 5 of the CON5 chip are respectively connected to WP_O, SCL_O and SDA_O, pins 11 and 12 of the CON5 chip are both connected to VDD, pins 13 and 14 of the CON5 chip are both connected to BN, pins 15 and 16 of the CON5 chip are both connected to PVM, pins 2, 4, 6, 7 and 8 of the CON5 chip are all grounded, pins 9 and 10 of the CON5 chip are both connected to placeholders, pins 1 of the R19 and R20 are connected to VDD, pin 2 of the VDD is respectively connected to VDD_O and BN, pin 1 of the R18 is connected to 2V5O, and pin 2 of the R18 is connected to PVM.

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