Semiconductor device and semiconductor circuit

Abstract

The present disclosure provides a semiconductor device and a semiconductor circuit. The semiconductor device includes a level conversion circuit and a bias generation circuit. The level conversion circuit is configured to generate an output voltage in a second voltage domain corresponding to an input signal in a first voltage domain, wherein the level conversion circuit includes at least a thick oxide transistor and a thin oxide transistor. The bias voltage generation circuit is effectively coupled to the level conversion circuit and is used for generating a bias voltage, and the bias voltage is substantially higher than the voltage of the input signal; and providing a bias voltage to the gate of the thick oxide transistor, thereby enabling the level conversion circuit to generate an output voltage.

Description

Technical Field

[0001] The present disclosure relates to a level shifter technology, and more particularly to a semiconductor device and a semiconductor circuit for implementing a level shifter with an internal self-protection high bias voltage generator. Background Art

[0002] The semiconductor industry has experienced rapid growth due to a series of improvements in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. The improvement in integration density comes primarily from the continuous reduction in the size of the smallest feature, which allows more components to be integrated into a given area. Utility Model Content

[0003] The present disclosure provides a semiconductor device, comprising a level conversion circuit and a bias generation circuit. The level conversion circuit is used to generate an output voltage in a second voltage domain corresponding to an input signal in a first voltage domain, wherein the level conversion circuit comprises at least a thick oxide transistor and a thin oxide transistor. The bias generation circuit is operatively coupled to the level conversion circuit and is used to: generate a bias voltage substantially higher than the voltage of the input signal; and provide the bias voltage to a gate of the thick oxide transistor, so that the level conversion circuit generates an output voltage.

[0004] The present disclosure provides a semiconductor circuit, comprising a first capacitor, a second capacitor, a first N-type metal oxide semiconductor (NMOS) transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The first capacitor has a first terminal coupled to a first signal. The second capacitor has a first terminal coupled to a source of a logic inversion signal of the first signal. The gate of the first NMOS transistor is coupled to a source voltage of the second NMOS transistor, the gate of the second NMOS transistor is coupled to a source voltage of the first NMOS transistor, the drain of the first NMOS transistor and the drain of the second NMOS transistor are coupled to a power supply voltage. The gate and drain of the third NMOS transistor and the gate and drain of the fourth NMOS transistor are coupled to a power supply voltage, the source of the first NMOS transistor and the source of the third NMOS transistor are each coupled to a voltage at a second terminal of the first capacitor, and the source of the second NMOS transistor and the source of the fourth NMOS transistor are each coupled to a voltage at a second terminal of the second capacitor. In response to the first signal being in a first logic state, the semiconductor circuit generates a bias output voltage at the second terminal of the second capacitor or at the second terminal of the first capacitor.

[0005] The present disclosure provides a semiconductor device, including a level conversion circuit and a bias generation circuit. The level conversion circuit includes a protection transistor. The bias generation circuit is coupled to the level conversion circuit, wherein the bias generation circuit is used to: receive an input signal corresponding to a first voltage source; generate a bias voltage based on the input signal and using the first voltage source; and provide the bias voltage to the protection transistor of the level conversion circuit. The level conversion circuit is electrically coupled to a second voltage source having a second voltage, the second voltage being greater than the first voltage of the first voltage source, and the level conversion circuit is used to generate an output voltage based on the bias voltage, the bias voltage being the second voltage or the ground voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the embodiments of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic block diagram of a level converter with a self-protected high bias voltage generator circuit, according to some embodiments;

[0008] Figure 2 for Figure 1 A waveform diagram of a voltage signal of a circuit in response to a high input voltage signal, which is illustrated according to some embodiments of the present disclosure;

[0009] Figure 3 for Figure 1 A waveform diagram of a voltage signal of a circuit in response to a low input voltage signal, which is illustrated according to some embodiments of the present disclosure;

[0010] Figure 4 A circuit diagram of an example self-protection bias circuit driving transistor of a level shifting circuit is shown according to some embodiments of the present disclosure;

[0011] Figure 5 A circuit diagram of an example self-protection bias circuit driving a transistor for a level shifting circuit that generates a logic-inverted output signal, according to some embodiments of the present disclosure; and

[0012] Figure 6 A flow chart of an example method for operating a level shifter with a self-protection bias circuit is shown according to some embodiments of the present disclosure.

[0013]

Explanation of symbols

[0014] 100: Level converter

[0015] 102: Self-protection high bias generator circuit

[0016] 104: Pull-up device

[0017] 106: Pull-up device

[0018] 108: First protection device

[0019] 110: Second protection device

[0020] 112: First pull-down device

[0021] 114: Second pull-down device

[0022] 116:OUTB node

[0023] 118:OUT node

[0024] 200,300: Waveform

[0025] 400: Circuit Diagram

[0026] 402: Example Self-Protection Bias Generator Circuit

[0027] 403: Level converter circuit

[0028] 404: first inverter

[0029] 406: Second inverter

[0030] 407: INB node

[0031] 408,410:Capacitor

[0032] 409:INI node

[0033] 412:IN_HV node

[0034] 414:INB_HV node

[0035] 416:OUTB node

[0036] 418:OUT node

[0037] 500: Circuit Diagram

[0038] 502: Example Self-Protection Bias Generator Circuit

[0039] 503: Level converter circuit

[0040] 504: first inverter

[0041] 506: Second inverter

[0042] 507,509: Node

[0043] 508,510:Capacitor

[0044] 512: INB_HV node

[0045] 514:IN_HV node

[0046] 516:OUTB node

[0047] 518:OUT node

[0048] 600: Method

[0049] 602,604,606,608: Operation

[0050] IN: Input signal

[0051] IN_HV, INB_HV: output voltage signal

[0052] INB, INI: output signal

[0053] M1~M20: Transistor

[0054] t0,t1: time

[0055] V1, V2: power supply voltage

[0056] V3: Bias voltage DETAILED DESCRIPTION

[0057] The following disclosure provides many different embodiments or examples to implement the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be directly contacted. In addition, the embodiments of the present disclosure may repeat element symbols and / or letters in each example. This repetition is for simplification and clarity purposes, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0058] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly accordingly.

[0059] Level shifting circuits are electronic circuits that generate an output signal that is proportional to an input signal. For example, such circuits can be used to drive components or circuits that operate at different voltage levels. In a typical level shifting circuit, the gate of a field effect transistor or other type of transistor can be driven in part by an input signal, which causes the transistor to turn a secondary voltage source on or off to generate an output signal. The secondary voltage source can be greater or less than the voltage source used to drive the input signal. However, due to the reduction in minimum feature size, driving the gate of a transistor (e.g., a thick oxide transistor) that is suitable for controlling a higher voltage to generate a reliable output signal will be challenging.

[0060] The present disclosure provides various embodiments of a level shifting system including a self-protection bias generator circuit capable of generating an amplified signal to drive a protection transistor integrated in the level shifter circuit. The protection transistor may be a thick oxide device that protects other thin oxide pull-down transistors that may be included in a typical level shifting circuit. By protecting the thin oxide transistor, the level shifting circuit may be fabricated with an ideal ratio of output voltage to input voltage and prevent instances of device failure or device malfunction.

[0061] Figure 1 A schematic block diagram of a level shifter 100 with a self-protected high bias voltage generator circuit 102 is shown according to some embodiments. A level shifter is a circuit that can be used to shift a signal from a first voltage level to a second voltage level. Generally, a level shifter receives an input signal at a first voltage level and generates an output voltage at a second voltage level with the same or opposite logic polarity. In some embodiments, the level shifter can be part of a larger integrated circuit device that includes other circuits with functionality other than a memory device.

[0062] The level converter 100 includes a pull-up device 104 and a pull-up device 106. The pull-up device 104 and the pull-up device 106 may each be a transistor electrically coupled to a power supply voltage V2, or each include a transistor electrically coupled to a power supply voltage V2. Figure 1 As shown, different terminals of the pull-up device 104 and the pull-up device 106 can be coupled to the OUTB node 116 and the OUT node 118. Other details of the pull-up device 104 and the pull-up device 106 will be combined with Figure 4 and Figure 5In one embodiment, the OUT node 118 can provide a level-shifted output voltage (e.g., pulled up to the supply voltage V2) to one or more other circuits or components of the integrated circuit. In one embodiment, the OUTB node 116 can provide a level-shifted output voltage pulled up to the supply voltage V2 with an opposite logic polarity (e.g., an opposite logic state).

[0063] The level converter 100 includes a first protection device 108 and a first pull-down device 112. The first protection device 108 and the first pull-down device 112 may each be a transistor, or each include a transistor. Figure 1 As shown, the protection device 108 is electrically coupled to the OUTB node 116 and the first pull-down device 112. The first pull-down device 112 is electrically coupled to the protection device 108 and the ground voltage. The voltage at the OUTB node 116 can be partially controlled by the first pull-up device 104, the first protection device 108, and the first pull-down device 112. The first protection device 108 and the first pull-down device 112 can be coupled in series. The second protection device 110 and the second pull-down device 114 can be coupled in series.

[0064] The level converter 100 includes a second protection device 110 and a second pull-down device 114. The second protection device 110 and the second pull-down device 114 may each be a transistor, or each include a transistor. Figure 1 As shown, the second protection device 110 is electrically coupled to the OUT node 118 and the second pull-down device 114. The second pull-down device 114 is electrically coupled to the protection device 110 and the ground voltage. The voltage at the OUT node 118 can be partially controlled by the second pull-up device 106, the second protection device 110, and the second pull-down device 114. In the level converter 100, the first pull-up device 104 and the second pull-up device 106 can be cross-coupled. Figure 1 As shown, at least one terminal (eg, gate terminal) of the first pull-up device 104 is connected to the OUT node 118 , and at least one terminal (eg, gate terminal) of the second pull-up device 106 is connected to the OUTB node 116 .

[0065] The first protection device 108 and the second protection device 110 can each be at least partially controlled by the self-protection bias generator circuit 102. The first protection device 108 and the second protection device 110 can be thick gate oxide transistors, or include thick gate oxide transistors. Compared to other types of transistors described in this disclosure, thick gate oxide transistors can be activated in response to relatively high gate voltages. In order to withstand relatively high voltages without gate oxide breakdown, such transistors are formed as transistors with relatively thick gate oxides, such as gate oxides with a thickness greater than about 50 angstroms and a relatively long channel length (for example, about twice the length of a thin oxide transistor). Therefore, the transistors described in this disclosure that can withstand relatively high voltages and have relatively thick gate oxides may be referred to as "thick oxide transistors" or "thick oxide field effect transistors (FETs)" in this disclosure. The first protection device 108 and the second pull-down device 110 can be thick oxide transistors, or include thick oxide transistors.

[0066] Certain logic transistors are examples of the second type of transistor that are designed to operate in a lower voltage environment (such as 1.1 volts). Because the voltage applied to the transistor is lower than the voltage applied to the thick oxide transistor, the gate oxide of the logic transistor does not need to be as thick as the gate oxide of the thick oxide device. For example, the gate oxide thickness of a typical logic transistor may be about 10 to 12 angstroms, and the channel length may be short (e.g., at a minimum specified lithography dimension). Therefore, the second type of transistor that can withstand relatively low voltages and has a relatively thin gate oxide may be referred to as a "thin oxide transistor" or "thin oxide FET" in this disclosure. The first pull-down device 112 and the second pull-down device 114 may be thin oxide transistors, or include thin oxide transistors.

[0067] Because the first protection device 108 and the second protection device 110 are thick oxide transistors, they can be started with a larger input voltage. In contrast, the thin oxide transistors of the first pull-down device 112 and the second pull-down device 114 operate at a lower voltage relative to the first protection device 108 and the second protection device 110. An additional bias voltage capable of driving the first protection device 108 and the second protection device 110 can be generated by the self-protection bias generator circuit 102. In addition, the self-protection bias generator circuit 102 can generate a signal capable of driving the thin oxide transistors of the first pull-down device 112 and the second pull-down device 114.

[0068] The self-protection bias generator circuit 102 may be connected to a power supply voltage V1, which may have a voltage capable of driving the first pull-down device 112 and the second pull-down device 114 but not driving the first protection device 108 and the second protection device 110. The self-protection bias generator circuit 102 may generate output voltage signals IN_HV and INB_HV using the power supply voltage V1 and the input signal IN, and the output voltage signals IN_HV and INB_HV may respectively drive the gates of the thick oxide transistors of the first protection device 108 and the second protection device 110. The self-protection bias generator circuit 102 may further provide output signals INI and INB corresponding to the power supply voltage V1, and the output signals INI and INB may drive the gates of the thin oxide transistors of the first pull-down device 112 and the second pull-down device 114.

[0069] The self-protection bias generator circuit 102 can generate output voltage signals IN_HV and INB_HV using only the power supply voltage V1 and the input signal IN without utilizing an additional bias voltage source that can drive the first protection device 108 and the second protection device 110 (for example, by a voltage greater than the power supply voltage V1). This reduces the overall power consumption compared to an implementation utilizing an additional bias voltage source. In addition, the self-protection bias generator circuit 102 can utilize thin oxide transistors at the input of the self-protection bias generator circuit 102, thereby enabling operation with relatively low voltage inputs. The self-protection bias generator circuit 102 only uses a relatively low power supply voltage V1, thereby increasing the ratio of the output voltage at the OUT node 118 to the input voltage of the input signal IN. Using the self-protection bias generator circuit 102 can provide compatibility with various logic processes without the need for additional process-specific components, devices, or circuits to perform level conversion. Various embodiments of the circuit of the self-protection bias generator circuit 102 will be combined Figure 4 and Figure 5 to describe.

[0070] Included in the Figure 1 The operation of the self-protection bias generator circuit 102 in the example level converter 100 will be combined with Figure 2 The waveform diagram 200 is used to describe. Figure 2 Draws Figure 1 200 is a waveform diagram of a voltage signal of a circuit in response to an input signal IN being in a "logic high" (e.g., "logic 1") state. In this example operation, from time t0 to t1, the input signal IN is in a logic high state (e.g., equal to the power supply voltage V1, such as Figure 2). When the input signal IN is in a logic high state, the self-protection bias generator circuit 102 can generate an output signal INI, and the output signal INI drives the first pull-down device 112 by a logic high voltage approximately equal to the power supply voltage V1. In addition, the self-protection bias generator circuit 102 generates an output voltage signal IN_HV, and the output voltage signal IN_HV drives the first protection device 108 by a bias voltage V3 that is greater than the power supply voltage V1 and less than the power supply voltage V2. The larger bias voltage enables the first protection device 108 to be activated even if the first protection device 108 includes a thick oxide transistor. Although not shown in this disclosure for clarity, the output signal INB is driven to a logic low (e.g., ground voltage, "logic 0") between times t0 and t1. In one embodiment, the output voltage signal INB_HV can be driven to a ground voltage or a voltage less than the bias voltage V3 (e.g., less than the threshold voltage of the second protection device 110). The power supply voltage V1 and the power supply voltage V2 can correspond to a first voltage domain and a second voltage domain, respectively. Voltage domains correspond to different sections or areas of a circuit that operate at different voltage levels and can be used to ensure that different portions of a circuit operate at the correct voltage levels to minimize power consumption, prevent damage, and improve overall performance.

[0071] When the output signal INI is generated at a logic high voltage and the output voltage signal IN_HV is generated at the bias voltage V3, both the first protection device 108 and the first pull-down device 112 are activated. In addition, when the output signal INB and the output voltage signal INB_HV are set to a logic low and less than the bias voltage V3, respectively, the second protection device 110 and the second pull-down device 114 are both turned off. When the first protection device 108 and the first pull-down device 112 are activated, the OUTB node 116 is pulled to approximately equal to the ground voltage. This situation activates the second pull-up device 106. Because the second protection device 110 and the second pull-down device 114 are turned off and non-conductive, and the second pull-up device 106 is activated and conductive, a voltage approximately equal to the power supply voltage V2 is generated at the OUT node 118 between approximately time t0 and t1, which has a slight time offset due to the time it takes for the transistors in the level converter 100 to change states.

[0072] When the input signal IN transitions to a logic low state after time t1, the self-protection bias generator circuit 102 pulls the output signal INI to a logic low state (e.g., a ground voltage) and outputs an output voltage signal IN_HV approximately equal to the power supply voltage V1. When the output signal INI is in a logic low state and the output voltage signal IN_HV has a voltage approximately equal to the power supply voltage V1, both the first protection device 108 and the first pull-down device 112 are turned off. Other details of the voltage levels of the nodes in the level converter 100 when the input signal IN is in a logic low state will be described in conjunction with Figure 3 to describe.

[0073] Figure 3 Draws Figure 1 300 is a waveform diagram of a voltage signal of the level converter 100 including the self-protection bias generator circuit 102 when the input signal IN is in a logic low state. In this example operation, from time t0 to t1, the input signal IN ( Figure 3 When the input signal IN is in a logic low state, the self-protection bias generator circuit 102 can generate an output signal INB, and the output signal INB drives the second pull-down device 114 by a logic high voltage approximately equal to the power supply voltage V1. In addition, the self-protection bias generator circuit 102 generates an output voltage signal INB_HV, and the output voltage signal INB_HV drives the second protection device 110 by a bias voltage V3 that is greater than the power supply voltage V1 and less than the power supply voltage V2. The larger bias voltage enables the second protection device 110 to be activated even if the first protection device 110 includes a thick oxide transistor. Although not shown in the present disclosure for clarity, the output signal INI is driven to a logic low voltage (e.g., ground voltage) between times t0 and t1. In addition, the output voltage signal IN_HV can be driven to a ground voltage or a voltage less than the edge voltage V3 (e.g., less than the critical voltage of the second protection device 110, approximately equal to the power supply voltage V1, etc.), as shown in FIG. Figure 2 The portion of the waveform diagram 200 shown is after time t1 .

[0074] When the output signal INB is generated at a logic high voltage and the output voltage signal INB_HV is generated at the bias voltage V3, both the second protection device 110 and the second pull-down device 114 are activated. In addition, when the output signal INI and the output voltage signal IN_HV are respectively set to a logic low and less than the bias voltage V3 (e.g., approximately equal to the power supply voltage V1), both the first protection device 108 and the first pull-down device 112 are turned off. When the second protection device 110 and the second pull-down device 114 are activated, the OUT node 118 is pulled to approximately equal to the ground voltage. This situation activates the first pull-up device 104. Because the first protection device 108 and the first pull-down device 112 are turned off and non-conductive, and the first pull-up device 104 is activated and conductive, a voltage approximately equal to the power supply voltage V2 is generated at the OUTB node 116 between approximately time t0 and t1, which has a slight time offset due to the time it takes for the transistors in the level converter 100 to change states.

[0075] When the input signal IN is converted to a logic high state after time t1, the self-protection bias generator circuit 102 pulls the output signal INB to a logic low state (e.g., a ground voltage) and outputs an output voltage signal INB_HV approximately equal to the power supply voltage V1. When the output signal INB is in a logic low state and the output voltage signal INB_HV has a voltage approximately equal to the power supply voltage V1, both the second protection device 110 and the second pull-down device 114 are turned off. Other details of the voltage levels of the nodes in the level converter 100 when the input signal IN is in a logic high state will be described in detail in conjunction with Figure 2 to describe.

[0076] Various embodiments of the circuit for implementing the level converter 100 including the self-protection bias generator circuit 102 will be respectively combined with Figure 4 and Figure 5 400 and 500 of the present disclosure. The transistors described in the present disclosure are illustrated as being of a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a Complementary Metal Oxide Semiconductor (CMOS) transistor, a P-channel Metal-Oxide Semiconductor (PMOS), an N-channel Metal-Oxide Semiconductor (NMOS), a Bipolar Junction Transistor (BJT), a high voltage transistor, a high frequency transistor, a P-channel and / or N-channel Field Effect Transistor (PFET / NFET), a Fin Field Effect Transistor (FinFET), a planar MOS transistor with elevated source / drain, a nanosheet FET, a nanowire FET, or the like. In addition, although Figure 4 The transistors M1 to M10 and Figure 5 The transistors M11 to M20 are each illustrated as one transistor, but the embodiment is not limited thereto. For example, Figure 4 The transistors M1 to M10 and Figure 5The transistors M11 to M20 of the present disclosure may each include more than one transistor ("sub-transistor") connected in parallel to each other. For example, in one embodiment, the sub-transistors of any transistor described in the present disclosure may each include a gate, a drain, and a source that are electrically coupled in parallel to the gates, drains, and sources of the other sub-transistors.

[0077] Figure 4 A circuit diagram 400 of an example self-protection bias generator circuit 402 driving a transistor of a level shifter circuit 403 is shown. The level shifter circuit 403 of the circuit diagram 400 generates an output voltage at an OUT node 418 having the same logic state as the input signal IN. Figure 4 As shown, the self-protection bias voltage generator circuit 402 includes a first inverter 404 and a second inverter 406. In some implementations, the first inverter 404 and the second inverter 406 may each include a thin oxide transistor. The self-protection bias voltage generator circuit 402 including the first inverter 404 and the second inverter 406 may be connected to a power supply voltage V1 and powered by the power supply voltage V1, such as Figure 4 shown.

[0078] The self-protection bias generator circuit 402 includes transistors M1, M2, M3, and M4. In some implementations, transistors M1, M2, M3, and M4 each include an nMOSFET. It should be understood that transistors M1 to M4 may each include various other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while remaining within the scope of the embodiments of the present disclosure. The drains of transistors M1 to M4 are electrically coupled to a power supply voltage V1. Transistors M1 and M4 operate as diode-connected transistors, wherein the gates of transistors M1 and M4 are each coupled to the drains of transistors M1 and M4 (e.g., the power supply voltage). Transistors M1 and M2 are coupled in parallel, wherein the sources of transistors M1 and M2 are each electrically coupled to an IN_HV node 412. Transistors M3 and M4 are coupled in parallel, wherein the sources of transistors M3 and M4 are each electrically coupled to an INB_HV node 414. The gate of transistor M2 is electrically coupled to INB_HV node 414, and the gate of transistor M3 is electrically coupled to IN_HV node 412. Transistors M1 to M4 may be thick oxide devices.

[0079] The self-protection bias generator circuit 402 includes a capacitor 408 and a capacitor 410. One terminal of the capacitor 408 is electrically coupled to the output of the first inverter 404 at the INB node 407, and the other terminal of the capacitor 408 is electrically coupled to the INB_HV node 414. One terminal of the capacitor 410 is electrically coupled to the output of the second inverter 406 at the INI node 409, and the other terminal of the capacitor 410 is electrically coupled to the IN_HV node 412. The transistors M1 to M4 and the capacitors 408 and 410 coupled to logically opposite inputs at the INB node 407 and the INI node 409, respectively, form a voltage doubler circuit that can output a voltage up to twice the power supply voltage V1 at the IN_HV node 412 or the INB_HV node 414 when controlled as described in this disclosure.

[0080] In the example operation of the self-protection bias generator circuit 402, the input signal IN is set to an initial logic state. In this example, the first logic state may be a logic low state (e.g., approximately equal to the ground voltage or zero volts). The first inverter 404 receives the input signal IN and generates an inverted input signal in a logic high state (e.g., approximately equal to the power supply voltage V1) at the INB node 407. The second inverter 406 receives the inverted input signal in a logic high state and generates a buffered input signal in a logic low state (e.g., approximately equal to the ground voltage) at the INI node 409. When the INB node 407 is approximately equal to the power supply voltage V1 and the INI node 409 is approximately equal to the ground voltage, the transistor M2 is turned on and the transistor M3 is turned off. When the transistor M2 is turned on and the INI node 409 has a voltage approximately equal to the ground voltage, the capacitor 410 is charged to a voltage approximately equal to the power supply voltage V1.

[0081] When the input signal IN changes from the initial logic low state to the logic high state, the first inverter 404 receives the input signal IN and generates an inverted input signal in a logic low state (i.e., approximately equal to the ground voltage) at the INB node 407. The second inverter 406 receives the inverted input signal in a logic low state and generates a buffered input signal in a logic high state (e.g., approximately equal to the power supply voltage V1) at the INI node 409. When the voltage at the INB node 407 is approximately equal to zero volts, the transistor M2 is turned off. The transistor M1 is in a diode connection configuration in parallel with the transistor M2, so that the voltage at the IN_HV node 412 can safely exceed the power supply voltage V1. When the voltage at the INI node 409 is driven to the power supply voltage V1, the IN_HV node 412 is therefore driven to twice the power supply voltage V1, thereby starting the transistor M3 and charging the capacitor 408. Because the load of IN_HV node 412 is capacitive (eg, the gates of transistors M3 and M7 ), the boosted voltage across capacitor 410 can be maintained without rapidly discharging (eg, compared to a resistive load).

[0082] Next, when the input signal IN changes from a logic high state to a logic low state, the first inverter 404 receives the input signal IN and generates an inverted input signal in a logic high state (i.e., approximately equal to the power supply voltage V1) at the INB node 407. The second inverter 406 receives the inverted input signal in a logic high state and generates a buffered input signal in a logic low state (e.g., approximately equal to the ground voltage) at the INI node 409. When the voltage at the INI node 409 is approximately equal to zero volts, the transistor M3 is turned off. The transistor M4 is in a diode connection configuration in parallel with the transistor M3, so that the voltage at the INB_HV node 414 can safely exceed the power supply voltage V1. When the voltage at the INB node 407 is driven to the power supply voltage V1, the INB_HV node 414 is therefore driven to approximately twice the power supply voltage V1, thereby starting the transistor M2 and discharging the capacitor 410, so that the IN_HV node 412 has a voltage approximately equal to the power supply voltage V1. Because the load of INB_HV node 414 is capacitive (eg, the gates of transistors M2 and M8 ), the boosted voltage across capacitor 408 can be maintained without rapidly discharging (eg, compared to a resistive load).

[0083] As described in this disclosure, transistors M1 and M4 operate as diode-connected transistors. Due to the configuration of transistors M1 and M4 at IN_HV node 412 and INB_HV node 414, respectively, the threshold voltages (V th) may affect the voltages of the IN_HV node 412 and the INB_HV node 414. For example, when the input signal IN is in a logic low state, instead of ranging from the power supply voltage V1 to twice the power supply voltage V1, the voltage at the IN_HV node 412 may range from the power supply voltage V1 minus the threshold voltage of the transistor M1 to the power supply voltage V1; when the input signal IN is in a logic high state, the range may be twice the power supply voltage V1 minus the threshold voltage of the transistor M1 to twice the power supply voltage V1. In another example, when the input signal IN is in a logic high state, instead of ranging from the power supply voltage V1 to twice the power supply voltage V1, the voltage at the INB_HV node 414 may range from the power supply voltage V1 minus the threshold voltage of the transistor M4 to the power supply voltage V1; when the input signal is in a logic low state, the range may be twice the power supply voltage V1 minus the threshold voltage of the transistor M1 to twice the power supply voltage V1.

[0084] like Figure 4 As shown, the INB node 407, the INI node 409, the IN_HV node 412, and the INB_HV node 414 each drive the gate of the transistor of the level converter circuit 403. Figure 4 As shown, the level converter circuit 403 includes transistors M5, M6, M7, M8, M9, and M10. In some implementations, transistors M5 and M6 each include a pMOSFET, and transistors M7, M8, M9, and M10 each include an nMOSFET. It should be understood that transistors M5 to M10 may each include various other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while remaining within the scope of the embodiments of the present disclosure. Transistors M5, M6, M7, and M8 may be thick oxide transistors, and transistors M9 and M10 may be thin oxide transistors. The sources of transistors M5 and M6 are electrically coupled to a second power supply voltage V2. The gate of transistor M5 is connected to the drain of transistor M6 and the drain of transistor M8 at OUT node 418, and the gate of transistor M6 is connected to the drain of transistor M5 and the drain of transistor M7 at OUTB node 416. The source of transistor M7 is connected to the drain of transistor M9, and the source of transistor M9 is connected to the ground voltage. The source of the transistor M8 is connected to the drain of the transistor M10 , and the source of the transistor M8 is connected to the ground voltage.

[0085] In this example, transistors M5 and M6 may be similar to Figure 1 Further, transistors M7 and M8 may be similar to Figure 1 The protection devices 108 and 110, and the transistors M9 and M10 can be similar to Figure 1The transistors M5 to M10 of the level converter circuit 403 can be similar to the combination of Figure 1 The components of the level converter 100 are described in detail. Figure 4 As shown, the gates of transistors M7 , M8 , M9 , and M10 receive voltage signals from the self-protection bias generator circuit 402 .

[0086] In an example operation of the level converter circuit 403, when the IN_HV node 412 and the INI node 409 are driven to approximately twice the power supply voltage and the power supply voltage, respectively (for example, when the input signal IN is a logic high), both transistors M7 and M9 may be activated. As described in the present disclosure, when the input signal IN is a logic high, the INB_HV node 414 and the INB node 407 are driven to approximately equal to the power supply voltage and the ground voltage, respectively, causing both transistors M8 and M10 to be turned off. When transistors M7 and M9 are activated, the OUTB node 416 is pulled to approximately equal to the ground voltage, thereby activating transistor M6. Because transistors M8 and transistor M10 are turned off and not conducting, and transistor M6 is activated and conducting, when the input signal IN is in a logic high state, a voltage approximately equal to the second power supply voltage V2 is generated at the output OUT node 418. In the diagram shown in Figure 4 In the embodiment of FIG. 4 , the level shifter circuit 403 generates an output voltage at the OUT node 418 that is at the same logic state as the input signal IN.

[0087] If the input signal IN is in a logic low state, the self-protection bias generator circuit 402 pulls the INI node 409 to approximately equal to the ground voltage and outputs an output voltage signal IN_HV approximately equal to the power supply voltage V1, as described in the present disclosure document. This situation causes both transistors M7 and M9 to be turned off. In addition, the self-protection bias generator circuit 402 generates a logic high voltage approximately equal to the power supply voltage V1 at the INB node 407, and generates a voltage approximately equal to twice the power supply voltage V1 at the INB_HV node 414, thereby enabling transistors M8 and M10 to be activated. When transistors M8 and M10 are activated, the voltage at the OUT node 418 is pulled to the ground voltage, and transistor M5 is activated. Because transistors M7 and M9 are not turned on, and transistor M5 is turned on, the voltage at the OUTB node 416 is approximately equal to the second power supply voltage V2. The level converter circuit 403 therefore generates an output voltage at the OUT node 418, which is in the same logic state as the input signal IN. Figure 4 The details of the voltage of each described node in response to different input signals are shown in Table 1 below.

[0088] node Input signal IN=0V Input signal IN=V1 INI Node 409 0V V1 INB node 407 V1 0 IN_HV node 412 V1-Vth to V1 2*V1-Vth to 2*V1 INB_HV node 414 2*V1-Vth to 2*V1 V1-Vth to V1 OUTB node 416 V2 0V OUT node 418 0V V2

[0089] Table 1

[0090] In the above Table 1, V th Corresponding to the threshold voltage of transistor M1 or M4. Although OUT node 418 is illustrated as being merely an output of level shifter circuit 403, it should be appreciated that in some embodiments, OUTB node 416 itself may serve as an output that provides a logical inversion signal of OUT node 418 at a second power supply voltage V2. OUT node 418 or OUTB node 416 may provide one or more outputs to one or more circuits operating at the second power supply voltage V2, such as an I / O circuit or logic circuit operating at a power supply voltage greater than V1.

[0091] Figure 5 A circuit diagram 500 of an example self-protection bias generator circuit 502 driving a transistor of a level shifter circuit 503 is shown. The level shifter circuit 503 of the circuit diagram 500 generates an output voltage at an OUT node 518, which has a logic state that is inverse to the input signal IN. The self-protection bias circuit 502 and the level shifter circuit 503 of the circuit diagram 500 may be similar to Figure 4 The self-protection bias circuit 402 and the level converter circuit 403. Figure 5 As shown, the self-protection bias voltage generator circuit 502 includes a first inverter 504 and a second inverter 506. In some implementations, the first inverter 504 and the second inverter 506 may each include a thin oxide transistor. The self-protection bias voltage generator circuit 502 including the first inverter 504 and the second inverter 506 may be connected to a power supply voltage V1 and powered by the power supply voltage V1, such as Figure 5 shown.

[0092] The self-protection bias generator circuit 502 includes transistors M11, M12, M13, and M14. In some implementations, transistors M11, M12, M13, and M14 each include an nMOSFET. It should be understood that transistors M11 to M14 may each include various other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while remaining within the scope of the embodiments of the present disclosure. The drains of transistors M11 to M14 are electrically coupled to a power supply voltage V1. Transistors M11 and M14 operate as diode-connected transistors, wherein the gates of transistors M11 and M14 are each coupled to the drains of transistors M11 and M14 (e.g., the power supply voltage). Transistors M11 and M12 are coupled in parallel, wherein the sources of transistors M11 and M12 are each electrically coupled to an INB_HV node 512. Transistors M13 and M14 are coupled in parallel, with each respective source of transistors M13 and M14 electrically coupled to IN_HV node 514. The gate of transistor M12 is electrically coupled to IN_HV node 514, and the gate of transistor M13 is electrically coupled to INB_HV node 512. Transistors M11 to M14 may be thick oxide devices.

[0093] The self-protection bias generator circuit 502 includes a capacitor 508 and a capacitor 510. One terminal of the capacitor 508 is electrically coupled to the output of the second inverter 506 at the INI node 507, and the other terminal of the capacitor 508 is electrically coupled to the IN_HV node 514. One terminal of the capacitor 510 is electrically coupled to the output of the first inverter 504 at the INB node 509, and the other terminal of the capacitor 510 is electrically coupled to the INB_HV node 512. Transistors M11 to M14 and capacitors 508 and 510 coupled to logically opposite inputs at nodes 507 and 509, respectively, form a voltage doubler circuit that can output a voltage up to twice the power supply voltage V1 at the INB_HV node 512 or the IN_HV node 514 when controlled as described in this disclosure.

[0094] In the example operation of the self-protection bias generator circuit 502, the input signal IN is set in an initial logic state. In this example, the first logic state may be a logic low state (e.g., approximately equal to the ground voltage or zero volts). The first inverter 504 receives the input signal IN and generates an inverted input signal in a logic high state (e.g., approximately equal to the power supply voltage V1) at the INB node 509. The second inverter 506 receives the inverted input signal in a logic high state and generates a buffered input signal in a logic low state (e.g., approximately equal to the ground voltage) at the INI node 507. When the INB node 509 is approximately equal to the power supply voltage V1 and the INI node 507 is approximately equal to the ground voltage, the transistor M13 is turned on and the transistor M12 is turned off. When the transistor M13 is turned on and the INI node 507 has a voltage of approximately the ground voltage, the capacitor 508 is charged to a voltage approximately equal to the power supply voltage V1.

[0095] When the input signal IN changes from the initial logic low state to the logic high state, the first inverter 504 receives the input signal IN and generates an inverted input signal in a logic low state (e.g., approximately equal to the ground voltage) at the INB node 509. The second inverter 506 receives the inverted input signal in a logic low state and generates a buffered input signal in a logic high state (e.g., approximately the power supply voltage V1) at the INI node 507. When the voltage at the INB node 509 is approximately zero volts, the transistor M13 is turned off. The transistor M14 is in a diode connection configuration in parallel with the transistor M13, so that the voltage at the IN_HV node 514 can safely exceed the power supply voltage V1. When the voltage at the INI node 507 is driven to the power supply voltage V1, the IN_HV node 514 is therefore driven to twice the power supply voltage V1, thereby starting the transistor M12 and charging the capacitor 510. Because the load of IN_HV node 514 is capacitive (eg, the gates of transistors M12 and M18 ), the boosted voltage across capacitor 508 can be maintained without rapidly discharging (eg, compared to a resistive load).

[0096] Next, when the input signal IN changes from a logic high state to a logic low state, the first inverter 504 receives the input IN and generates an inverted input signal in a logic high state (i.e., approximately equal to the power supply voltage V1) at the INB node 509. The second inverter 506 receives the inverted input signal in a logic high state and generates a buffered input signal in a logic low state (e.g., approximately equal to the ground voltage) at the INI node 507. When the voltage at the INI node 507 is approximately equal to zero volts, the transistor M12 is turned off. The transistor M11 is in a diode connection configuration in parallel with the transistor M12, so that the voltage at the INB_HV node 512 can safely exceed the power supply voltage V1. When the voltage at the INB node 509 is driven to the power supply voltage V1, the INB_HV node 512 is therefore driven to approximately twice the power supply voltage V1, thereby starting the transistor M13 and discharging the capacitor 508, so that the IN_HV node has a voltage approximately equal to the power supply voltage V1. Because the load of INB_HV node 512 is capacitive (eg, the gates of transistors M13 and M17), the boosted voltage across capacitor 510 can be maintained without rapid discharge (eg, compared to a resistive load).

[0097] As described in the present disclosure, transistors M11 and M14 operate as diode-connected transistors. Due to the configuration of transistors M11 and M14 at the INB_HV node 512 and the IN_HV node 514, respectively, the threshold voltages of transistors M11 and M14 may affect the voltages of the IN_HV node 512 and the INB_HV node 514. For example, when the input signal is in a logic high state, instead of ranging from the power supply voltage V1 to twice the power supply voltage V1, the voltage range at the INB_HV node 512 may be from the power supply voltage V1 minus the threshold voltage of transistor M11 to the power supply voltage V1; when the input signal is in a logic low state, the range may be from twice the power supply voltage V1 minus the threshold voltage of transistor M11 to twice the power supply voltage V1. In another example, when the input signal is in a logic low state, instead of a range from the power supply voltage V1 to twice the power supply voltage V1, the voltage range at the IN_HV node 514 may be the power supply voltage V1 minus the threshold voltage of transistor M14 to the power supply voltage V1; when the input signal is in a logic high state, the range may be twice the power supply voltage V1 minus the threshold voltage of transistor M11 to twice the power supply voltage V1.

[0098] like Figure 5 As shown, the INI node 507, the INB node 509, the INB_HV node 512, and the IN_HV node 514 each drive the gate of the transistor of the level converter circuit 503. Figure 5As shown, the level converter circuit 503 includes transistors M15, M16, M17, M18, M19, and M20. In some implementations, transistors M15 and M16 each include a pMOSFET, and transistors M17, M18, M19, and M20 each include an nMOSFET. It should be understood that transistors M15 to M20 may each include various other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while remaining within the scope of the embodiments of the present disclosure. Transistors M15, M16, M17, and M18 may be thick oxide transistors, and transistors M19 and M20 may be thin oxide transistors. The sources of transistors M15 and M16 are electrically coupled to the second power supply voltage V2. The gate of transistor M15 is connected to the drain of transistor M16 and the drain of transistor M18 at OUT node 518, and the gate of transistor M16 is connected to the drain of transistor M15 and the drain of transistor M17 at OUTB node 516. The source of the transistor M17 is connected to the drain of the transistor M19, and the source of the transistor M19 is connected to the ground voltage. The source of the transistor M18 is connected to the drain of the transistor M20, and the source of the transistor M18 is connected to the ground voltage.

[0099] In this example, transistors M15 and M16 may be similar to Figure 1 Further, transistors M17 and M18 may be similar to Figure 1 The protection devices 108 and 110, and the transistors M19 and M20 can be similar to Figure 1 The transistors M15 to M20 of the level converter circuit 503 can be similar to the combination of Figure 1 The components of the level converter 100 are described in detail. Figure 5 As shown, the gates of transistors M17 , M18 , M19 , and M20 receive voltage signals from the self-protection bias generator circuit 502 .

[0100] In an example operation of the level converter circuit 503, when the INB_HV node 512 and the INB node 509 are driven to approximately twice the power supply voltage and the power supply voltage, respectively (for example, when the input signal IN is a logic low), both transistors M17 and M19 may be activated. As described in the present disclosure, when the input signal IN is a logic low, the IN_HV node 514 and the IN node 507 are driven to approximately equal to the power supply voltage and the ground voltage, respectively, causing both transistors M18 and M20 to be turned off. When transistors M17 and M19 are activated, the OUTB node 516 is pulled to approximately equal to the ground voltage, thereby activating transistor M16. Because transistors M18 and transistor M20 are turned off and not conducting, and transistor M16 is activated and conducting, when the input signal IN is in a logic low state, a voltage approximately equal to the second power supply voltage V2 is generated at the output OUT node 518. In the diagram shown in Figure 5 In the embodiment of FIG. 5 , the level shifter circuit 503 generates an output voltage at the OUT node 518 , which is in a logic state opposite to the input signal IN.

[0101] If the input signal IN is in a logic high state, the self-protection bias generator circuit 502 pulls the INB node 509 to approximately equal to the ground voltage and outputs an output voltage signal INB_HV approximately equal to the power supply voltage V1, as described in the present disclosure. This situation causes both transistors M17 and M19 to be turned off. In addition, the self-protection bias generator circuit 502 generates a logic high voltage approximately equal to the power supply voltage V1 at the INI node 507, and generates a voltage approximately equal to twice the power supply voltage V1 at the IN_HV node 514, thereby enabling both transistors M18 and M20 to be activated. When transistors M18 and M20 are activated, the voltage at the OUT node 518 is pulled to the ground voltage, and transistor M15 is activated. Because transistors M17 and M19 are not conducting, and transistor M15 is conducting, the voltage at the OUTB node 516 is approximately equal to the second power supply voltage V2. The level converter circuit 503 therefore generates an output voltage at the OUT node 518, which is in a logic state inverted from the input signal IN. Figure 5 The details of the voltage of each described node in response to different input signals are shown in Table 2 below.

[0102] node Input signal IN=0V Input signal IN=V1 INI Node 507 0V V1 INB Node 509 V1 0 IN_HV node 514 V1-Vth to V1 2*V1-Vth to 2*V1 INB_HV node 512 2*V1-Vth to 2*V1 V1-Vth to V1 OUTB Node 516 0V V2 OUT node 518 V2 0V

[0103] Table 2

[0104] In the above Table 2, V thCorresponding to the threshold voltage of transistor M11 or M14. Although OUT node 518 is illustrated as being merely an output of level shifter circuit 503, it should be appreciated that in some embodiments, OUTB node 516 itself may be used as an output that provides a logical inversion signal of OUT node 518 at a second power supply voltage V2. OUT node 518 or OUTB node 516 may provide one or more outputs to one or more circuits operating at the second power supply voltage V2, such as an I / O circuit or logic circuit operating at a power supply voltage greater than V1.

[0105] Figure 6 Flowchart of an example method 600 for operating a voltage providing circuit according to some embodiments of the present disclosure. The method 600 may be used to generate a level conversion device (e.g., the level converter 100, the circuit diagram 400, the circuit diagram 500, etc.) including a self-protection bias generator (e.g., the self-protection bias generator circuit 102, the self-protection bias generator circuit 402, the self-protection bias generator circuit 502, etc.). For example, at least a portion of the operations described in the method 600 use Figures 1 to 5 It should be noted that method 600 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 600 may be used in Figure 6 Additional operations are provided before, during, and after method 600, and some other operations may be described only briefly in this disclosure.

[0106] In summary, the method 600 begins at operation 602, where an input signal corresponding to a first voltage source is received. The method 600 then proceeds to operation 604, where a bias voltage is generated based on the input signal and using the first voltage source. The method 600 then proceeds to operation 606, where the bias voltage is provided to a protection transistor of a level shifting circuit, the level shifting circuit being electrically coupled to a second voltage source having a second voltage, wherein the second voltage is greater than a first voltage of the first voltage source. The method 600 then proceeds to operation 608, where an output voltage is generated based on the bias voltage, the bias voltage being a second voltage or a ground voltage.

[0107] Referring to operation 602, an input signal (e.g., an input signal IN described in the present disclosure) corresponding to a first voltage source (e.g., a power supply voltage V1) is received. The input signal may be provided via one or more logic circuits and received by a self-protection bias generator (e.g., self-protection bias generator circuit 102, self-protection bias generator circuit 402, self-protection bias generator circuit 502, etc.), as described in the present disclosure. In one embodiment, the input signal may be received by an inverter of the self-protection bias generator.

[0108] Referring to operation 604, based on the input signal and using a bias voltage of a first voltage source (eg, as shown in FIG. 1 ), Figure 2 and Figure 3 The bias voltage may be generated by a self-protection bias generator to drive one or more thick oxide transistors of a level shifting circuit (e.g., level shifter 100, level shifter circuit 403, level shifter circuit 503, etc.). In one embodiment, for example, when the input signal changes from a first logic state to a second logic state, the self-protection bias generator may generate a second bias voltage based on the input signal and using a first voltage source.

[0109] Referring to operation 606, a bias voltage may be provided to a protection transistor (e.g., a thick oxide transistor) of a level shifting circuit (e.g., level shifter 100). The level shifting circuit may be electrically coupled to a second voltage source (e.g., power supply voltage V2) greater than a first voltage source (e.g., power supply voltage V1). The bias voltage (e.g., output voltage signal IN_HV) may be provided to a gate of a protection transistor (e.g., first protection device 108) to drive the protection transistor. In embodiments where the second bias voltage (e.g., output voltage signal INB_HV) is generated when the input signal changes from a first logic state to a second logic state, the second bias voltage may be provided to a second protection transistor (e.g., second protection device 110) of the level shifting circuit, as described in the disclosure.

[0110] Referring to operation 608, an output voltage (e.g., a voltage at the OUT node 118, 418, or 518, a voltage at the OUTB node 116, 416, or 516, etc.) may be generated based on a bias voltage, which is a voltage of a second voltage source or a ground voltage. The bias voltage may control a transistor (e.g., a first pull-down device 112, a second pull-down device 114, etc.) of the level conversion circuit so that the level conversion circuit generates (e.g., at the output node 118) a logic high output (e.g., a voltage of the second voltage source) or a logic low output (e.g., a ground voltage).

[0111] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a level shifting circuit and a bias generating circuit. The level shifting circuit is used to generate an output voltage in a second voltage domain corresponding to an input signal in a first voltage domain, wherein the level shifting circuit includes at least a thick oxide transistor and a thin oxide transistor. The bias generating circuit is operatively coupled to the level shifting circuit and is used to: generate a bias voltage substantially higher than a voltage of the input signal; and provide the bias voltage to a gate of the thick oxide transistor, so that the level shifting circuit generates an output voltage.

[0112] In some embodiments of the semiconductor device, a first terminal of the thin oxide transistor is electrically coupled to ground, and a second terminal of the thin oxide transistor is electrically coupled to the first terminal of the thick oxide transistor.

[0113] In some embodiments of the semiconductor device, a threshold voltage of the thick oxide transistor is greater than a threshold voltage of the thin oxide transistor.

[0114] In some embodiments of the semiconductor device, a gate of the thick oxide transistor and a gate of the thin oxide transistor are electrically coupled to a bias voltage generating circuit via a first capacitor and a second capacitor, respectively.

[0115] In some embodiments of the semiconductor device, the bias generating circuit is electrically coupled to a first voltage source of the first voltage domain, and the level shifting circuit is electrically coupled to a second voltage source of the second voltage domain.

[0116] In some embodiments of the semiconductor device, the level conversion circuit is used to generate an output voltage in the second voltage domain, and the output voltage is proportional to the input signal.

[0117] In some embodiments of the semiconductor device, the level conversion circuit is used to generate an output voltage in the second voltage domain, and the output voltage is proportional to a logic inversion signal of the input signal.

[0118] In some embodiments of the semiconductor device, the bias circuit includes a plurality of inverters.

[0119] In some embodiments of the semiconductor device, the level conversion circuit further includes a second thick oxide transistor and a second thin oxide transistor, and the bias generating circuit generates a second bias voltage.

[0120] In another aspect of the present disclosure, a semiconductor circuit is disclosed. The semiconductor circuit includes a first capacitor, a second capacitor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The first capacitor has a first terminal coupled to a first signal. The second capacitor has a first terminal coupled to a source of a logic inversion signal of the first signal. The gate of the first NMOS transistor is coupled to a source voltage of the second NMOS transistor, the gate of the second NMOS transistor is coupled to a source voltage of the first NMOS transistor, the drain of the first NMOS transistor and the drain of the second NMOS transistor are coupled to a power supply voltage. The gate and drain of the third NMOS transistor and the gate and drain of the fourth NMOS transistor are coupled to a power supply voltage, the source of the first NMOS transistor and the source of the third NMOS transistor are each coupled to a voltage at the second terminal of the first capacitor, and the source of the second NMOS transistor and the source of the fourth NMOS transistor are each coupled to a voltage at the second terminal of the second capacitor. In response to the first signal being in a first logic state, the semiconductor circuit generates a bias output voltage at the second terminal of the second capacitor or at the second terminal of the first capacitor.

[0121] In some embodiments of the semiconductor circuit, the semiconductor circuit generates a second bias output voltage at a second terminal of the first capacitor.

[0122] In some embodiments of the semiconductor circuit, the semiconductor circuit further includes a level converter, the level converter includes a first PMOS transistor and a second PMOS transistor, the source of the first PMOS transistor and the source of the second PMOS transistor are coupled to a second power supply voltage greater than the power supply voltage, the gate of the first PMOS transistor is coupled to the drain voltage of the second PMOS transistor, and the gate of the second PMOS transistor is coupled to the drain voltage of the first PMOS transistor.

[0123] In some embodiments of the semiconductor circuit, the level converter further includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor. The drain of the fifth NMOS transistor is coupled to the drain voltage of the first PMOS transistor. The drain of the sixth NMOS transistor is coupled to the source voltage of the fifth NMOS transistor, and the source of the sixth NMOS transistor is coupled to the ground voltage. The drain of the seventh NMOS transistor is coupled to the drain voltage of the second PMOS transistor. The drain of the eighth NMOS transistor is coupled to the source voltage of the seventh NMOS transistor, and the source of the eighth NMOS transistor is coupled to the ground voltage.

[0124] In some embodiments of the semiconductor circuit, a gate of the fifth NMOS transistor is coupled to the bias output voltage at the second terminal of the second capacitor, and a gate of the sixth NMOS transistor is coupled to a logic inversion signal of the first signal.

[0125] In some embodiments of the semiconductor circuit, a drain voltage of the seventh NMOS transistor provides a second power supply voltage that is in a logic state matching a logical inversion signal of the first signal.

[0126] In some embodiments of the semiconductor circuit, the semiconductor circuit generates a bias output voltage at the second terminal of the first capacitor, the gate of the seventh NMOS transistor is coupled to the bias output voltage at the second terminal of the first capacitor, and the gate of the eighth NMOS transistor is coupled to a logically in-phase signal of the first signal.

[0127] In some embodiments of the semiconductor circuit, a drain voltage of the seventh NMOS transistor provides a second power supply voltage, the second power supply voltage being in a logic state matching a logic state of the first signal.

[0128] In some embodiments of the semiconductor circuit, the semiconductor circuit further comprises a first inverter and a second inverter. The first inverter is used to receive an input signal and generate a first signal. The second inverter is used to receive the first signal and generate a logic inversion signal of the first signal.

[0129] In another aspect of the present disclosure, an operating method is disclosed. The operating method includes the following steps: receiving an input signal corresponding to a first voltage source; generating a bias voltage based on the input signal and using the first voltage source; providing the bias voltage to a protection transistor of a level conversion circuit, the level conversion circuit being electrically coupled to a second voltage source having a second voltage, the second voltage being greater than a first voltage of the first voltage source; and generating an output voltage based on the bias voltage, the bias voltage being the second voltage or a ground voltage.

[0130] In some embodiments of the operating method, the operating method further includes the following steps: generating a second bias voltage based on the input signal and using a first voltage source; and providing the second bias voltage to a second protection transistor of the level conversion circuit.

[0131] In another aspect of the present disclosure, a semiconductor device is disclosed, comprising a level conversion circuit and a bias generation circuit. The level conversion circuit comprises a protection transistor. The bias generation circuit is coupled to the level conversion circuit, wherein the bias generation circuit is used to: receive an input signal corresponding to a first voltage source; generate a bias voltage based on the input signal and using the first voltage source; and provide the bias voltage to the protection transistor of the level conversion circuit. The level conversion circuit is electrically coupled to a second voltage source having a second voltage, the second voltage being greater than the first voltage of the first voltage source, and the level conversion circuit is used to generate an output voltage based on the bias voltage, the bias voltage being the second voltage or the ground voltage.

[0132] As used herein, the terms "about" and "approximately" generally mean plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0133] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: a level conversion circuit for generating an output voltage in a second voltage domain corresponding to an input signal in a first voltage domain, wherein the level conversion circuit comprises at least one thick oxide transistor and one thin oxide transistor; as well as A bias generating circuit is effectively coupled to the level conversion circuit and is used to: generating a bias voltage substantially higher than a voltage of the input signal; as well as The bias voltage is provided to a gate of the thick oxide transistor, so that the level conversion circuit generates the output voltage.

2. The semiconductor device according to claim 1, wherein A first terminal of the thin oxide transistor is electrically coupled to ground, and a second terminal of the thin oxide transistor is electrically coupled to a first terminal of the thick oxide transistor.

3. The semiconductor device according to claim 1, wherein The gate of the thick oxide transistor and a gate of the thin oxide transistor are electrically coupled to the bias voltage generating circuit via a first capacitor and a second capacitor respectively.

4. The semiconductor device according to claim 1, wherein: The bias voltage generating circuit is electrically coupled to a first voltage source of the first voltage domain, and the level conversion circuit is electrically coupled to a second voltage source of the second voltage domain.

5. The semiconductor device according to claim 1, wherein in: The level shifting circuit further comprises a second thick oxide transistor and a second thin oxide transistor; and The bias generating circuit generates a second bias voltage.

6. A semiconductor circuit, characterized in that: Include: a first capacitor having a first terminal coupled to a first signal; a second capacitor having a first terminal coupled to a source of a logic inverted signal of the first signal; a first NMOS transistor and a second NMOS transistor, a gate of the first NMOS transistor is coupled to a source voltage of the second NMOS transistor, a gate of the second NMOS transistor is coupled to a source voltage of the first NMOS transistor, a drain of the first NMOS transistor and a drain of the second NMOS transistor are coupled to a power supply voltage; a third NMOS transistor and a fourth NMOS transistor, a gate and a drain of the third NMOS transistor and a gate and a drain of the fourth NMOS transistor coupled to the power supply voltage, a source of the first NMOS transistor and a source of the third NMOS transistor respectively coupled to a voltage at a second terminal of the first capacitor, a source of the second NMOS transistor and a source of the fourth NMOS transistor respectively coupled to a voltage at a second terminal of the second capacitor, In response to the first signal being in a first logic state, the semiconductor circuit generates a bias output voltage at the second terminal of the second capacitor or at the second terminal of the first capacitor.

7. The semiconductor circuit according to claim 6, wherein: Also included is a level converter, the level converter comprising: a first PMOS transistor and a second PMOS transistor, a source of the first PMOS transistor and a source of the second PMOS transistor are coupled to a second power supply voltage greater than the power supply voltage, a gate of the first PMOS transistor is coupled to a drain voltage of the second PMOS transistor, and a gate of the second PMOS transistor is coupled to a drain voltage of the first PMOS transistor.

8. The semiconductor circuit according to claim 7, wherein: The level converter further comprises: a fifth NMOS transistor, a drain of the fifth NMOS transistor being coupled to the drain voltage of the first PMOS transistor; a sixth NMOS transistor, a drain of the sixth NMOS transistor being coupled to a source voltage of the fifth NMOS transistor, and a source of the sixth NMOS transistor being coupled to a ground voltage; a seventh NMOS transistor, a drain of the seventh NMOS transistor being coupled to the drain voltage of the second PMOS transistor; and an eighth NMOS transistor, a drain of the eighth NMOS transistor is coupled to a source voltage of the seventh NMOS transistor, and a source of the eighth NMOS transistor is coupled to the ground voltage.

9. The semiconductor circuit according to claim 8, characterized in that in: The semiconductor circuit generates the bias output voltage at the second terminal of the first capacitor; A gate of the seventh NMOS transistor is coupled to the bias output voltage at the second terminal of the first capacitor; and A gate of the eighth NMOS transistor is coupled to a logic in-phase signal of the first signal.

10. A semiconductor device, characterized in that: Include: a level conversion circuit, comprising a protection transistor; and A bias generating circuit is coupled to the level conversion circuit, wherein the bias generating circuit is used to: receiving an input signal corresponding to a first voltage source; Generating a bias voltage based on the input signal and using the first voltage source; and providing the bias voltage to the protection transistor of the level conversion circuit, The level conversion circuit is electrically coupled to a second voltage source having a second voltage, the second voltage being greater than a first voltage of the first voltage source, and the level conversion circuit is used to generate an output voltage based on the bias voltage, the bias voltage being the second voltage or a ground voltage.

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