Semiconductor structure and semiconductor device

Abstract

The utility model provides a semiconductor structure and a semiconductor device. The semiconductor structure comprises a substrate; the drift region is arranged in the substrate, and a first doped region is arranged in the drift region; the body region is arranged in the substrate, the body region is connected to the drift region and forms a first PN junction, and a second PN junction is arranged in the body region; the isolation structure is arranged on the substrate and covers part of the drift region, one surface, close to the body region, of the isolation structure is a slope surface, and the height of the slope surface is increased in the direction away from the body region. The utility model provides a semiconductor structure and a semiconductor device, so as to improve the semiconductor manufacturing efficiency, reduce the manufacturing cost and reduce the on-resistance of the device.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a semiconductor device. Background Art

[0002] When a semiconductor field effect transistor is started, the resistance between the source and drain is called the on-resistance. The smaller the on-resistance, the smaller the power loss of the device. In semiconductor devices, setting lateral high voltage and low on-resistance can greatly reduce the surface electric field. This technology is used to form high-voltage and highly integrated semiconductor devices.

[0003] Lapping the gate end onto the isolation structure to form a gate field plate can increase the terminal voltage of the gate field plate, which is conducive to achieving a better RESURF effect. In order to achieve a better RESURF effect, there is room for further optimization of the on-resistance and lateral electric field distribution of semiconductor devices. Utility Model Content

[0004] The purpose of the utility model is to provide a semiconductor structure and a semiconductor device to improve semiconductor manufacturing efficiency, reduce manufacturing costs, and reduce the on-resistance of the device.

[0005] In order to solve the above technical problems, the utility model is achieved through the following technical solutions:

[0006] The utility model provides a semiconductor structure, comprising:

[0007] substrate;

[0008] A drift region is arranged in the substrate, wherein a first doping region is arranged in the drift region;

[0009] a body region, disposed in the substrate, the body region being connected to the drift region and forming a first PN junction, wherein a second PN junction is disposed in the body region; and

[0010] An isolation structure is disposed on the substrate and covers a portion of the drift region, wherein a surface of the isolation structure close to the body region is a slope surface, and the height of the slope surface increases along a direction away from the body region.

[0011] In an embodiment of the present invention, the semiconductor structure further comprises a gate oxide layer, which is disposed on the substrate and the isolation structure, covers the slope surface of the isolation structure, and one side of the gate oxide layer extends onto the body region.

[0012] In an embodiment of the present invention, the semiconductor structure includes a polysilicon layer, and the polysilicon layer is disposed on the gate oxide layer, wherein portions of the gate oxide layer and the polysilicon layer located on the surface of the substrate form a gate structure.

[0013] In an embodiment of the present invention, the second PN junction includes a second doping region, the doping ion type of the second doping region is the same as the ion doping type of the first doping region, and the surface of the second doping region is connected to the gate oxide layer.

[0014] In an embodiment of the present invention, the second PN junction includes a third doped region connected to a side of the second doped region away from the drift region, wherein the third doped region and the second doped region have different doping ion types.

[0015] In one embodiment of the present invention, the drift region includes a first region and a second region in which the first doping region is disposed, the surface of the second region is higher than the surface of the first region, and the second region is far away from the body region, and the side of the isolation structure opposite to the slope surface is adjacent to the second region.

[0016] In an embodiment of the present invention, a surface of the isolation structure is higher than the second area.

[0017] In an embodiment of the present invention, the surface of the first region is flush with the surface of the body region and the bottom surface of the isolation structure.

[0018] In an embodiment of the present invention, a side wall of the isolation structure adjacent to the second region is a slope structure or a curved structure.

[0019] The present invention provides a semiconductor device, comprising at least:

[0020] A semiconductor structure as described above, comprising a first doped region and a second PN junction;

[0021] A dielectric layer covering the semiconductor structure;

[0022] a contact column, passing through the dielectric layer and connected to the second PN junction and the first doped region; and

[0023] The metal layer is disposed on the dielectric layer, and the metal layer is connected to the contact pillar.

[0024] As described above, the utility model provides a semiconductor structure and a semiconductor device that can withstand lateral high voltage and has a low surface electric field, and is suitable for forming an LDMOS device. And under the premise of the same breakdown voltage, the semiconductor structure and semiconductor device provided by the utility model have a higher space utilization rate, and therefore have both lower on-resistance and lower manufacturing cost. The isolation structure in the semiconductor structure provided by the utility model forms a slope field plate, which has a better lateral electric field distribution, and under the same breakdown voltage, the accumulation effect of the semiconductor structure is better, a lower on-resistance is obtained, and a better RESURF effect can be achieved.

[0025] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for describing the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 FIG. 1 is a schematic diagram of a semiconductor structure in an embodiment of the present invention.

[0028] Figure 2 FIG. 4 is a schematic diagram of a semiconductor structure in another embodiment of the present invention.

[0029] Figure 3 It is a structural schematic diagram of the concave portion in one embodiment of the utility model.

[0030] Figure 4 It is a schematic diagram of an isolation structure formed by deposition in one embodiment of the utility model.

[0031] Figure 5 It is a schematic diagram of forming a drift region in one embodiment of the utility model.

[0032] Figure 6 It is a schematic diagram of etching to form an isolation structure in one embodiment of the utility model.

[0033] Figure 7 It is a schematic diagram of the structure of the gate oxide layer and the polysilicon layer in one embodiment of the utility model.

[0034] Figure 8 It is a schematic structural diagram of a semiconductor device in one embodiment of the utility model.

[0035] Fig. 9 It is a schematic structural diagram of a semiconductor device in another embodiment of the utility model.

[0036] In the figure: 100, substrate; 101, drift region; 101a, first region; 101b, second region; 102, body region; 103, recess; 104, first doped region; 105, second doped region; 106, third doped region; 110, first photoresist pattern; 111, second photoresist pattern; 112, third photoresist pattern; 200, isolation structure; 300, gate oxide layer; 400, polysilicon layer; 500, dielectric layer; 600, contact pillar; 601, metal layer. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0038] LDMOS devices (Laterally-Diffused Metal-Oxide Semiconductor) are used in high-voltage power integrated circuits to meet the requirements of high-voltage resistance and power control. In addition, LDMOS devices are widely used in radio frequency power circuits. In semiconductor devices, multiple active areas can be isolated on a wafer or substrate through structures such as shallow trench isolation (Shallow Trench Isolation, STI) and local oxidation of silicon isolation (Local Oxidation of Silicon, LOCOS), thereby providing a formation environment for a highly integrated chip structure. The semiconductor structure provided by the utility model can be used to form an LDMOS device, and while having low on-resistance and low mask cost, it can withstand lateral high voltage.

[0039] See also Figure 1 and Figure 2As shown, the utility model provides a semiconductor structure. In the utility model, the semiconductor structure includes a substrate 100, a drift region 101 and a body region 102. Wherein, the substrate 100 is, for example, a silicon substrate for forming a semiconductor structure. The substrate 100 may include a substrate and a silicon layer arranged above the substrate, and the substrate is, for example, a semiconductor substrate material such as silicon (Si), silicon carbide (SiC), sapphire (Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), etc., and the silicon layer is formed above the substrate. The utility model does not limit the material and thickness of the substrate 100. Wherein, the drift region 101 and the body region 102 are arranged in the substrate 100. The drift region 101 and the body region 102 are adjacent, and the drift region 101 is connected to the body region 102 and forms a first PN junction. Specifically, the drift region 101 is an N-type doped region, and the doped ions are, for example, phosphorus ions. The body region 102 is a P-type doped region, and the doped ions are, for example, boron ions. A second PN junction is provided in the body region 102 to form a first electrode, and a first doped region 104 is provided in the drift region 101 to form a second electrode. Voltage is applied between the first doped region 104 and the second PN junction to form a current. In the present invention, the current flow path is horizontal, and there is no obstruction on the current flow path, such as Figure 1 and Figure 2 As indicated by the arrow.

[0040] See also Figure 1 and Figure 2 As shown, in one embodiment of the utility model, the second PN junction includes a second doping region 105 and a third doping region 106. The second doping region 105 and the third doping region 106 are adjacent and connected to form a second PN junction. The doping type of the second doping region 105 is the same as the doping ion of the first doping region 104, and the doping ion concentration of the first doping region 104 and the second doping region 105 can be the same. Specifically, the second doping region 105 is an N-type doping region. The third doping region 106 is connected to a side of the second doping region 105 away from the first doping region 104. The doping ion types of the third doping region 106 and the second doping region 105 are different. Specifically, the third doping region 106 is a P-type doping region. A current flow path is formed between the second doping region 105 and the first doping region 104.

[0041] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, the drift region 101 includes a first region 101a and a second region 101b. Among them, the second region 101b is arranged on the first region 101a, so that the height of the first doped region 104 is higher than the first region 101a. This structure eliminates the curvature effect of the drain, so that the depth of the drain injection does not destroy the charge balance between the drift region and the substrate, so that the LDMOS device can achieve a better RESURF effect, obtain a better breakdown voltage and a lower on-resistance. In the present invention, the body region 102 is flush with the top surface of the first region 101a. And the first region 101a is adjacent to the body region 102. Specifically, the first region 101a is connected to the body region 102 and forms a first PN junction. The present invention does not limit the thickness of the body region 102 and the first region 101a. It should be noted that, Figure 1 and Figure 2 The thickness of the body region 102 and the first region 101a shown in FIG. 1 is equal, which is only one embodiment of the present invention. In one embodiment of the present invention, the side wall of the second region 102 close to the body region 102 is a plane, such as Figure 1 In another embodiment of the present invention, the sidewall of the second region 102 close to the body region 102 is a curved surface, such as Figure 2 As shown. The first doping region 104 is arranged in the second region 101b, and the surface of the first doping region 104 is flush with the surface of the second region 101b, so as to facilitate the subsequent formation of the electrical interconnection structure of the device. The second doping region 105 and the third doping region 106 are arranged side by side, and the top surfaces of the second doping region 105 and the third doping region 106 are flush with the surface of the first region 101a. Therefore, in the present utility model, the first doping region 104 is higher than the second doping region 105 and the third doping region 106.

[0042] See also Figure 1 and Figure 2As shown, in the present invention, the semiconductor structure includes an isolation structure 200, wherein the isolation structure 200 is arranged on the substrate 100. In the present invention, the isolation structure 200 covers part of the drift region 101, and the isolation structure 200 does not cover the body region 102, so as to ensure that the device threshold voltage is not too large and affects the switching response speed of the semiconductor device. Specifically, the isolation structure 200 covers part of the first region 101a, and the isolation structure 200 is connected to the side wall of the second region 101b. The side of the isolation structure 200 close to the body region 102 is a slope surface, and the height of the slope surface increases along the direction close to the drift region 101. The side of the isolation structure 200 opposite to the slope surface is adjacent to the second region 101b. And the bottom surface of the isolation structure 200 is flush with the surface of the second PN junction, and the first doped region 104 is located on the side of the isolation structure 200. When the first electrode and the second electrode are turned on, the current directly passes from the bottom of the isolation structure 200 along the bottom surface of the isolation structure 200, and the current path does not need to be detoured, so the current path is greatly shortened, achieving a lower on-resistance. And through the slope surface or arc surface with increasing height, it can withstand higher lateral voltage. Under the same breakdown voltage, the semiconductor structure of the utility model has a low on-resistance. It should be noted that in an embodiment of the utility model, the isolation structure 200 is a shallow trench isolation structure, such as Figure 1 In another embodiment of the present invention, the isolation structure 200 is a silicon local oxidation isolation structure, such as Figure 2 shown.

[0043] See also Figure 1 and Figure 2 As shown, in the present invention, the semiconductor structure includes a gate oxide layer 300, and the gate oxide layer 300 is disposed on the substrate 100 and the isolation structure 200. The gate oxide layer 300 covers the slope surface of the isolation structure 200, and one side of the gate oxide layer 300 extends to the second PN junction. Specifically, one side of the gate oxide layer 300 extends to the second doped region 105, and the gate oxide layer 300 is connected to the second doped region 105. The other side of the gate oxide layer 300 extends to the top of the isolation structure 200 to ensure that the gate oxide layer 300 can completely cover the slope surface of the isolation structure 200. In the present invention, as shown in FIG. Figure 1 and Figure 2 As shown, the gate oxide layer 300 is partially located on the substrate 100 , partially located on the slope surface of the isolation structure 200 , and partially located on the top of the isolation structure 200 .

[0044] See also Figure 1 and Figure 2As shown, in the present invention, the semiconductor structure includes a polysilicon layer 400. The polysilicon layer 400 is disposed on the gate oxide layer 300. The portion of the gate oxide layer 300 and the polysilicon layer 400 located on the surface of the substrate 100 form a gate structure. When a voltage is applied to the polysilicon layer 400, the first PN junction and the second PN junction can be activated, thereby forming a current path between the first electrode and the second electrode. In the present invention, the polysilicon layer 400 is completely formed on the surface of the gate oxide layer 300.

[0045] See also Figure 8 and Fig. 9 As shown, the semiconductor device provided by the utility model is based on the semiconductor structure provided by the utility model. The semiconductor device includes a dielectric layer 500, a contact column 600 and a metal layer 601. The dielectric layer 500 covers the semiconductor structure. Specifically, the dielectric layer 500 is arranged on the substrate 100, the polysilicon layer 400 and the partial isolation structure 200. The dielectric layer 500 can be silicon oxide. In the utility model, the contact column 600 is arranged in the dielectric layer 500. One end of the contact column 600 is connected to the first doping region 104, the second doping region 105 and the third doping region 106. The other end of the contact column 600 is connected to the metal layer 601. The metal layer 601 is arranged on the dielectric layer 500. The metal layer 601 is the first layer of metal of the metal interconnection structure of the integrated circuit. And the utility model does not limit the material of the metal layer 601.

[0046] See also Figure 3 and Figure 4As shown, according to the semiconductor structure and semiconductor device provided by the utility model, not only can the on-resistance be reduced, but also the mask cost can be saved, and the process economy is relatively high. In the step of forming the semiconductor structure, a substrate 100 is first provided, and then a first photoresist pattern 110 is formed on the substrate 100. Photoresist can be spin-coated on the substrate 100 to form a photoresist layer, and the photoresist layer can be patterned by exposure etching and the like to form a first photoresist pattern 110. The first photoresist pattern 110 covers the substrate 100, and specifically covers the area where the recess 103 is not formed. Then, the silicon material of a portion of the substrate 100 is removed by wet etching or dry etching, thereby forming a recess 103 on the substrate 100. At this time, the recess 103 has separated the second area 101b in the substrate 100. Then, under the premise that the first photoresist pattern 110 is not removed, the recess 103 is filled by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) to form an isolation structure 200. In order to ensure that the isolation structure 200 can fill the recess 103, the recess 103 is overfilled so that the surface of the isolation structure 200 is higher than the surface of the second region 101b. In addition, the surface of the isolation structure 200 is higher than the surface of the second region 101b, which can leave a consumption margin of the oxidized material for the subsequent acid etching process, thereby ensuring that the gate structure can reach a preset shape. After the isolation structure 200 is formed, the first photoresist pattern 110 is removed.

[0047] See also Figures 4 to 6 As shown, in the step of forming the semiconductor structure, a second photoresist pattern 111 is formed on the isolation structure 200. And, using the second photoresist pattern 111 as a mask, the first type of ions are injected into the substrate 100 to form the drift region 101. At this time, the drift region 101 is naturally divided into a first region 101a and a second region 101b. Among them, the second photoresist pattern 111 is arranged in an area where the drift region 101 is not prepared to be formed. After the drift region 101 is formed, the second photoresist pattern 111 is removed. And then a third photoresist pattern 112 is formed on the substrate 100 and on part of the isolation structure 200. Among them, the third photoresist pattern 112 covers the second region 101b. The utility model does not limit the coverage area of ​​the third photoresist pattern 112 on the isolation structure 200. Using the third photoresist pattern 112 as a mask, the isolation structure 200 is etched, part of the isolation structure 200 is removed, and the slope surface a of the isolation structure 200 is formed. The isolation structure 200 formed after etching covers part of the drift region 101. Then, with the assistance of a mask, the second type of ions are implanted into the substrate 100 to form a body region 102. The mask shields the exposed drift region 101. Then, the third photoresist pattern 112 is removed.

[0048] See also Figure 6 and Figure 7 As shown, in the step of forming the semiconductor structure, a gate oxide layer 300 is then formed on the substrate 100 and the isolation structure 200. Specifically, the gate oxide layer 300 is formed on the substrate 100 and the isolation structure 200 by chemical vapor deposition, wherein the gate oxide layer 300 covers the substrate 100 and the isolation structure 200. Then, a polysilicon layer 400 is formed on the gate oxide layer 300 by chemical vapor deposition. The polysilicon layer 400 covers the gate oxide layer 300. Then, the gate oxide layer 300 and the polysilicon layer 400 are patterned by dry etching to form a structure as shown in FIG. Figure 7 The gate oxide layer 300 and the polysilicon layer 400 are shown. The portion of the isolation structure 200 that is higher than the second region 101b can be used as the etching margin of the polysilicon layer 400 etching process to ensure that the second region 101b will not be damaged when the polysilicon 400 is etched cleanly, so that the gate structure can reach the expected shape and avoid short circuit of the device. The gate oxide layer 300 is partially located on the substrate 100, partially located on the slope surface of the isolation structure 200, and partially located on the top of the isolation structure 200. One side of the gate oxide layer 300 extends to the second doped region 105, and the gate oxide layer 300 is connected to the second doped region 105. The other side of the gate oxide layer 300 extends to the top of the isolation structure 200 to ensure that the gate oxide layer 300 can completely cover the slope surface of the isolation structure 200. The patterned polysilicon layer 400 covers the gate oxide layer 300.

[0049] See also Figures 1 to 9 As shown, the steps of the semiconductor structure provided by the utility model can be used to form the shallow trench isolation structure in one embodiment of the utility model, and can also be used to form the silicon local oxidation structure in another embodiment of the utility model. When forming the isolation structure 200 with the slope surface a, only a single mask structure of the third photoresist pattern 112 is required to complete the setting of the isolation structure 200, so the mask cost is greatly reduced. Among them, the semiconductor device formed based on the semiconductor structure provided by the utility model can achieve the effect of reducing the mask cost and reducing the surface electric field of the device.

[0050] The embodiments of the utility model disclosed above are only used to help illustrate the utility model. The embodiments do not describe all the details in detail, nor do they limit the utility model to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the utility model, so that technicians in the relevant technical field can well understand and use the utility model. The utility model is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A drift region is arranged in the substrate, wherein a first doping region is arranged in the drift region; A body region, arranged in the substrate, the body region is connected to the drift region and forms a first PN junction, wherein a second PN junction is arranged in the body region; as well as An isolation structure is disposed on the substrate and covers a portion of the drift region, wherein a surface of the isolation structure close to the body region is a slope surface, and the height of the slope surface increases along a direction away from the body region.

2. A semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises a gate oxide layer, which is arranged on the substrate and the isolation structure, covers the slope surface of the isolation structure, and one side of the gate oxide layer extends to the body region.

3. A semiconductor structure according to claim 2, characterized in that: The semiconductor structure comprises a polysilicon layer, and the polysilicon layer is arranged on the gate oxide layer, wherein a portion of the gate oxide layer and the polysilicon layer located on the surface of the substrate forms a gate structure.

4. A semiconductor structure according to claim 2, characterized in that: The second PN junction includes a second doping region, the doping ion type of the second doping region is the same as the ion doping type of the first doping region, and the surface of the second doping region is connected to the gate oxide layer.

5. A semiconductor structure according to claim 4, characterized in that: The second PN junction includes a third doping region connected to a side of the second doping region away from the drift region, wherein the third doping region and the second doping region have different doping ion types.

6. A semiconductor structure according to claim 1, characterized in that: The drift region includes a first region and a second region provided with the first doping region, the surface of the second region is higher than the surface of the first region and the second region is far away from the body region, and the side of the isolation structure opposite to the slope surface is adjacent to the second region.

7. A semiconductor structure according to claim 6, characterized in that: A surface of the isolation structure is higher than the second region.

8. A semiconductor structure according to claim 6, characterized in that: A surface of the first region is flush with a surface of the body region and a bottom surface of the isolation structure.

9. A semiconductor structure according to claim 6, characterized in that: The side wall of the isolation structure adjacent to the second region is a slope structure or a curved structure.

10. A semiconductor device, characterized in that: At least: A semiconductor structure according to any one of claims 1 to 9, comprising a first doped region and a second PN junction; A dielectric layer covering the semiconductor structure; A contact column, passing through the dielectric layer and connected to the second PN junction and the first doped region; as well as The metal layer is disposed on the dielectric layer, and the metal layer is connected to the contact pillar.

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