Chip packaging structure
By designing the crystal-setting area of the inclined buffer zone and flat flip zone on the substrate, the problems of insufficient filling and spillage in the bottom filler in traditional chip packaging are solved, and the connection of the heat dissipation cover is improved by increasing the use of adhesive glue. strength.
Patent Information
- Application Number
- CN202421189750.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-28
- Publication Date
- 2025-02-11
- Estimated Expiration
- 2034-05-28
AI Technical Summary
Traditional chip packaging methods are prone to wrap bubbles and hollows during the process of colloid flow during large-size or dense solder joints, and the problems of underfilling spillage and contamination of nearby components.
A chip packaging structure is designed, including a crystal-setting region and a non-setting region on the substrate, with a slanted buffer zone and a flat flip zone, forming a height difference to sufficiently fill the underfill and by The crystal area is equipped with grooves connecting the heat dissipation cover and is filled with adhesive to improve the connection strength.
Full underfill filling around the chip is achieved, which avoids overflow of underfill, improves the connection strength between the plastic seal body and the heat dissipation cover, and prevents degumming at the connection between the heat dissipation cover and the substrate.
Smart Images
Figure CN222462896U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of chip packaging, in particular to a chip packaging structure. Background Art
[0002] The traditional chip packaging method is to weld or paste the chip and components on the substrate, and then fill the bottom by dispensing glue from the side of the chip. The colloid is filled between the chip and the substrate by the capillary action of the liquid, and then cured at high temperature. The bottom filler plays a role in protecting the welding points and fixing the support. However, when filling large-sized chips or chips with dense solder joints, it is easy to wrap bubbles and form voids during the flow of the colloid. There is also the problem of overflow of the bottom filler and contamination of nearby components.
[0003] Therefore, how to improve the filling effect of chip underfill, avoid voids, and prevent underfill overflow is a problem that needs to be solved at present. Summary of the invention
[0004] The technical problem to be solved by the utility model is how to improve the filling effect of chip bottom filler, avoid the occurrence of voids, prevent the bottom filler from overflowing, and provide a chip packaging structure.
[0005] In order to solve the above problems, the utility model provides a chip packaging structure, including: a substrate, the upper surface of the substrate includes a crystal placement area and a non-crystal placement area located outside the crystal placement area, the crystal placement area includes a flip-chip area and a buffer zone, the buffer zone connects the flip-chip area and the non-crystal placement area, and the upper surface of the substrate is recessed inward to form an inclined buffer zone and a flat flip-chip area, the surface of the flip-chip area is lower than the surface of the non-crystal placement area; a chip stacking structure, flipped on the flip-chip area; and a bottom filling layer, at least filling between the chip stacking structure and the flip-chip area.
[0006] In some embodiments, the buffer region is a slope extending from the flip chip region to the non-chip region.
[0007] In some embodiments, the buffer zone has an inclination angle of 1° to 5°.
[0008] In some embodiments, the buffer region is in a step shape extending from the flip-chip region to the non-chip region.
[0009] In some embodiments, the underfill layer is filled between the chip stacking structure and the die-placement area, and the upper surface of the underfill layer is flush with the surface of the non-die-placement area.
[0010] In some embodiments, a plastic encapsulation layer is further included, covering the upper surface of the substrate, the chip stacking structure, and the bottom filling layer, and the surface of the chip stacking structure away from the substrate is exposed to the plastic encapsulation layer.
[0011] In some embodiments, the chip packaging structure further includes a heat dissipation cover, and the heat dissipation cover covers the upper surface and side surfaces of the plastic packaging layer.
[0012] In some embodiments, the surface of the non-crystal region further has a groove, and the heat dissipation cover includes a connecting portion extending toward the substrate, and an end of the connecting portion close to the substrate is disposed in the groove.
[0013] In some embodiments, the bottom of the groove is higher than or flush with the surface of the flip chip area.
[0014] In some embodiments, an adhesive is disposed in the groove, and an end of the connecting portion close to the substrate is fixed in the groove by the adhesive.
[0015] In some embodiments, the surface of the chip stacking structure away from the substrate is connected to the heat dissipation cover via heat dissipation adhesive.
[0016] The above technical solution sets a die-placement area with an inclined buffer zone and a flat flip-chip area on the upper surface of the substrate, so that the surface of the die-placement area is lower than the non-die-placement area. The height difference formed can be fully filled when the underfill is filled around the chip. The existence of the buffer zone also avoids the overflow of the underfill. A groove connected to the heat dissipation cover is further provided in the non-die-placement area, and the groove is filled with adhesive, which can improve the connection strength between the plastic package and the heat dissipation cover and prevent debonding at the connection between the heat dissipation cover and the substrate.
[0017] It should be understood that the above general description and the detailed description below are only exemplary and explanatory and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but in appropriate cases, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the specific implementation of the utility model, the following is a brief introduction to the drawings required for the description of the specific implementation. Obviously, the drawings described below are only some specific implementations of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0019] Figure 1A It is a structural schematic diagram of the first embodiment of the chip packaging structure of the present invention.
[0020] Figure 1B It is a structural schematic diagram of the second embodiment of the chip packaging structure of the present invention.
[0021] Figure 2 It is a structural schematic diagram of the third embodiment of the chip packaging structure of the present invention.
[0022] Figure 3 It is a structural schematic diagram of a fourth embodiment of the chip packaging structure of the present invention.
[0023] Figure 4 It is a schematic structural diagram of the metal wiring layer of the utility model. DETAILED DESCRIPTION
[0024] The technical scheme in the embodiment of the utility model will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.
[0025] See also Figure 1A , which is a schematic diagram of the structure of the first embodiment of the chip packaging structure of the utility model. Figure 1A As shown, the chip packaging structure includes: a substrate 11, a chip stacking structure 12, and an underfill layer 13. The upper surface S1 of the substrate 11 includes a crystal region 111 and a non-crystal region 112 located outside the crystal region 111. The crystal region 111 includes a flip-chip region 114 and a buffer region 113. The buffer region 113 connects the flip-chip region 114 and the non-crystal region 112. The upper surface S1 of the substrate 11 is recessed inward to form an inclined buffer region 113 and a flat flip-chip region 114. The surface of the flip-chip region 114 is lower than the surface of the non-crystal region 112. The chip stacking structure 12 is flipped on the flip-chip region 114. The underfill layer 13 is at least filled between the chip stacking structure 12 and the flip-chip region 114.
[0026] The above technical solution sets a crystal placement area with an inclined buffer zone and a flat flip-chip area on the upper surface of the substrate, so that the surface of the crystal placement area is lower than the non-crystal placement area. The height difference formed can be fully filled when the bottom fill is filled around the chip. The existence of the buffer zone also avoids overflow of the bottom fill.
[0027] Specifically, the substrate 11 is a redistribution layout (RDL) substrate. The redistribution layout substrate includes a metal layer 119 and a dielectric layer 118 between each of the metal layers 119. The redistribution layout technology uses a multi-layer polyimide layer with photosensitive properties as the dielectric layer 118 between each of the metal layers 119. The stacked wiring structure needs to go through multiple process steps such as coating, exposure, development, and curing during the photolithography process, and utilizes the excellent electrical insulation performance of polyimide to achieve the transfer of the original pressure point of the chip. Figure 4 As shown, taking two layers of metal wiring as an example, metal layers 411, 412 and dielectric layers 421, 422, 423, 424 are cross-overlapped and distributed, and the dielectric layer isolates the upper and lower adjacent metal layers 411 and 412. The metal layer lateral portion of metal layer 411 is located within dielectric layer 422 and is located above dielectric layer 421, the metal layer longitudinal portion of metal layer 411 penetrates dielectric layer 421, the metal layer lateral portion of metal layer 412 is located within dielectric layer 424 and is located above dielectric layer 423, and the metal layer longitudinal portion of metal layer 412 penetrates dielectric layer 423 and is connected to the metal layer lateral portion of metal layer 411.
[0028] As shown in FIG1 , the thickness of the dielectric layer 118 of the flip-chip area 114 is set to be smaller than the thickness of the dielectric layer 118 of the non-crystal area 112, so as to form a height difference between the flip-chip area 114 and the surface of the non-crystal area 112. The height difference formed can fully fill the bottom fill when the bottom fill is filled around the chip. At the same time, the buffer zone 113 is set so that the thickness of the dielectric layer 118 gradually increases in the direction close to the non-crystal area 112, which also avoids the overflow of the bottom fill.
[0029] In some embodiments, the buffer region 113 is a slope extending from the flip-chip region 114 to the non-chip region 112 .
[0030] In some embodiments, the inclination angle of the buffer zone 113 is 1° to 5°. In this embodiment, the inclination angle of the buffer zone 113 is 5°. In other embodiments, the inclination angle of the buffer zone 113 may also be 1° or 3°.
[0031] In some embodiments, the bottom filling layer 13 is filled between the chip stacking structure 12 and the crystal area 111, and the upper surface of the bottom filling layer 13 is flush with the surface of the non-crystal area 112. While ensuring that the bottom filling between the chip stacking structure 12 and the crystal area 111 is fully filled, it can also accommodate excess bottom filling to prevent the bottom filling from overflowing into the non-crystal area 112 and interfering with the connectivity of other circuits. In other embodiments, on the premise of ensuring that the bottom filling between the chip stacking structure 12 and the crystal area 111 is fully filled, the surface of the bottom filling layer 13 can also be lower than the surface of the non-crystal area 112 to prevent the bottom filling from overflowing.
[0032] In some embodiments, a plastic encapsulation layer 14 is further included, covering the upper surface S1 of the substrate 11 , the chip stacking structure 12 , and the bottom filling layer 13 , and the surface of the chip stacking structure 12 away from the substrate 11 is exposed to the plastic encapsulation layer 14 .
[0033] In some embodiments, the chip stacking structure 12 includes multiple first chips 120, and the multiple first chips 120 are connected by micro bumps 18; micro bumps 18 are also arranged between the chip stacking structure 12 and the flip-chip area 114; and the lower surface S2 of the substrate 11 is also provided with multiple solder balls 15 for connecting to external circuits.
[0034] See also Figure 1B , which is a schematic diagram of the structure of the second embodiment of the chip packaging structure of the utility model. Figure 1B As shown, the chip packaging structure includes: an adapter plate 19, a chip stacking structure 12, a second chip 122, and an underfill layer 13. The upper surface S1 of the adapter plate 19 includes a plurality of crystal-setting areas 191 and a non-crystal-setting area 192 located outside the crystal-setting area 191. The crystal-setting area 191 includes a flip-chip area 194 and a buffer area 193. The buffer area 193 connects the flip-chip area 194 and the non-crystal-setting area 192. The upper surface S1 of the substrate 19 is recessed inward to form an inclined buffer area 193 and a flat flip-chip area 194. The surface of the flip-chip area 194 is lower than the surface of the non-crystal-setting area 192. The chip stacking structure 12 and the second chip 122 are flip-chipped on the flip-chip areas 194 of different crystal-setting areas 191, respectively. The underfill layer 13 is at least filled between the chip stack 12 and the flip-chip area 194 and between the second chip 122 and the flip-chip area 194.
[0035] In some embodiments, the chip stacking structure 12 includes a plurality of first chips 120, wherein the first chip 120 is a memory chip, such as a dynamic random access memory chip (DRAM) chip or a static random access memory chip (SRAM) chip. The second chip 122 is a logic chip, such as a central processing unit (CPU) chip or a graphics processing unit (GPU) chip. The chip packaging structure of this embodiment can be applied to high-bandwidth memory (HBM) packaging.
[0036] See also Figure 2 , which is a schematic diagram of the structure of the third embodiment of the chip packaging structure of the utility model. Figure 2 As shown, the chip packaging structure includes: a substrate 21, a chip stacking structure 22, and an underfill layer 23. The upper surface S1 of the substrate 21 includes a crystal region 211 and a non-crystal region 212 located outside the crystal region 211. The crystal region 211 includes a flip-chip region 214 and a buffer region 213. The buffer region 213 connects the flip-chip region 214 and the non-crystal region 212. The upper surface S1 of the substrate 21 is recessed inward to form an inclined buffer region 213 and a flat flip-chip region 214. The surface of the flip-chip region 214 is lower than the surface of the non-crystal region 212. The chip stacking structure 22 is flipped on the flip-chip region 214. The underfill layer 23 is at least filled between the chip stacking structure 22 and the flip-chip region 214.
[0037] Figure 2 The embodiment shown is different from the embodiment shown in FIG. 1 in that the buffer zone 213 in the present embodiment is in a stepped shape extending from the flip-chip area 214 to the non-crystal area 212. Specifically, the substrate 21 is a rewiring substrate, including a metal layer 219 and a dielectric layer 218 between each of the metal layers 219. By setting the number of layers of the dielectric layer 218 in the flip-chip area 214 to be smaller than the number of layers of the dielectric layer 218 in the non-crystal area 212, a height difference between the surface of the crystal area 211 and the non-crystal area 212 is formed, and the edge of the dielectric layer 218 higher than the flip-chip area 214 is arranged in a stepped shape in the buffer zone 213, and the height of the step is the thickness of the dielectric layer 218. The height difference formed can fully fill the bottom fill when the bottom fill is filled around the chip, and also avoid the overflow of the bottom fill.
[0038] In some embodiments, the bottom filling layer 23 is filled between the chip stacking structure 22 and the crystal area 211, and the upper surface of the bottom filling layer 23 is flush with the surface of the non-crystal area 212. While ensuring that the bottom filling between the chip stacking structure 22 and the crystal area 211 is fully filled, it can also accommodate excess bottom filling to prevent the bottom filling from overflowing into the non-crystal area 212 and interfering with the connectivity of other circuits. In other embodiments, on the premise of ensuring that the bottom filling between the chip stacking structure 22 and the crystal area 211 is fully filled, the surface of the bottom filling layer 23 can also be lower than the surface of the non-crystal area 212 to prevent the bottom filling from overflowing.
[0039] In some embodiments, a plastic encapsulation layer 24 is further included, covering the upper surface S1 of the substrate 21 , the chip stacking structure 22 , and the bottom filling layer 23 , and the surface of the chip stacking structure 22 away from the substrate 21 is exposed to the plastic encapsulation layer 24 .
[0040] In some embodiments, the chip stacking structure 22 includes multiple first chips 220, and the multiple first chips 220 are connected by micro bumps 28; micro bumps 28 are also arranged between the chip stacking structure 22 and the flip-chip area 214; and the lower surface S2 of the substrate 21 is also provided with multiple solder balls 25 for connecting to external circuits.
[0041] See also Figure 3 , which is a schematic diagram of the structure of the fourth embodiment of the chip packaging structure of the utility model. Figure 3 As shown, the chip packaging structure includes: a substrate 31, a chip stacking structure 32, and an underfill layer 33. The upper surface S1 of the substrate 31 includes a crystal region 311 and a non-crystal region 312 located outside the crystal region 311. The crystal region 311 includes a flip-chip region 314 and a buffer region 313. The buffer region 313 connects the flip-chip region 314 and the non-crystal region 312. The upper surface S1 of the substrate 31 is recessed inward to form an inclined buffer region 313 and a flat flip-chip region 314. The surface of the flip-chip region 314 is lower than the surface of the non-crystal region 312. The chip stacking structure 32 is flipped on the flip-chip region 314. The underfill layer 33 is at least filled between the chip stacking structure 32 and the flip-chip region 314.
[0042] Specifically, the substrate 31 is a rewiring substrate, including a metal layer 319 and a dielectric layer 318 between the metal layers 319. The thickness of the dielectric layer 318 in the flip-chip area 314 is set to be smaller than the thickness of the dielectric layer 318 in the non-crystal area 312, so as to form a height difference between the surface of the flip-chip area 314 and the non-crystal area 312. The height difference formed can fully fill the bottom fill when the bottom fill is filled around the chip. At the same time, the buffer zone 313 in which the thickness of the dielectric layer 318 gradually increases in the direction close to the non-crystal area 312 also avoids overflow of the bottom fill.
[0043] In some embodiments, the buffer region 313 is a slope extending from the flip-chip region 314 to the non-chip region 312 .
[0044] In some embodiments, the inclination angle of the buffer zone 313 is 1° to 5°. In this embodiment, the inclination angle of the buffer zone 313 is 5°. In other embodiments, the inclination angle of the buffer zone 313 may also be 1° or 3°.
[0045] In some embodiments, the bottom filling layer 33 is filled between the chip stacking structure 32 and the crystal area 311, and the upper surface of the bottom filling layer 33 is flush with the surface of the non-crystal area 312. While ensuring that the bottom filling between the chip stacking structure 32 and the crystal area 311 is fully filled, it can also accommodate excess bottom filling to prevent the bottom filling from overflowing into the non-crystal area 312 and interfering with the connectivity of other circuits. In other embodiments, on the premise of ensuring that the bottom filling between the chip stacking structure 32 and the flip-chip area 314 is fully filled, the surface of the bottom filling layer 33 can also be lower than the surface of the non-crystal area 312 to prevent the bottom filling from overflowing.
[0046] In some embodiments, a plastic encapsulation layer 34 is further included, covering the upper surface S1 of the substrate 31 , the chip stacking structure 32 , and the bottom filling layer 33 , and the surface of the chip stacking structure 32 away from the substrate 31 is exposed to the plastic encapsulation layer 34 .
[0047] In some embodiments, the chip stacking structure 32 includes a plurality of first chips 320, and the plurality of first chips 320 are connected by micro bumps 38; micro bumps 38 are also provided between the chip stacking structure 32 and the flip-chip area 314; and a plurality of solder balls 35 are also provided on the lower surface S2 of the substrate 31 for connecting to an external circuit. The plurality of first chips 320 may be chips of the same type, and the first chips 320 may be memory chips, for example, each of the first chips 320 is a dynamic random access memory chip, a static random access memory chip, or a magnetoresistive random access memory chip. In other embodiments, the plurality of first chips 320 may include chips of different types. For example, some of the plurality of first chips 320 may be logic chips, and other first chips 320 may be memory chips. For example, each of the logic chips may be a central processing unit chip, a graphics processing unit chip, or an application processor (AP) chip.
[0048] Figure 3 The embodiment shown is different from the embodiment shown in FIG. 1 in that the chip packaging structure in this embodiment further includes a heat dissipation cover 36 , which covers the upper surface S341 and the side surface S340 of the plastic packaging layer 34 to improve the heat dissipation capability of the packaging structure.
[0049] In some embodiments, the surface of the non-crystal region 312 further has a groove 315, and the heat dissipation cover 36 includes a connection portion 360 extending toward the substrate 31, and one end of the connection portion 360 close to the substrate 31 is disposed in the groove 315. The groove 315 is used to enhance the connection strength between the heat dissipation cover 36 and the substrate 31 to prevent the heat dissipation cover 36 from falling off. In this embodiment, the connection portion 360 covers the side of the plastic encapsulation layer 34.
[0050] In some embodiments, the bottom of the groove 315 is higher than or flush with the surface of the flip-chip region 314. In this embodiment, the groove 315 is located in the dielectric layer 318, and the bottom of the groove 315 is higher than the surface of the flip-chip region 314, that is, the depth of the groove 315 is less than or equal to the sinking depth of the die placement region 311, so as to avoid affecting the redistribution layer 319.
[0051] In some embodiments, an adhesive 37 is disposed in the groove 315 , and one end of the connecting portion 360 close to the substrate 31 is fixed in the groove 315 by the adhesive 37 to further enhance the connection strength between the heat dissipation cover 36 and the substrate 31 .
[0052] In some embodiments, the surface of the chip stacking structure 32 away from the substrate 31 is connected to the heat dissipation cover 36 through a heat dissipation adhesive (not shown) to accelerate the heat dissipation speed of the chip stacking structure 32. In other embodiments, the surface of the chip stacking structure 32 away from the adapter substrate 31 can also be directly attached to the heat dissipation cover 36.
[0053] The above technical solution sets a crystal placement area with an inclined buffer zone and a flat flip-chip area on the surface of the substrate, so that the surface of the crystal placement area is lower than the non-crystal placement area. The height difference formed can be fully filled when the bottom fill is filled around the chip. The existence of the buffer zone also avoids overflow of the bottom fill.
[0054] A groove connected to the heat dissipation cover is further opened in the non-crystal area, and the groove is filled with adhesive, which can improve the connection strength between the plastic package body and the heat dissipation cover and prevent the heat dissipation cover from being debonded at the connection with the substrate.
[0055] It should be noted that references in the specification to "an embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.
[0056] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. Similarly, terms such as "one", "a" or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected / coupled" refers not only to the direct coupling of one component to another component, but also to the indirect coupling of one component to another component through an intermediate component.
[0057] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present utility model are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments of the present utility model and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concepts of the present utility model. In the above-mentioned embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.
[0058] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.
Claims
1. A chip packaging structure, characterized in that: include: A substrate, wherein the upper surface of the substrate includes a crystal placement area and a non-crystal placement area located outside the crystal placement area, the crystal placement area includes a flip-chip area and a buffer area, the buffer area connects the flip-chip area and the non-crystal placement area, and the upper surface of the substrate is recessed inward to form an inclined buffer area and a flat flip-chip area, and the surface of the flip-chip area is lower than the surface of the non-crystal placement area; A chip stacking structure is flipped on the flip-chip area; The bottom filling layer is at least filled between the chip stacking structure and the flip-chip area.
2. The chip packaging structure according to claim 1, characterized in that: The buffer zone is a slope extending from the flip-chip zone to the non-chip zone.
3. The chip packaging structure according to claim 2, characterized in that: The inclination angle of the buffer zone is 1° to 5°.
4. The chip packaging structure according to claim 1, characterized in that: The buffer zone is in a step shape extending from the flip-chip zone to the non-crystal zone.
5. The chip packaging structure according to claim 1, characterized in that: The bottom filling layer is filled between the chip stacking structure and the die placement area, and the upper surface of the bottom filling layer is flush with the surface of the non-die placement area.
6. The chip packaging structure according to claim 1, characterized in that: It also includes a plastic encapsulation layer covering the upper surface of the substrate, the chip stacking structure, and the bottom filling layer, and the surface of the chip stacking structure away from the substrate is exposed to the plastic encapsulation layer.
7. The chip packaging structure according to claim 6, characterized in that: The chip packaging structure further includes a heat dissipation cover, and the heat dissipation cover covers the upper surface and the side surface of the plastic packaging layer.
8. The chip packaging structure according to claim 7, characterized in that: The surface of the non-crystal area also has a groove, and the heat dissipation cover includes a connecting portion extending toward the substrate, and an end of the connecting portion close to the substrate is arranged in the groove.
9. The chip packaging structure according to claim 8, characterized in that: The bottom of the groove is higher than or flush with the surface of the flip-chip region.
10. The chip packaging structure according to claim 8, characterized in that: Adhesive is arranged in the groove, and one end of the connecting part close to the substrate is fixed in the groove by the adhesive.