Power converter and photovoltaic system
By designing a timing protection circuit in the power converter, the problem of high PWM protection logic cost and long development cycle of programmable devices in the prior art is solved, and low-cost and efficient dead-band and time-sequence logic protection is achieved.
Patent Information
- Application Number
- CN202421132584.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-23
- Publication Date
- 2025-02-11
- Estimated Expiration
- 2034-05-23
AI Technical Summary
In the prior art, the hardware cost of using programmable devices to implement PWM protection logic is relatively high and the development cycle is long.
A power converter is designed, using a timing protection circuit to receive the initial pulse signal and perform timing adjustments, output the target pulse signal to avoid the switching tube being turned on at the same time, and control the switch action to realize the dead zone and time sequence logic protection function, relying only on simplicity Hardware circuit.
This solution realizes low-cost and efficient deadband and time-sequence logic protection in ANPC three-level topology circuits, simplifying the development process and reducing hardware costs.
Smart Images
Figure CN222464463U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of photovoltaic power generation, in particular to a power converter and a photovoltaic system. Background Art
[0002] Active Neutral Point Clamped (ANPC) inverter is a common power conversion unit in the field of power electronics. Compared with the traditional NPC (Neutral Point Clamped) topology, ANPC has the advantages of flexible control mode and uniform loss distribution, so it is widely used in DC / AC or AC / DC converters. ANPC usually uses pulse width modulation (PWM) technology to convert DC signals into AC sinusoidal signals of a specific frequency, or vice versa, to convert AC sinusoidal signals of a certain frequency into DC signals to achieve power or energy transmission.
[0003] Figure 1 This is a schematic diagram of an ANPC three-level topology. Figure 1 As shown, the ANPC three-level topology structure includes switch tubes T1 to T6, and the connection point of switch tubes T5 and T6 is connected to the midpoint O of the positive and negative DC bus. Capacitor C1 is connected in series between the positive terminal P of the DC bus and the midpoint O, and capacitor C2 is connected in series between the negative terminal N and the midpoint O. In half a cycle, switch tube T2 is always in the on state, while T1 and T5 are turned on alternately, and switch tubes T3 / T4 / T6 are all kept off; in the other half cycle, switch tube T3 is always in the on state, while T6 and T4 are turned on alternately, and switch tubes T1 / T5 / T2 are all kept off. In order to achieve reliable switching on and off of semiconductor devices, it is necessary to monitor and protect the PWM timing logic to prevent the bridge arm from being damaged due to direct conduction or abnormal shutdown. Taking the switch tube T1 / T5 / T2 as an example, it is necessary to insert a certain dead zone between the conduction time of T1 and T5 to prevent T1 and T5 from being turned on at the same time and causing the bridge arm to be turned on. In addition, in order to avoid overvoltage during shutdown, T1 / T5 must be switched only within the conduction time of T2. When T2 is not turned on, T1 / T5 must remain disconnected.
[0004] At present, the industry usually uses devices such as Complex Programmable Logical Devices (CPLD) or Field Programmable Gate Arrays (FPGA) to implement PWM dead zone and corresponding protection logic. However, this solution has high hardware costs and also requires related software codes for control, which results in a long development cycle. Utility Model Content
[0005] In view of this, it is necessary to provide a power converter and a photovoltaic system to solve the problems of high cost and long development cycle of using programmable devices to implement PWM protection logic in the prior art.
[0006] In a first aspect, a power converter is provided in this embodiment, comprising a first switch tube, a second switch tube, a third switch tube and a fourth switch tube connected in series in sequence, and a fifth switch tube and a sixth switch tube connected in series and connected in parallel with the second switch tube and the third switch tube, wherein a connection point between the fifth switch tube and the sixth switch tube is connected to a midpoint of a positive and negative DC bus; the power converter further comprises a timing protection circuit connected to each switch tube,
[0007] The timing protection circuit receives multiple initial pulse signals corresponding to each of the switch tubes, performs timing adjustment on the multiple initial pulse signals, outputs corresponding multiple target pulse signals and sends them to the corresponding switch tubes to avoid the first switch tube and the fifth switch tube from being turned on at the same time, and to avoid the fourth switch tube and the sixth switch tube from being turned on at the same time; and controls the first switch tube and the fifth switch tube to perform switching actions when the second switch tube is turned on, and controls the fourth switch tube and the sixth switch tube to perform switching actions when the third switch tube is turned on.
[0008] In a further embodiment, the timing protection circuit includes a timing control circuit and a state identification circuit connected to each other.
[0009] The state identification circuit performs delay processing on the multiple initial pulse signals corresponding to the switch tubes, outputs the corresponding delayed pulse signals, and performs logic processing on the initial pulse signals and the corresponding delayed pulse signals, and outputs the corresponding state identification signals;
[0010] The timing control circuit performs logic processing on the multiple delayed pulse signals and the multiple state identification signals corresponding to the switch tubes, and outputs corresponding target pulse signals.
[0011] In a further embodiment, the state identification circuit includes a first identification circuit, a fourth identification circuit, a fifth identification circuit and a sixth identification circuit which correspond to the first switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube respectively and have the same structure, and
[0012] A second identification circuit and a third identification circuit respectively corresponding to the second switch tube and the third switch tube and having the same structure.
[0013] In a further embodiment, the first identification circuit includes a conduction delay circuit, a first NOT gate, a second NOT gate and a first AND gate.
[0014] The input end of the conduction delay circuit and the input end of the second NOT gate receive the initial pulse signal of the first switch tube, and the output end of the conduction delay circuit outputs the delayed pulse signal of the first switch tube; the input end of the first NOT gate receives the delayed pulse signal, the output end of the first NOT gate is connected to the first input end of the first AND gate, the output end of the second NOT gate is connected to the second input end of the first AND gate, and the output end of the first AND gate outputs a low effective signal of the first switch tube.
[0015] In a further embodiment, the second identification circuit includes a turn-off delay circuit, a third NOT gate and a second AND gate.
[0016] The input end of the shutdown delay circuit and the first input end of the second AND gate receive the initial pulse signal of the second switch tube, and the output end of the shutdown delay circuit outputs the delayed pulse signal of the second switch tube; the second input end of the second AND gate and the input end of the third NOT gate receive the delayed pulse signal, the output end of the second AND gate outputs a high valid signal of the second switch tube, and the output end of the third NOT gate outputs a low valid signal of the second switch tube.
[0017] In a further embodiment, the timing control circuit includes a first control circuit corresponding to the first switch tube,
[0018] The first control circuit includes a third AND gate, a fourth AND gate, a fifth AND gate and a sixth AND gate, wherein the output end of the previous AND gate is connected to the first input end of the next AND gate; the first input end of the third AND gate receives the delayed pulse signal of the first switch tube, the second input end of the third AND gate receives the high effective signal of the second switch tube, the second input end of the fourth AND gate receives the low effective signal of the third switch tube, the second input end of the fifth AND gate receives the low effective signal of the fifth switch tube, the second input end of the sixth AND gate receives the low effective signal of the fourth switch tube, and the output end of the sixth AND gate outputs the target pulse signal of the first switch tube.
[0019] In a further embodiment, the timing control circuit further includes a fourth control circuit corresponding to the fourth switch tube;
[0020] The fourth control circuit includes a seventh AND gate, an eighth AND gate, a ninth AND gate and a tenth AND gate, wherein the output end of the previous AND gate is connected to the first input end of the next AND gate; the first input end of the seventh AND gate receives the delayed pulse signal of the fourth switch tube, the second input end of the seventh AND gate receives the high effective signal of the third switch tube, the second input end of the eighth AND gate receives the low effective signal of the sixth switch tube, the second input end of the ninth AND gate receives the low effective signal of the second switch tube, the second input end of the tenth AND gate receives the low effective signal of the first switch tube, and the output end of the tenth AND gate outputs the target pulse signal of the fourth switch tube.
[0021] In a further embodiment, the timing control circuit includes a second control circuit corresponding to the second switch tube.
[0022] The second control circuit includes an eleventh AND gate, a first input end of the eleventh AND gate receives the delayed pulse signal of the second switch tube, a second input end of the eleventh AND gate receives the low effective signal of the fourth switch tube, and an output end of the eleventh AND gate outputs the target pulse signal of the second switch tube.
[0023] In a further embodiment, the timing control circuit further includes a third control circuit corresponding to the third switch tube;
[0024] The third control circuit includes a twelfth AND gate, a first input end of the twelfth AND gate receives the delayed pulse signal of the third switch tube, a second input end of the twelfth AND gate receives the low effective signal of the first switch tube, and an output end of the twelfth AND gate outputs the target pulse signal of the third switch tube.
[0025] In a further embodiment, the timing control circuit includes a fifth control circuit corresponding to the fifth switch tube.
[0026] The fifth control circuit includes a thirteenth AND gate and a fourteenth AND gate, wherein the output end of the thirteenth AND gate is connected to the first input end of the fourteenth AND gate; the first input end of the thirteenth AND gate receives the delayed pulse signal of the fifth switch tube, the second input end of the thirteenth AND gate receives the high effective signal of the second switch tube, the second input end of the fourteenth AND gate receives the low effective signal of the first switch tube, and the output end of the fourteenth AND gate outputs the target pulse signal of the fifth switch tube.
[0027] In a further embodiment, the timing control circuit further includes a sixth control circuit corresponding to the sixth switch tube;
[0028] The sixth control circuit includes a fifteenth AND gate and a sixteenth AND gate, wherein the output end of the fifteenth AND gate is connected to the first input end of the sixteenth AND gate; the first input end of the fifteenth AND gate receives the delayed pulse signal of the sixth switch tube, the second input end of the fifteenth AND gate receives the high valid signal of the third switch tube, the second input end of the sixteenth AND gate receives the low valid signal of the fourth switch tube, and the output end of the sixteenth AND gate outputs the target pulse signal of the sixth switch tube.
[0029] In a further embodiment, the on-delay circuit comprises a first diode, a first resistor and a first capacitor,
[0030] The first resistor is connected between the input and output ends of the conduction delay circuit, the anode of the first diode is connected to the output end, the cathode of the first diode is connected to the input end, one end of the first capacitor is connected to the output end, and the other end of the first capacitor is grounded.
[0031] In a further embodiment, the turn-off delay circuit includes a second diode, a second resistor and a second capacitor.
[0032] The second resistor is connected between the input and output ends of the shutdown delay circuit, the anode of the second diode is connected to the input end, the cathode of the second diode is connected to the output end, one end of the second capacitor is connected to the output end, and the other end of the second capacitor is grounded.
[0033] According to a second aspect, a photovoltaic system is provided in this embodiment. The photovoltaic system includes the power converter according to the first aspect.
[0034] The power converter of the utility model receives a plurality of initial pulse signals corresponding to each switch tube in an ANPC three-level topology circuit through a timing protection circuit, performs timing adjustment on the plurality of initial pulse signals, outputs a plurality of corresponding target pulse signals and sends them to the corresponding switch tubes, so as to avoid the first switch tube and the fifth switch tube from being turned on at the same time, and to avoid the fourth switch tube and the sixth switch tube from being turned on at the same time; and controls the first switch tube and the fifth switch tube to perform switching action when the second switch tube is turned on, and controls the fourth switch tube and the sixth switch tube to perform switching action when the third switch tube is turned on, so that the dead zone and timing logic protection functions can be realized in the ANPC three-level topology circuit only through a simple hardware circuit, without relying on programmable devices and software codes, and the scheme is simple, easy to implement, and the cost is very low. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 It is a schematic diagram of the ANPC three-level topology;
[0036] Figure 2 is a schematic diagram of the structure of a power converter according to some embodiments of the present application;
[0037] Figure 3 is a schematic diagram of the structure of a timing protection circuit in some embodiments of the present application;
[0038] Figure 4 is a schematic diagram of the internal connection of the timing protection circuit of some embodiments of the present application;
[0039] Figure 5 is a circuit connection diagram of a first identification circuit in some embodiments of the present application;
[0040] Figure 6 is a circuit connection diagram of a second identification circuit in some embodiments of the present application;
[0041] Figure 7 is a circuit connection diagram of a first control circuit in some embodiments of the present application;
[0042] Figure 8 is a circuit connection diagram of a fourth control circuit in some embodiments of the present application;
[0043] Fig. 9 is a circuit connection diagram of a second control circuit in some embodiments of the present application;
[0044] Fig.10 is a circuit connection diagram of a third control circuit in some embodiments of the present application;
[0045] Fig.11 is a circuit connection diagram of a fifth control circuit in some embodiments of the present application;
[0046] Fig.12 is a circuit connection diagram of a sixth control circuit in some embodiments of the present application;
[0047] Fig.13 is a schematic diagram of target pulse signals corresponding to each switch tube in some embodiments of the present application;
[0048] Fig.14 is a circuit connection diagram of a turn-on delay circuit of some embodiments of the present application;
[0049] Fig.15 It is a circuit connection diagram of the shutdown delay circuit of some embodiments of the present application. DETAILED DESCRIPTION
[0050] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0051] It should be noted that when a component is referred to as being "fixed to" another component, it may be directly on the other component or there may also be a component centered. When a component is considered to be "connected to" another component, it may be directly connected to the other component or there may be a component centered at the same time. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a component centered at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only. "First" and "second" are only for the distinction of component names and do not indicate order.
[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.
[0053] In order to make the above-mentioned purposes, features and advantages of the utility model more obvious and easy to understand, the specific implementation methods of the utility model are described in detail below in conjunction with the accompanying drawings. Among them, the utility model embodiment is described in detail in conjunction with the schematic diagram, and the schematic diagram is only an example, which should not limit the scope of protection of the utility model.
[0054] The power converter provided by the embodiment of the utility model is further described in detail below in conjunction with the accompanying drawings.
[0055] See also Figure 2 , which is a schematic diagram of the structure of a power converter of some embodiments of the present application. The power converter includes a first switch tube T1, a second switch tube T2, a third switch tube T3 and a fourth switch tube T4 connected in series, and a fifth switch tube T5 and a sixth switch tube T6 connected in series and connected in parallel with the second switch tube T2 and the third switch tube T3, and the connection point of the fifth switch tube T5 and the sixth switch tube T6 is connected to the midpoint O of the positive and negative DC bus P and N. The power converter also includes a timing protection circuit 10 connected to each switch tube.
[0056] Figure 2The topological connection circuit 20 of the switch tubes T1 to T6 shown is an ANPC three-level topological structure, and each switch tube is switched by a corresponding PWM signal. When the PWM signal is at a high level, the corresponding switch tube is turned on; when the PWM signal is at a low level or a zero level, the corresponding switch tube is turned off.
[0057] The timing protection circuit 10 receives a plurality of initial pulse signals PWMI_T1-PWMI_T6 corresponding to each switch tube, and performs timing adjustment on the plurality of initial pulse signals PWMI_T1-PWMI_T6, outputs a plurality of corresponding target pulse signals PWMO_T1-PWMO_T6 and sends them to the corresponding switch tubes T1-T6, so as to prevent the first switch tube T1 and the fifth switch tube T5 from being turned on at the same time, and to prevent the fourth switch tube T4 and the sixth switch tube T6 from being turned on at the same time; and controls the first switch tube T1 and the fifth switch tube T5 to perform switching action when the second switch tube T2 is turned on, and controls the fourth switch tube T4 and the sixth switch tube T6 to perform switching action when the third switch tube T3 is turned on.
[0058] Among them, the timing protection circuit 10 is a hardware circuit, which may include logic devices and devices such as resistors, capacitors, and diodes, but does not include programmable logic devices, and does not need to be controlled by software code. The timing protection circuit 10 performs timing adjustment on the initial pulse signals PWMI_T1~PWMI_T6, and the adjustment method may include delaying the time of high and low level switching in the initial pulse signals PWMI_T1~PWMI_T6 through a delay circuit, and may also perform corresponding logic processing on the input initial pulse signals PWMI_T1~PWMI_T6 and the pulse signals after delay processing according to the timing logic relationship between the switch tubes, and finally output the target pulse signals PWMO_T1~PWMO_T6 to realize reliable switching control of the switch tubes T1~T6, thereby improving the safety and reliability of the operation of the power converter, and the cost is very low.
[0059] According to the working mode of the ANPC three-level topology, in half a cycle, the switch tube T2 is always in the on state, and PWMO_T2 is high level; while T1 and T5 are alternately turned on, that is, PWMO_T1 and PWMO_T5 are alternately in the high level state; the switch tubes T3 / T4 / T6 are all kept off, that is, PWMO_T3, PWMO_T4 and PWMO_T6 are low level or zero level. In the other half cycle, the switch tube T3 is always kept on, and PWMO_T3 is high level; while T6 and T4 are alternately turned on, that is, PWMO_T6 and PWMO_T4 are alternately in the high level state; the switch tubes T1 / T5 / T2 are all kept off, that is, PWMO_T1, PWMO_T5 and PWMO_T2 are low level or zero level.
[0060] There is a dead zone between the time intervals when PWMO_T1 and PWMO_T5 are in the high level state. During the dead zone, PWMO_T1 and PWMO_T5 are both in the low level state to avoid the switch tubes T1 and T5 being turned on at the same time, resulting in the bridge arm being directly turned on. Moreover, PWMO_T1 and PWMO_T5 are alternately in the high level state only during the time interval when PWMO_T2 is in the high level. When PWMO_T2 is in the low level or zero level, PWMO_T1 and PWMO_T5 are both in the low level, that is, the switch tubes T1 and T5 can only perform switching actions during the time when T2 is turned on. When T2 is not turned on, the switch tubes T1 and T5 must remain disconnected to avoid overvoltage when turned off.
[0061] Similarly, there is a dead zone between the time intervals when PWMO_T4 and PWMO_T6 are in the high level state. During the dead zone, PWMO_T4 and PWMO_T6 are both in the low level state to avoid the switch tubes T4 and T6 being turned on at the same time, causing the bridge arm to be directly turned on. Moreover, PWMO_T4 and PWMO_T6 are alternately in the high level state only during the time interval when PWMO_T3 is at the high level. When PWMO_T3 is at the low level or zero level, PWMO_T4 and PWMO_T6 are both at the low level, that is, the switch tubes T4 and T6 can only perform switching actions during the time when T3 is turned on. When T3 is not turned on, the switch tubes T4 and T6 must remain disconnected to avoid overvoltage when turned off.
[0062] Specifically, Figure 3 is a schematic diagram of the structure of the timing protection circuit of some embodiments of the present application, such as Figure 3 As shown, the timing protection circuit 30 includes a timing control circuit 32 and a state identification circuit 34 connected to each other. The state identification circuit 34 performs delay processing on a plurality of initial pulse signals PWMI_T31~PWMI_T36 corresponding to each switch tube T1~T6, outputs corresponding delayed pulse signals PWMDe_T1~PWMDe_T6, and performs logic processing on the initial pulse signals PWMI_T31~PWMI_T36 and the corresponding delayed pulse signals PWMDe_T1~PWMDe_T6, and outputs corresponding state identification signals Sta_T1~Sta_T6. The timing control circuit 12 performs logic processing on the plurality of delayed pulse signals PWMDe_T1~PWMDe_T6 and the plurality of state identification signals Sta_T1~Sta_T6 corresponding to each switch tube, and outputs corresponding target pulse signals PWMO_T31~PWMO_T36.
[0063] In this embodiment, the high level or low level state in the initial pulse signals PWMI_T31 to PWMI_T36 can be delayed to generate delayed pulse signals PWMDe_T1 to PWMDe_T6. The delay processing refers to postponing the switching time of the signal state from high to low or from low to high. For example, for the initial pulse signal PWMI_T31, when the state of PWMI_T31 switches from a low level to a high level, the output time of the high level state can be delayed, while the low level state is not delayed. For the initial pulse signal PWMI_T32, when the state of PWMI_T32 switches from a high level to a low level, the output time of the low level state can be delayed, while the high level state is not delayed.
[0064] Specifically, signal delay can be achieved through an RC circuit, and the specific delay time can be set by adjusting the resistance value of the resistor and the capacitance value of the capacitor.
[0065] The state identification signals Sta_T1 to Sta_T6 can be used as enable signals to control the corresponding switch tube to be turned on or off, and can specifically include high-effective signals T1_HIGH to T6_HIGH and low-effective signals T1_LOW to T6_LOW. The high-effective signals T1_HIGH to T6_HIGH mean that when the signal is at a high level, the action condition of the corresponding switch tube can be met, and the low-effective signals T1_LOW to T6_LOW mean that when the signal is at a low level, the action condition of the corresponding switch tube can be met.
[0066] The timing control circuit 12 outputs target pulse signals PWMO_T31 ˜ PWMO_T36 through the delayed pulse signals PWMDe_T1 ˜ PWMDe_T6 and the state identification signals Sta_T1 ˜ Sta_T6 according to the timing logic relationship between the switch tubes.
[0067] In some embodiments, Figure 4 is a schematic diagram of the internal connection of the timing protection circuit of some embodiments of the present application, such as Figure 4 As shown, the state identification circuit 44 includes a first identification circuit 141, a fourth identification circuit 144, a fifth identification circuit 145 and a sixth identification circuit 146 which correspond to the first switch tube T1, the fourth switch tube T4, the fifth switch tube T5 and the sixth switch tube T6 respectively and have the same structure, and a second identification circuit 142 and a third identification circuit 143 which correspond to the second switch tube T2 and the third switch tube T3 respectively and have the same structure.
[0068] The first identification circuit 141, the fourth identification circuit 144, the fifth identification circuit 145 and the sixth identification circuit 146 have the same structure, which means that the components constituting these four circuits are the same and the topological connections between the components are the same. The second identification circuit 142 and the third identification circuit 143 also have the same structure.
[0069] like Figure 4 As shown, the timing control circuit 42 includes a first control circuit 421, a second control circuit 422, a third control circuit 423, a fourth control circuit 424, a fifth control circuit 425, and a sixth control circuit 426 corresponding to the switch tubes T1 to T6, respectively. That is, each switch tube T1 to T6 has a one-to-one corresponding identification circuit and control circuit. The identification circuit outputs the corresponding delayed pulse signal PWMDe_T11 to PWMDe_T16 and the corresponding state identification signal Sta_T11 to Sta_T16 according to the input initial pulse signal PWMI_T41 to PWMI_T46. Among them, the delayed pulse signal PWMDe_T11 to PWMDe_T16 is input into the control circuit corresponding to the switch tube, and the state identification signal Sta_T11 to Sta_T16 is input into the control circuit of other switch tubes to control the switching action of other switch tubes.
[0070] The connection relationship between the state identification signals Sta_T1~Sta_T6 and the switch tubes is determined by the topological relationship of each switch tube. For example, the low effective signal T1_LOW can be used to control the conduction of the switch tubes T3, T4, and T5, because the switch tube T1 is turned off, which is a prerequisite for the switch tubes T3, T4, and T5 to be turned on. For example, the high effective signal T2_HIGH can be used to control the turn-off of the switch tubes T1 and T5, because the turn-on of the switch tube T2 is a prerequisite for the turn-off of the switch tubes T1 and T5; the low effective signal T2_LOW can be used to control the conduction of the switch tube T4, because the turn-off of the switch tube T2 is a prerequisite for the turn-on of the switch tube T4.
[0071] Based on the topological relationship of each switch tube, such as Figure 4 As shown, the state identification signal Sta_T11 is input into the third control circuit 423, the fourth control circuit 424, and the fifth control circuit 425, the state identification signal Sta_T12 is input into the first control circuit 421, the fourth control circuit 424, and the fifth control circuit 425, the state identification signal Sta_T13 is input into the first control circuit 421, the fourth control circuit 424, and the sixth control circuit 426, the state identification signal Sta_T14 is input into the first control circuit 421, the second control circuit 422, and the sixth control circuit 426, the state identification signal Sta_T15 is input into the first control circuit 421, and the state identification signal Sta_T16 is input into the fourth control circuit 424.
[0072] The control circuit corresponding to each switch tube outputs the corresponding target pulse signal PWMO_T41 ˜PWMO_T46 according to the delayed pulse signal PWMDe_T11 ˜PWMDe_T16 and the input state identification signal Sta_T11 ˜ Sta_T16 .
[0073] In some specific embodiments, Figure 5 is a circuit connection diagram of the first identification circuit of some embodiments of the present application, such as Figure 5 As shown, the first identification circuit 541 includes a turn-on delay circuit 5411, a first NOT gate UN1, a second NOT gate UN2 and a first AND gate UA1. The input end of the turn-on delay circuit 5411 and the input end of the second NOT gate UN2 receive the initial pulse signal PWMI_T51 of the first switch tube T1, and the output end of the turn-on delay circuit 5411 outputs the delayed pulse signal PWMDe_T21 of the first switch tube T1; the input end of the first NOT gate UN1 receives the delayed pulse signal PWMDe_T21, the output end of the first NOT gate UN1 is connected to the first input end of the first AND gate UA1, the output end of the second NOT gate UN2 is connected to the second input end of the first AND gate UA1, and the output end of the first AND gate UA1 outputs the low effective signal T1_LOW of the first switch tube T1.
[0074] In this embodiment, the first NOT gate UN1, the second NOT gate UN2, and the first AND gate UA1 represent logic NOT gate and logic AND gate devices, which can be implemented by, for example, 74HCT series logic chips. The on-delay function of the on-delay circuit 5411 means that when the signal state of the input terminal switches from a low level to a high level, the high level is output with a delay. The on-delay circuit 5411 can be implemented by simple resistors, capacitors, and diodes.
[0075] When the initial pulse signal PWMI_T51 switches from a low level to a high level, the on-delay circuit 5411 inserts a delay time and outputs a delayed pulse signal PWMDe_T21, which can be used as an input signal of the timing control circuit to generate a target pulse signal of the switch tube T1, so that the switch tube T1 is delayed to be turned on to meet the dead zone requirement between the on-time of the switch tubes T1 and T5. At the same time, the initial pulse signal PWMI_T51 is first inverted before and after the delay and then the "AND" logic is taken to output a low effective signal T1_LOW to control the corresponding switch tubes T3, T4, and T5.
[0076] When the initial pulse signal PWMI_T51 switches from a high level to a low level, the on-delay circuit 5411 has no delay effect, the output delayed pulse signal PWMDe_T21 has no delay effect, and the switch tube T1 has no delay when it is turned off.
[0077] Similarly, the fourth identification circuit, the fifth identification circuit and the sixth identification circuit have the same structure as the first identification circuit. The input end of the fourth identification circuit receives the initial pulse signal PWMI_T54 corresponding to the fourth switch tube T4, and outputs the corresponding delayed pulse signal PWMDe_T24 and the low effective signal T4_LOW. The input end of the fifth identification circuit receives the initial pulse signal PWMI_T55 corresponding to the fifth switch tube T5, and outputs the corresponding delayed pulse signal PWMDe_T25 and the low effective signal T5_LOW; the input end of the sixth identification circuit receives the initial pulse signal PWMI_T56 corresponding to the sixth switch tube T6, and outputs the corresponding delayed pulse signal PWMDe_T26 and the low effective signal T6_LOW.
[0078] Since the switch tubes T1 and T5 are turned on alternately, and the switch tubes T4 and T6 are turned on alternately, the delayed pulse signals PWMDe_T21 and PWMDe_T25 meet the dead zone requirements between the conduction time of T1 / T5; the delayed pulse signals PWMDe_T24 and PWMDe_T26 meet the dead zone requirements between the conduction time of T4 / T6. The low effective signal T5_LOW is used to control the corresponding switch tube T1; the low effective signal T4_LOW is used to control the corresponding switch tubes T1, T2, and T6, and the low effective signal T6_LOW is used to control the corresponding switch tube T4.
[0079] In some specific embodiments, Figure 6 is a circuit connection diagram of the second identification circuit of some embodiments of the present application, such as Figure 6 As shown, the second identification circuit 542 includes a turn-off delay circuit 5421, a third NOT gate UN3, and a second AND gate UA2. The input end of the turn-off delay circuit 5421 and the first input end of the second AND gate UA2 receive the initial pulse signal PWMI_T52 of the second switch tube T2, and the output end of the turn-off delay circuit 5421 outputs the delayed pulse signal PWMDe_T22 of the second switch tube T2; the second input end of the second AND gate UA2 and the input end of the third NOT gate UN3 receive the delayed pulse signal PWMDe_T22, the output end of the second AND gate UA2 outputs the high effective signal T2_HIGH of the second switch tube T2, and the output end of the third NOT gate UN3 outputs the low effective signal T2_LOW of the second switch tube T2.
[0080] The turn-off delay function of the turn-off delay circuit 5421 means that when the signal state of the input terminal switches from a high level to a low level, the low level is output with a delay. The turn-on delay circuit 5421 can be implemented with simple resistors, capacitors and diodes.
[0081] When the initial pulse signal PWMI_T52 switches from a high level to a low level, the shutdown delay circuit 5421 inserts a delay time and outputs a delayed pulse signal PWMDe_T22, which can be used as an input signal of the timing control circuit to generate a target pulse signal of the switch tube T2, so as to extend the conduction time of the switch tube T2, ensure that the switch tubes T1 and T5 complete the shutdown action within the conduction time of the second switch tube T2, and avoid overvoltage during shutdown. At the same time, the "AND" logic is taken for the signals of the initial pulse signal PWMI_T52 before and after the delay, and a high effective signal T2_HIGH and a low effective signal T2_LOW are output. The high effective signal T2_HIGH is used to control the switch tubes T1 and T5, and the low effective signal T2_LOW is used to control the switch tube T4.
[0082] When the initial pulse signal PWMI_T52 switches from a low level to a high level, the turn-off delay circuit 5421 has no delay effect, the output delayed pulse signal PWMDe_T22 has no delay effect, and the switch tube T2 has no delay when it is turned on.
[0083] Similarly, the third identification circuit has the same structure as the second identification circuit. The input end of the third identification circuit receives the initial pulse signal PWMI_T53 corresponding to the third switch tube T3, and outputs the corresponding delayed pulse signal PWMDe_T23 as well as the high effective signal T3_HIGH and the low effective signal T3_LOW. The delayed pulse signal PWMDe_T23 is used to generate the target pulse signal of the switch tube T3 to extend the conduction time of the switch tube T3 and ensure that the switch tubes T4 and T6 complete the shutdown action within the conduction time of the third switch tube T3. The high effective signal T3_HIGH is used to control the switch tubes T4 and T6, and the low effective signal T3_LOW is used to control the switch tube T1.
[0084] In some embodiments, Figure 7 is a circuit connection diagram of the first control circuit of some embodiments of the present application, such as Figure 7As shown, the timing control circuit includes a first control circuit 521 corresponding to the first switch tube T1. The first control circuit 521 includes a third AND gate UA3, a fourth AND gate UA4, a fifth AND gate UA5 and a sixth AND gate UA6, wherein the output end of the previous AND gate is connected to the first input end of the next AND gate; the first input end of the third AND gate UA3 receives the delayed pulse signal PWMDe_T31 of the first switch tube T1, the second input end of the third AND gate UA3 receives the high effective signal T2_HIGH1 of the second switch tube T2, the second input end of the fourth AND gate UA4 receives the low effective signal T3_LOW1 of the third switch tube T3, the second input end of the fifth AND gate UA5 receives the low effective signal T5_LOW1 of the fifth switch tube T5, the second input end of the sixth AND gate UA6 receives the low effective signal T4_LOW1 of the fourth switch tube T4, and the output end of the sixth AND gate UA6 outputs the target pulse signal PWMO_T51 of the first switch tube T1.
[0085] In this embodiment, the delayed pulse signal PWMDe_T31, the high effective signal T2_HIGH1, the low effective signal T3_LOW1, the low effective signal T5_LOW1, and the low effective signal T4_LOW1 of the first switch tube T1 are taken into "AND" logic to output the target pulse signal PWMO_T51, that is, only when the first five signals are all high level, the target pulse signal PWMO_T51 is high level; when any one or more of the first five signals are low level, the target pulse signal PWMO_T51 is low level. The delayed pulse signal PWMDe_T31 is used to provide the dead time of the target pulse signal PWMO_T51, and the high effective signal T2_HIGH1, the low effective signal T3_LOW1, T5_LOW1, and T4_LOW1 are used as the limiting conditions for the switch tube T1 to be turned on. When the switch tube T3 / T4 / T5 is abnormally turned on, the switch tube T1 can be turned off in time to improve the reliability of the switch control of the switch tube T1.
[0086] In some embodiments, Figure 8 is a circuit connection diagram of the fourth control circuit of some embodiments of the present application, such as Figure 8As shown, the timing control circuit also includes a fourth control circuit 524 corresponding to the fourth switch tube T4. The fourth control circuit 524 includes a seventh AND gate UA7, an eighth AND gate UA8, a ninth AND gate UA9 and a tenth AND gate UA10, wherein the output end of the previous AND gate is connected to the first input end of the next AND gate. The first input end of the seventh AND gate UA7 receives the delayed pulse signal PWMDe_T34 of the fourth switch tube T4, the second input end of the seventh AND gate UA7 receives the high effective signal T3_HIGH2 of the third switch tube T3, the second input end of the eighth AND gate UA8 receives the low effective signal T6_LOW2 of the sixth switch tube T6, the second input end of the ninth AND gate UA9 receives the low effective signal T2_LOW2 of the second switch tube T2, the second input end of the tenth AND gate UA10 receives the low effective signal T1_LOW2 of the first switch tube T1, and the output end of the tenth AND gate UA10 outputs the target pulse signal PWMO_T54 of the fourth switch tube T4.
[0087] Similar to the previous embodiment, the delayed pulse signal PWMDe_T34, the high effective signal T3_HIGH2, the low effective signal T6_LOW2, the low effective signal T2_LOW2, and the low effective signal T1_LOW2 of the fourth switch tube T4 are subjected to the "AND" logic to output the target pulse signal PWMO_T54, that is, only when the first five signals are all high level, the target pulse signal PWMO_T54 is high level; when any one or more of the first five signals are low level, the target pulse signal PWMO_T54 is low level. The delayed pulse signal PWMDe_T34 is used to provide the dead time of the target pulse signal PWMO_T54, and the high effective signal T3_HIGH2, the low effective signal T6_LOW2, T2_LOW2, and T1_LOW2 are used as the limiting conditions for the switch tube T4 to be turned on. When the switch tubes T1 / T2 / T6 are abnormally turned on, the switch tube T4 can be turned off in time to improve the reliability of the switch control of the switch tube T1.
[0088] In some embodiments, Fig. 9 is a circuit connection diagram of the second control circuit of some embodiments of the present application, such as Fig. 9 As shown, the timing control circuit includes a second control circuit 522 corresponding to the second switch tube T2, and the second control circuit 522 includes an eleventh AND gate UA11. The first input end of the eleventh AND gate UA11 receives the delayed pulse signal PWMDe_T32 of the second switch tube T2, the second input end of the eleventh AND gate UA11 receives the low effective signal T4_LOW3 of the fourth switch tube T4, and the output end of the eleventh AND gate UA11 outputs the target pulse signal PWMO_T52 of the second switch tube T2.
[0089] In this embodiment, the delayed pulse signal PWMDe_T32 and the low effective signal T4_LOW3 of the second switch tube T2 are taken into "AND" logic to output the target pulse signal PWMO_T52, that is, only when PWMDe_T32 and T4_LOW3 are both high, the target pulse signal PWMO_T52 is high; when any one or more of PWMDe_T32 and T4_LOW3 is low, the target pulse signal PWMO_T52 is low. The delayed pulse signal PWMDe_T32 is used to extend the conduction time of the target pulse signal PWMO_T52 to ensure that the switch tubes T1 / T5 are turned off earlier than T2; the low effective signal T4_LOW3 is used as a limiting condition for the conduction of the switch tube T2 to improve the reliability of the switch control of the switch tube T2.
[0090] In some embodiments, Fig.10 Schematic diagram of circuit connection of the third control circuit in some embodiments of the present application, such as Fig.10 As shown, the timing control circuit also includes a third control circuit 523 corresponding to the third switch tube T3. The third control circuit 523 includes a twelfth AND gate UA12, a first input end of the twelfth AND gate UA12 receives the delayed pulse signal PWMDe_T33 of the third switch tube T3, a second input end of the twelfth AND gate UA12 receives the low effective signal T1_LOW4 of the first switch tube T1, and an output end of the twelfth AND gate UA12 outputs the target pulse signal PWMO_T53 of the third switch tube T3.
[0091] Similarly, the delayed pulse signal PWMDe_T33 and the low effective signal T1_LOW4 of the third switch tube T3 are ANDed to output the target pulse signal PWMO_T53, that is, the target pulse signal PWMO_T53 is high only when PWMDe_T33 and T1_LOW4 are both high; the target pulse signal PWMO_T53 is low when any one or more of PWMDe_T33 and T1_LOW4 are low. The delayed pulse signal PWMDe_T33 is used to extend the on time of the target pulse signal PWMO_T53 to ensure that the switch tubes T4 / T6 are turned off earlier than T3; the low effective signal T1_LOW4 is used as a limiting condition for the on-state of the switch tube T3 to improve the reliability of the switch control of the switch tube T3.
[0092] In some embodiments, Fig.11 Schematic diagram of circuit connection of the fifth control circuit of some embodiments of the present application, such as Fig.11As shown, the timing control circuit includes a fifth control circuit 525 corresponding to the fifth switch tube T5, and the fifth control circuit 525 includes a thirteenth AND gate UA13 and a fourteenth AND gate UA14, wherein the output end of the thirteenth AND gate UA13 is connected to the first input end of the fourteenth AND gate UA14; the first input end of the thirteenth AND gate UA13 receives the delayed pulse signal PWMDe_T35 of the fifth switch tube T5, the second input end of the thirteenth AND gate UA13 receives the high valid signal T2_HIGH5 of the second switch tube T2, the second input end of the fourteenth AND gate UA14 receives the low valid signal T1_LOW5 of the first switch tube T1, and the output end of the fourteenth AND gate UA14 outputs the target pulse signal PWMO_T55 of the fifth switch tube T5.
[0093] In this embodiment, the delayed pulse signal PWMDe_T35, the high effective signal T2_HIGH5, and the low effective signal T1_LOW5 of the fifth switch tube T5 are taken into "AND" logic to output the target pulse signal PWMO_T55, that is, only when the first three signals are all high level, the target pulse signal PWMO_T55 is high level; when any one or more of the first three signals are low level, the target pulse signal PWMO_T55 is low level. The delayed pulse signal PWMDe_T35 is used to provide the dead time of the target pulse signal PWMO_T55, and the high effective signal T2_HIGH5 and the low effective signal T1_LOW5 are used as the limiting conditions for the conduction of the switch tube T5. When the switch tube T1 is abnormally turned on, the switch tube T5 can be turned off in time to improve the reliability of the switch control of the switch tube T5.
[0094] In some embodiments, Fig.12 Schematic diagram of circuit connection of the sixth control circuit of some embodiments of the present application, such as Fig.12 As shown, the timing control circuit also includes a sixth control circuit 526 corresponding to the sixth switch tube T6. The sixth control circuit 526 includes a fifteenth AND gate UA15 and a sixteenth AND gate UA16, wherein the output end of the fifteenth AND gate UA15 is connected to the first input end of the sixteenth AND gate UA16; the first input end of the fifteenth AND gate UA15 receives the delayed pulse signal PWMDe_T36 of the sixth switch tube T6, the second input end of the fifteenth AND gate UA15 receives the high effective signal T3_HIGH6 of the third switch tube T3, the second input end of the sixteenth AND gate UA16 receives the low effective signal T4_LOW6 of the fourth switch tube T4, and the output end of the sixteenth AND gate UA16 outputs the target pulse signal PWMO_T56 of the sixth switch tube T6.
[0095] In this embodiment, the delayed pulse signal PWMDe_T36, the high effective signal T3_HIGH6, and the low effective signal T4_LOW6 of the sixth switch tube T6 are subjected to the "AND" logic to output the target pulse signal PWMO_T56, that is, the target pulse signal PWMO_T56 is high only when the first three signals are high; when any one or more of the first three signals are low, the target pulse signal PWMO_T56 is low. The delayed pulse signal PWMDe_T36 is used to provide the dead time of the target pulse signal PWMO_T56, and the high effective signal T3_HIGH6 and the low effective signal T4_LOW6 are used as the limiting conditions for the conduction of the switch tube T6. When the switch tube T4 is abnormally turned on, the switch tube T6 can be turned off in time to improve the reliability of the switch control of the switch tube T6.
[0096] Fig.13 Schematic diagram of target pulse signals corresponding to each switch tube in some embodiments of the present application, such as Fig.13 As shown, taking the switch tube T1 / T2 / T5 as an example, when the switch tube T2 is turned on, the switch tubes T3 / T4 / T6 should all be in the off state, and the corresponding target pulse signal should be low level, that is, the low effective signals corresponding to the switch tubes T3 / T4 / T6 are all high level. The initial pulse signal of the switch tube T2 is high level, T2_HIGH is high level, and T2_LOW is low level. At this time, the delayed pulse signal of the switch tube T2 is high level, T4_LOW is high level, then the target pulse signal of T2 is high level, and the switch tube T2 is turned on.
[0097] Further, when the switch tube T2 is turned on, when the switch tube T5 is in the on state and the switch tube T1 is in the off state, the initial pulse signal of the switch tube T5 is high level, T2_HIGH is high level, T1_LOW is high level, then the target pulse signal of T5 is high level, and the switch tube T5 is turned on.
[0098] When the switch tube T5 is in the on state, when the initial pulse signal of the switch tube T1 changes from low level to high level, T1_LOW changes to low level, and the target pulse signal of T5 changes to low level. Although the initial pulse signal of the switch tube T1 changes to high level, since T5_LOW is still low level at this time, the target pulse signal of T1 is low level; due to the existence of the on-delay circuit, the high-level delayed pulse signal of T1 reaches the AND gate after the delay time S1, that is, in the S1 time period, the target pulse signal of T1 is still low level. Therefore, as long as the target pulse signal of the switch tube T5 changes to low level in the S1 time period, T5_LOW has changed to high level before the high-level delayed pulse signal of T1 reaches the AND gate. After the high-level delayed pulse signal of T1 reaches the AND gate, the target pulse signal of TI changes to high level. At this time, the switch tube T1 is turned on. Since the switch tube T5 is turned off before the switch tube T1 is turned on, the simultaneous conduction of the switch tubes T1 and T5 is avoided.
[0099] The connection relationship and purpose of each circuit in this embodiment have been explained in the above embodiments and will not be repeated here.
[0100] In some embodiments, Fig.14 Schematic diagram of circuit connection of the conduction delay circuit of some embodiments of the present application, such as Fig.14 As shown, the turn-on delay circuit 5411 includes a first diode D1, a first resistor R1 and a first capacitor C1. The first resistor R1 is connected between the input terminal In1 and the output terminal Out1 of the turn-on delay circuit 5411, the positive electrode of the first diode D1 is connected to the output terminal Out1, the negative electrode of the first diode D1 is connected to the input terminal In1, one end of the first capacitor C1 is connected to the output terminal Out1, and the other end of the first capacitor C1 is grounded.
[0101] When the signal inputted by the input terminal In1 is at a high level, the first diode D1 is turned off, and the high level signal is output after being delayed by the RC circuit composed of the first resistor R1 and the first capacitor C1. When the signal inputted by the input terminal In1 changes from a high level to a low level, since the first diode D1 has a freewheeling function, the right side of the first diode D1 is at a high level and the left side is at a low level, the first diode D1 is turned on, and therefore the turn-on delay circuit 5411 does not have a delay function on the input low level signal.
[0102] In some embodiments, Fig.15 Schematic diagram of circuit connection of the shutdown delay circuit of some embodiments of the present application, such as Fig.15As shown, the shutdown delay circuit 5421 includes a second diode D2, a second resistor R2 and a second capacitor C2. The second resistor R2 is connected between the input terminal In2 and the output terminal Out2 of the shutdown delay circuit 5421. The positive electrode of the second diode D2 is connected to the input terminal In2, the negative electrode of the second diode D2 is connected to the output terminal Out2, one end of the second capacitor C2 is connected to the output terminal Out2, and the other end of the second capacitor C2 is grounded.
[0103] When the signal inputted by the input terminal In2 is at a low level, the second diode D2 is turned off, and the low level signal is output after being delayed by the RC circuit composed of the second resistor R2 and the second capacitor C2. When the signal inputted by the input terminal In2 changes from a low level to a high level, the second diode D2 is turned on, so the turn-off delay circuit 5421 does not have a delay effect on the input high level signal.
[0104] Some embodiments of the present application also provide a photovoltaic system, which includes a power converter as described in the above embodiments, and realizes dead zone and timing logic protection functions in an ANPC three-level topology circuit through a simple hardware circuit, does not rely on programmable devices and software codes, and the solution is simple, easy to implement, and has very low cost.
[0105] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0106] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. A power converter, comprising a first switch tube, a second switch tube, a third switch tube and a fourth switch tube connected in series in sequence, and a fifth switch tube and a sixth switch tube connected in series and connected in parallel with the second switch tube and the third switch tube, wherein the connection point of the fifth switch tube and the sixth switch tube is connected to the midpoint of the positive and negative DC bus; characterized in that: The power converter also includes a timing protection circuit connected to each switch tube. The timing protection circuit receives multiple initial pulse signals corresponding to each of the switch tubes, performs timing adjustment on the multiple initial pulse signals, outputs corresponding multiple target pulse signals and sends them to the corresponding switch tubes to avoid the first switch tube and the fifth switch tube from being turned on at the same time, and to avoid the fourth switch tube and the sixth switch tube from being turned on at the same time; and controls the first switch tube and the fifth switch tube to perform switching actions when the second switch tube is turned on, and controls the fourth switch tube and the sixth switch tube to perform switching actions when the third switch tube is turned on.
2. The power converter according to claim 1, characterized in that: The timing protection circuit includes a timing control circuit and a state identification circuit connected to each other. The state identification circuit performs delay processing on the multiple initial pulse signals corresponding to the switch tubes, outputs the corresponding delayed pulse signals, and performs logic processing on the initial pulse signals and the corresponding delayed pulse signals, and outputs the corresponding state identification signals; The timing control circuit performs logic processing on the multiple delayed pulse signals and the multiple state identification signals corresponding to the switch tubes, and outputs corresponding target pulse signals.
3. The power converter according to claim 2, characterized in that: The state identification circuit includes a first identification circuit, a fourth identification circuit, a fifth identification circuit and a sixth identification circuit which correspond to the first switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube respectively and have the same structure, and A second identification circuit and a third identification circuit respectively corresponding to the second switch tube and the third switch tube and having the same structure.
4. The power converter according to claim 3, characterized in that: The first identification circuit includes a conduction delay circuit, a first NOT gate, a second NOT gate and a first AND gate. The input end of the conduction delay circuit and the input end of the second NOT gate receive the initial pulse signal of the first switch tube, and the output end of the conduction delay circuit outputs the delayed pulse signal of the first switch tube; the input end of the first NOT gate receives the delayed pulse signal, the output end of the first NOT gate is connected to the first input end of the first AND gate, the output end of the second NOT gate is connected to the second input end of the first AND gate, and the output end of the first AND gate outputs a low effective signal of the first switch tube.
5. The power converter according to claim 3, characterized in that: The second identification circuit includes a turn-off delay circuit, a third NOT gate and a second AND gate. The input end of the shutdown delay circuit and the first input end of the second AND gate receive the initial pulse signal of the second switch tube, and the output end of the shutdown delay circuit outputs the delayed pulse signal of the second switch tube; the second input end of the second AND gate and the input end of the third NOT gate receive the delayed pulse signal, the output end of the second AND gate outputs a high valid signal of the second switch tube, and the output end of the third NOT gate outputs a low valid signal of the second switch tube.
6. The power converter according to claim 2, characterized in that: The timing control circuit includes a first control circuit corresponding to the first switch tube, The first control circuit includes a third AND gate, a fourth AND gate, a fifth AND gate and a sixth AND gate, wherein the output end of the previous AND gate is connected to the first input end of the next AND gate; the first input end of the third AND gate receives the delayed pulse signal of the first switch tube, the second input end of the third AND gate receives the high effective signal of the second switch tube, the second input end of the fourth AND gate receives the low effective signal of the third switch tube, the second input end of the fifth AND gate receives the low effective signal of the fifth switch tube, the second input end of the sixth AND gate receives the low effective signal of the fourth switch tube, and the output end of the sixth AND gate outputs the target pulse signal of the first switch tube.
7. The power converter according to claim 6, characterized in that: The timing control circuit further includes a fourth control circuit corresponding to the fourth switch tube; The fourth control circuit includes a seventh AND gate, an eighth AND gate, a ninth AND gate and a tenth AND gate, wherein the output end of the previous AND gate is connected to the first input end of the next AND gate; the first input end of the seventh AND gate receives the delayed pulse signal of the fourth switch tube, the second input end of the seventh AND gate receives the high effective signal of the third switch tube, the second input end of the eighth AND gate receives the low effective signal of the sixth switch tube, the second input end of the ninth AND gate receives the low effective signal of the second switch tube, the second input end of the tenth AND gate receives the low effective signal of the first switch tube, and the output end of the tenth AND gate outputs the target pulse signal of the fourth switch tube.
8. The power converter according to claim 2, characterized in that: The timing control circuit includes a second control circuit corresponding to the second switch tube, The second control circuit includes an eleventh AND gate, a first input end of the eleventh AND gate receives the delayed pulse signal of the second switch tube, a second input end of the eleventh AND gate receives the low effective signal of the fourth switch tube, and an output end of the eleventh AND gate outputs the target pulse signal of the second switch tube.
9. The power converter according to claim 8, characterized in that: The timing control circuit also includes a third control circuit corresponding to the third switch tube; The third control circuit includes a twelfth AND gate, a first input end of the twelfth AND gate receives the delayed pulse signal of the third switch tube, a second input end of the twelfth AND gate receives the low effective signal of the first switch tube, and an output end of the twelfth AND gate outputs the target pulse signal of the third switch tube.
10. The power converter according to claim 2, characterized in that: The timing control circuit includes a fifth control circuit corresponding to the fifth switch tube, The fifth control circuit includes a thirteenth AND gate and a fourteenth AND gate, wherein the output end of the thirteenth AND gate is connected to the first input end of the fourteenth AND gate; the first input end of the thirteenth AND gate receives the delayed pulse signal of the fifth switch tube, the second input end of the thirteenth AND gate receives the high effective signal of the second switch tube, the second input end of the fourteenth AND gate receives the low effective signal of the first switch tube, and the output end of the fourteenth AND gate outputs the target pulse signal of the fifth switch tube.
11. The power converter according to claim 10, characterized in that: The timing control circuit further includes a sixth control circuit corresponding to the sixth switch tube; The sixth control circuit includes a fifteenth AND gate and a sixteenth AND gate, wherein the output end of the fifteenth AND gate is connected to the first input end of the sixteenth AND gate; the first input end of the fifteenth AND gate receives the delayed pulse signal of the sixth switch tube, the second input end of the fifteenth AND gate receives the high valid signal of the third switch tube, the second input end of the sixteenth AND gate receives the low valid signal of the fourth switch tube, and the output end of the sixteenth AND gate outputs the target pulse signal of the sixth switch tube.
12. The power converter according to claim 4, characterized in that: The conduction delay circuit includes a first diode, a first resistor and a first capacitor. The first resistor is connected between the input and output ends of the conduction delay circuit, the anode of the first diode is connected to the output end, the cathode of the first diode is connected to the input end, one end of the first capacitor is connected to the output end, and the other end of the first capacitor is grounded.
13. The power converter according to claim 5, characterized in that: The turn-off delay circuit includes a second diode, a second resistor and a second capacitor. The second resistor is connected between the input and output ends of the shutdown delay circuit, the anode of the second diode is connected to the input end, the cathode of the second diode is connected to the output end, one end of the second capacitor is connected to the output end, and the other end of the second capacitor is grounded.
14. A photovoltaic system, characterized in that: The photovoltaic system comprises the power converter according to any one of claims 1 to 13.