Power module lead interconnection structure capable of reducing thermal stress
By welding or sintering a gold gasket on a power semiconductor chip and connecting it with metal bond wires, the problem of thermal stress caused by mismatch of thermal expansion coefficient in the prior art is solved, and the reliability of the power module is significantly improved and life.
Patent Information
- Application Number
- CN202420425020.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-05
- Publication Date
- 2025-02-14
- Estimated Expiration
- 2034-03-05
AI Technical Summary
In the prior art, the electrical connection between the power semiconductor chip and the substrate is through the copper gasket and the copper bonding wire, resulting in mismatch between the thermal expansion coefficient between the copper gasket and the chip, causing the problem of large thermal stress.
Alloy gaskets are soldered or sintered on the upper surface of the power semiconductor chip, and electrically connected on the alloy gaskets through metal bonding wires. The equivalent thermal expansion coefficient of the alloy gaskets is designed between 6.0 and 12.0ppm, which is between the chip and the thermal expansion coefficient of the metal bond wire.
Through the design of the alloy gasket, the thermal stress between the bonding wire and the chip is significantly reduced, and the reliability and power cycle life of the power module are improved.
Smart Images
Figure CN222483379U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of semiconductor chips, in particular to a power module lead interconnection structure capable of reducing thermal stress. Background Art
[0002] The power module is mainly composed of a metal base plate, a welding layer, a substrate, a power semiconductor chip, and bonding wires; the power semiconductor chip is fixed to the substrate by welding or metal sintering, and then electrically connected through aluminum bonding wires or copper gaskets and copper bonding wires, and then the substrate is welded or sintered to the metal base plate through processes such as reflow soldering or sintering; the heat generated by the power semiconductor chip is conducted to the metal base plate through the substrate and the welding layer, and finally the heat is dissipated through the coolant.
[0003] In existing products, the electrical connection between power semiconductor chips and substrates is mainly through copper gaskets and copper bonding wires; the use of copper gaskets and copper bonding wires is called the DTS solution in the industry, and is the mainstream solution in the current industry to improve the reliability of bonding wire connections; the specific operation of the DTS solution is: by welding or sintering copper gaskets on the power semiconductor chips, and then bonding copper bonding wires on the copper gaskets. Although this improvement solution solves the problem of mismatch in thermal expansion coefficients between the bonding wire material and the gasket material, the thermal expansion coefficient of the copper gasket is still very different from that of the silicon-based chip or silicon carbide chip, so the problem of high thermal stress between the copper gasket and the power semiconductor chip still exists. Utility Model Content
[0004] In order to solve the above problems in the prior art, the utility model provides a power module lead interconnection structure that reduces thermal stress, thereby improving the problem of excessive thermal stress between metal bonding wires and chip materials.
[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:
[0006] As one aspect of the utility model, a power module lead interconnection structure for reducing thermal stress is provided, which comprises: a copper-clad ceramic substrate and a power semiconductor chip, wherein the power semiconductor chip is connected to the copper-clad ceramic substrate;
[0007] An alloy gasket is connected to the upper surface of the power semiconductor chip, and the alloy gasket and the corresponding area of the copper-clad ceramic substrate are interconnected through metal bonding wires to form a required interconnection circuit.
[0008] Optionally, the copper-clad ceramic substrate includes a copper-clad ceramic substrate ceramic layer, the copper-clad ceramic substrate ceramic layer has a first surface and a second surface arranged opposite to each other, a first connecting copper layer is connected to the first surface, and a second connecting copper layer is connected to the second surface.
[0009] Optionally, the material of the connection surface of the alloy gasket for connecting with the metal bonding wire is the same as the material of the metal bonding wire.
[0010] Optionally, the alloy gasket includes a first buffer layer, a second buffer layer and a third buffer layer connected in sequence from top to bottom; the third buffer layer is connected to the upper surface of the power semiconductor chip, and the connection surface of the first buffer layer is connected to the corresponding area of the copper-clad ceramic substrate through a metal bonding wire.
[0011] Optionally, the metal bonding wire is a copper bonding wire, an aluminum bonding wire or a magnesium-aluminum alloy bonding wire.
[0012] Optionally, the material of the first buffer layer is the same as that of the metal bonding wire; the material of the second buffer layer is molybdenum, molybdenum alloy or iron-nickel alloy; the material of the third buffer layer is copper, copper alloy, aluminum, aluminum alloy or magnesium-aluminum alloy.
[0013] Optionally, the alloy gasket has an equivalent thermal expansion coefficient of 6.0 to 12.0 ppm.
[0014] Optionally, a heat sink is also included, and the heat sink is connected to the copper-clad ceramic substrate.
[0015] Optionally, the heat conducting surface of the heat sink is connected to the copper-clad ceramic substrate via a third sintered layer.
[0016] Optionally, the power semiconductor chip is connected to the copper-clad ceramic substrate through a first sintering layer.
[0017] Optionally, the upper surface of the power semiconductor chip is connected to the alloy gasket via a second sintering layer.
[0018] The utility model has the beneficial effects of reducing thermal stress of power module lead interconnection structure, which is specifically embodied in: 1. In order to improve the problem of excessive thermal stress between metal bonding wire and power semiconductor chip, the present application adopts alloy gasket to be welded or sintered on the upper surface of power semiconductor chip, and then the electrical connection between power semiconductor chip and copper-clad ceramic substrate is made through metal bonding wire on the alloy gasket;
[0019] 2. By designing the alloy gasket into a first buffer layer, a second buffer layer and a third buffer layer structure connected sequentially from top to bottom, the equivalent thermal expansion coefficient of the alloy gasket is between 6.0 and 12.0 ppm. Therefore, the overall equivalent thermal expansion coefficient of the alloy gasket is slightly larger than the thermal expansion coefficient of power semiconductor chips such as silicon-based chips or silicon carbide chips, which is 3.0 to 6.0 ppm, and slightly smaller than the thermal expansion coefficient of metal bonding wires, which is 17.0 to 25.0 ppm. Therefore, the equivalent thermal expansion coefficient of the alloy gasket is between the thermal expansion coefficient of the power semiconductor chip and the thermal expansion coefficient of the metal bonding wire, and its equivalent thermal expansion coefficient will neither be seriously mismatched with the thermal expansion coefficient of the power semiconductor chip nor with the thermal expansion coefficient of the metal bonding wire, which plays a role in greatly reducing the thermal stress between the bonding wire and the chip, and ultimately significantly improves the overall reliability and power cycle life of the power module. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The drawings in the specification, which constitute a part of the present application, are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation on the present invention.
[0021] Figure 1 This is a structural stereogram of a power module lead interconnection structure for reducing thermal stress of the utility model;
[0022] Figure 2 It is a top view of the structure of the power module lead interconnection structure for reducing thermal stress of the utility model;
[0023] Figure 3 It is a structural side view of the power module lead interconnection structure for reducing thermal stress of the utility model;
[0024] Figure 4 for Figure 3 Partial schematic diagram at point A in the middle;
[0025] Figure 5 It is a structural schematic diagram of the alloy gasket of the utility model. DETAILED DESCRIPTION
[0026] In order to make the purpose, technical solution and advantages of the utility model clearer, the technical solution of the utility model will be clearly and completely described below in combination with the specific embodiments of the utility model and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the utility model.
[0027] A power module lead interconnection structure for reducing thermal stress according to an embodiment of the present application is as follows: Figure 1-Figure 4 As shown, it comprises: a copper-clad ceramic substrate 1 and a power semiconductor chip 2, wherein the copper-clad ceramic substrate 1 plays the role of current conduction, insulation, heat conduction and mechanical support; the copper-clad ceramic substrate 1 comprises a copper-clad ceramic substrate ceramic layer 11, wherein the copper-clad ceramic substrate ceramic layer 11 has a first surface and a second surface arranged oppositely, wherein a first connection copper layer 12 is connected to the first surface, and a second connection copper layer 13 is connected to the second surface;
[0028] The power semiconductor chip 2 is connected to the first connection copper layer 12 through the first sintering layer 3; it should be noted that the power semiconductor chip 2 has a chip gate level 21, a chip Kelvin source 22, a chip source 23 and a chip drain 24, and the chip gate level 21, the chip Kelvin source 22, the chip source 23 and the chip drain 24 are all connected to the corresponding areas of the first connection copper layer 12. This structure is a prior art and will not be repeated here;
[0029] The upper surface of the power semiconductor chip 2 is connected to an alloy gasket 5 through a second sintered layer 4, and the alloy gasket 5 is interconnected with the corresponding area of the copper-clad ceramic substrate 1 through a metal bonding wire 6 to form a required interconnection circuit; the material of the connection surface of the alloy gasket 5 used for connecting to the metal bonding wire 6 is the same as the material of the metal bonding wire 6; the metal bonding wire 6 is a copper bonding wire, an aluminum bonding wire or a magnesium-aluminum alloy bonding wire.
[0030] During normal operation of the power module, the switching and conduction of the power semiconductor chip 2 generates heat loss, which is dissipated outward through the copper-clad ceramic substrate 1 and the heat sink 7. When high and low temperature changes such as temperature shock and power cycling occur, the thermal expansion coefficients of the metal bonding wire 6 and the power semiconductor chip 2 are seriously mismatched, resulting in very large thermal stress between the metal bonding wire 6 and the power semiconductor chip 2, which in turn causes the metal bonding wire 6 to break or fall off from the power semiconductor chip 2, ultimately reducing the reliability and power cycle life of the power module.
[0031] In order to improve the problem of excessive thermal stress between the metal bonding wire 6 and the power semiconductor chip 2, the present application adopts an alloy gasket 5 welded or sintered on the upper surface of the power semiconductor chip 2, and then the electrical connection between the power semiconductor chip 2 and the copper-clad ceramic substrate 1 is made through the metal bonding wire 6 on the alloy gasket 5.
[0032] In one embodiment, if Figure 5As shown, the alloy gasket 5 includes a first buffer layer 51, a second buffer layer 52 and a third buffer layer 53 which are connected in sequence from top to bottom; the third buffer layer 53 is connected to the upper surface of the power semiconductor chip 2 by welding or metal sintering, and the connection surface of the first buffer layer 51 is connected to the corresponding area of the copper-clad ceramic substrate 1 by a metal bonding wire 6; because the metal bonding wire 6 is directly bonded to the first buffer layer 51, it belongs to the same material bonding, and there is no problem of equivalent thermal expansion coefficient mismatch, so the connection reliability is high; the material of the first buffer layer 51 is the same as that of the metal bonding wire 6; the material of the second buffer layer 52 is molybdenum, molybdenum alloy or iron-nickel alloy; the third buffer layer 53 must consider the material of the second buffer layer 52 and the upper surface metal of the power semiconductor chip at the same time, and the material of the third buffer layer 53 is copper, copper alloy, aluminum, aluminum alloy or magnesium-aluminum alloy.
[0033] In addition, by designing the alloy gasket 5 to be a first buffer layer 51, a second buffer layer 52, and a third buffer layer 53 structure connected sequentially from top to bottom, the equivalent thermal expansion coefficient of the alloy gasket 5 is between 6.0 and 12.0 ppm. Therefore, the overall equivalent thermal expansion coefficient of the alloy gasket 5 is slightly larger than the thermal expansion coefficient of the power semiconductor chip 2, such as a silicon-based chip or a silicon carbide chip, which is 3.0 to 6.0 ppm, and is slightly smaller than the thermal expansion coefficient of the metal bonding wire, which is
[0034] 17.0~25.0ppm, so the equivalent thermal expansion coefficient of the alloy gasket 5 is between the thermal expansion coefficient of the power semiconductor chip 2 and the thermal expansion coefficient of the metal bonding wire, and its equivalent thermal expansion coefficient is neither seriously mismatched with the thermal expansion coefficient of the power semiconductor chip 2 nor seriously mismatched with the thermal expansion coefficient of the metal bonding wire, which plays a role in greatly reducing the thermal stress between the bonding wire and the chip, and ultimately significantly improves the overall reliability and power cycle life of the power module.
[0035] In one embodiment, if Figure 1-Figure 4 As shown, it also includes a heat sink 7, which is connected to the copper-clad ceramic substrate 1. The second connecting copper layer 13 of the copper-clad ceramic substrate 1 is connected to the heat conducting surface of the heat sink 7. The heat sink 7 plays a role of heat conduction and mechanical support.
[0036] In one embodiment, the heat conducting surface of the heat sink 7 and the second connecting copper layer 13 are connected via a third sintering layer 8 .
[0037] In one embodiment, the first sintered layer 3, the second sintered layer 4 and the third sintered layer 8 are all metal sintered layers; the metal sintered layers have good high temperature resistance, good connection reliability in a high temperature environment, and good thermal conductivity, which can not only improve the connection reliability of the packaging structure in a high temperature working environment, but also accelerate the heat conduction of the device and improve the heat dissipation performance.
[0038] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.
[0039] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values of the parts and steps set forth in these embodiments do not limit the scope of the present application. Meanwhile, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, methods and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology, methods and equipment should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and therefore, once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.
[0040] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.
[0041] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" may include both "above" and "below". The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.
[0042] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of this application.
[0043] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0044] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.
Claims
1. A power module lead interconnection structure for reducing thermal stress, characterized in that: It includes: A copper-clad ceramic substrate and a power semiconductor chip, wherein the power semiconductor chip is connected to the copper-clad ceramic substrate; An alloy gasket is connected to the upper surface of the power semiconductor chip, and the alloy gasket and the corresponding area of the copper-clad ceramic substrate are interconnected through metal bonding wires to form a required interconnection circuit.
2. The power module lead interconnect structure for reducing thermal stress according to claim 1, characterized in that: The copper-clad ceramic substrate comprises a copper-clad ceramic substrate ceramic layer, wherein the copper-clad ceramic substrate ceramic layer has a first surface and a second surface arranged opposite to each other, wherein a first connection copper layer is connected to the first surface, and a second connection copper layer is connected to the second surface.
3. The power module lead interconnection structure for reducing thermal stress according to claim 1, characterized in that: The material of the connection surface of the alloy gasket used for connecting with the metal bonding wire is the same as the material of the metal bonding wire.
4. The power module lead interconnection structure for reducing thermal stress according to claim 1, characterized in that: The alloy gasket includes a first buffer layer, a second buffer layer and a third buffer layer connected in sequence from top to bottom; the third buffer layer is connected to the upper surface of the power semiconductor chip, and the connection surface of the first buffer layer is connected to the corresponding area of the copper-clad ceramic substrate through a metal bonding wire.
5. The power module lead interconnection structure for reducing thermal stress according to claim 1, characterized in that: The metal bonding wire is a copper bonding wire, an aluminum bonding wire or a magnesium-aluminum alloy bonding wire.
6. The power module lead interconnection structure for reducing thermal stress according to claim 4, characterized in that: The material of the first buffer layer is the same as that of the metal bonding wire; the material of the second buffer layer is molybdenum, molybdenum alloy or iron-nickel alloy; the material of the third buffer layer is copper, copper alloy, aluminum, aluminum alloy or magnesium-aluminum alloy.
7. The power module lead interconnection structure for reducing thermal stress according to claim 3, characterized in that: The equivalent thermal expansion coefficient of the alloy gasket is 6.0-12.0 ppm.
8. The power module lead interconnection structure for reducing thermal stress according to any one of claims 1 to 7, characterized in that: The invention also comprises a heat sink, which is connected to the copper-clad ceramic substrate.
9. The power module lead interconnection structure for reducing thermal stress according to claim 8, characterized in that: The heat conducting surface of the heat sink is connected to the copper-clad ceramic substrate via a third sintering layer.
10. The power module lead interconnection structure for reducing thermal stress according to any one of claims 1 to 7, characterized in that: The power semiconductor chip is connected to the copper-clad ceramic substrate through a first sintering layer.
11. The power module lead interconnection structure for reducing thermal stress according to any one of claims 1 to 7, characterized in that: The upper surface of the power semiconductor chip is connected to the alloy gasket via a second sintering layer.