Array substrate and display panel

Abstract

The utility model provides an array substrate and a display panel. The array substrate comprises a substrate, a first metal layer and a first transparent conductive layer. The first metal layer is disposed on one side of the substrate and includes a metal member. The metal component comprises a metal side wall and a metal top surface connected with the metal side wall, and the metal top surface is the surface, away from the substrate, of the metal component. The first transparent conductive layer is disposed on one side of the substrate and includes a transparent conductive member. The transparent conductive member comprises a first transparent conductive sub-layer and a second transparent conductive sub-layer, the first transparent conductive sub-layer extends from the substrate to be in contact with the metal side wall, and the second transparent conductive sub-layer is located on the side, away from the substrate, of the first transparent conductive sub-layer and extends from the first transparent conductive sub-layer to be in contact with the metal top face.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] For display devices, indium tin oxide film is a common transparent conductive film in the display field. Indium tin oxide film is generally prepared by magnetron sputtering. At present, overlapping the indium tin oxide film on the metal layer to achieve connection between the indium tin oxide film and the metal layer is a common overlapping method. However, when the indium tin oxide film is overlapped with the metal layer, overlapping defects are prone to occur, such as the breakage of the indium tin oxide film, which in turn affects the display effect of the display device.

[0003] Therefore, it is necessary to propose a technical solution to improve the problem of overlapping defects between the indium tin oxide film and the metal layer. Utility Model Content

[0004] The present application provides an array substrate and a display panel to reduce the risk of overlapping defects when a transparent conductive component and a metal component on the array substrate are overlapped, thereby improving the display effect of the display panel.

[0005] In a first aspect, the present application provides an array substrate, comprising:

[0006] substrate;

[0007] a first metal layer, disposed on one side of the substrate, and comprising a metal component, wherein the metal component comprises a metal sidewall and a metal top surface connected to the metal sidewall, wherein the metal top surface is a surface of the metal component away from the substrate; and

[0008] A first transparent conductive layer is arranged on one side of the substrate and includes a transparent conductive component, wherein the transparent conductive component includes a first transparent conductive sublayer and a second transparent conductive sublayer, wherein the first transparent conductive sublayer extends from the substrate to contact the metal side wall, and the second transparent conductive sublayer is located on a side of the first transparent conductive sublayer away from the substrate and extends from the first transparent conductive sublayer to contact the metal top surface.

[0009] In some embodiments, the transparent conductive component further includes: a third transparent conductive sublayer, which is located on a side of the second transparent conductive sublayer away from the substrate and extends from the second transparent conductive sublayer to contact the metal top surface.

[0010] In some embodiments, a thickness of the third transparent conductive sublayer and a thickness of the second transparent conductive sublayer are less than a thickness of the first transparent conductive sublayer.

[0011] In some embodiments, the thickness of the first metal layer is greater than or equal to 1000 angstroms and less than or equal to 6000 angstroms;

[0012] The thickness of the third transparent conductive sublayer and the thickness of the second transparent conductive sublayer are both greater than or equal to 80 angstroms and less than or equal to 150 angstroms, and the thickness of the first transparent conductive sublayer is greater than or equal to 160 angstroms and less than or equal to 250 angstroms.

[0013] In some embodiments, the density of the third transparent conductive sublayer and the second transparent conductive sublayer is greater than the density of the first transparent conductive sublayer.

[0014] In some embodiments, the first transparent conductive sublayer includes a first transparent sidewall away from the metal member;

[0015] The second transparent conductive sublayer includes a second transparent side wall away from the metal component, and the second transparent side wall is disposed adjacent to the first transparent side wall; and

[0016] The third transparent conductive sublayer comprises a third transparent side wall away from the metal component, and the third transparent side wall is arranged adjacent to the second transparent side wall;

[0017] The second transparent side wall is located on a side of the first transparent side wall close to the metal component, and the third transparent side wall is located on a side of the second transparent side wall close to the metal component; or the first transparent side wall, the second transparent side wall and the third transparent side wall are coplanar.

[0018] In some embodiments, the first transparent conductive sublayer, the second transparent conductive sublayer, and the third transparent conductive sublayer include at least one of an indium tin oxide layer and an indium zinc oxide layer, and the first metal layer includes at least one of a copper layer, a molybdenum layer, an aluminum layer, a titanium layer, a copper alloy layer, a titanium alloy layer, a molybdenum alloy layer, and an aluminum alloy layer.

[0019] In some embodiments, the first transparent conductive sublayer includes a first transparent bottom surface, the first transparent bottom surface extends from the substrate to contact the metal side wall of the metal component, and the first transparent bottom surface is a surface of the first transparent conductive sublayer close to the substrate;

[0020] The first transparent conductive sublayer also includes a fourth transparent side wall, which is connected to the first transparent bottom surface and is arranged adjacent to the metal side wall, at least a portion of the fourth transparent side wall is coplanar with at least a portion of the metal top surface, and the second transparent conductive sublayer extends from the surface of the first transparent conductive sublayer away from the substrate to the fourth transparent side wall and the metal top surface.

[0021] In some embodiments, the metal member includes a drain electrode, and the transparent conductive member includes a pixel electrode.

[0022] In some embodiments, the first metal layer further includes a source electrode spaced apart from the drain electrode, and the array substrate further includes:

[0023] A second metal layer, disposed between the first metal layer and the substrate, and comprising a gate;

[0024] a gate insulating layer, disposed between the second metal layer and the first metal layer, and covering the second metal layer and the substrate;

[0025] an active layer, disposed between the first metal layer and the gate insulating layer, at least a portion of the source electrode and at least a portion of the drain electrode being disposed on the active layer, and the pixel electrode extending from the gate insulating layer through a side wall of the active layer and a side wall of the drain electrode to a surface of the drain electrode away from the substrate;

[0026] a passivation layer covering the first metal layer, the first transparent conductive layer, the active layer and the gate insulating layer; and

[0027] The second transparent conductive layer is arranged on a side of the passivation layer away from the substrate.

[0028] In a second aspect, the present application further provides a display panel, which includes the array substrate of any of the above embodiments.

[0029] In some embodiments of the present application, the transparent conductive component includes a first transparent conductive sublayer and a second transparent conductive sublayer. The first transparent conductive sublayer extends from the substrate to contact the metal side wall of the metal component. The second transparent conductive sublayer is located on the side of the first transparent conductive sublayer away from the substrate and extends from the first transparent conductive sublayer to contact the metal top surface. In this way, the first transparent conductive sublayer acts as a step to reduce the climbing height and climbing slope when the second transparent conductive sublayer overlaps the metal top surface of the metal component, thereby reducing the risk of fracture of the second transparent conductive sublayer due to the large climbing height and climbing slope. In addition, the first transparent conductive sublayer contacts the metal side wall of the metal component, which can increase the contact area between the transparent conductive component and the metal component, reduce the overlapping impedance between the transparent conductive component and the metal component, and further improve the problem of thin thickness and poor contact of the transparent conductive component. Therefore, the overlap yield between the transparent conductive component and the metal component is improved, which is conducive to improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic cross-sectional structure diagram of an array substrate of some embodiments provided in the present application;

[0031] Figure 2 Schematic diagrams of cross-sectional structures of array substrates of other embodiments provided in the present application;

[0032] Figure 3 to Figure 4 A structural schematic diagram of the manufacturing process of the array substrate provided in this application.

[0033] The reference numerals are as follows:

[0034] 100, array substrate; 10, substrate;

[0035] 11, first metal layer; 111, metal component; 111a, metal sidewall; 111b, metal top surface; 111c, metal bottom surface; 112, drain; 113, source;

[0036] 12, a first transparent conductive layer;

[0037] 121, a transparent conductive member; 125, a pixel electrode;

[0038] 122, first transparent conductive sublayer; 122a, first transparent side wall; 122b, first transparent bottom surface; 122c, fourth transparent side wall;

[0039] 123, second transparent conductive sublayer; 123a, second transparent side wall; 123b, second transparent bottom surface;

[0040] 124, a third transparent conductive sublayer; 124a, a third transparent side wall; 125, a pixel electrode;

[0041] 126, a first initial transparent conductive sublayer;

[0042] 13, second metal layer; 131, gate; 14, gate insulating layer; 15, active layer; 16, passivation layer; 17, second transparent conductive layer. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0044] Please refer to Figure 1 and Figure 2 As shown, Figure 1 The cross-sectional structure diagram of the array substrate of some embodiments provided in the present application is as follows: Figure 2 Schematic diagrams of cross-sectional structures of array substrates of other embodiments provided in the present application.

[0045] like Figure 1 and Figure 2 As shown, the array substrate 100 includes a substrate 10, a first metal layer 11 and a first transparent conductive layer 12. The first metal layer 11 and the first transparent conductive layer 12 are disposed on the same side of the substrate 10.

[0046] like Figure 1 and Figure 2 As shown, the first metal layer 11 includes a metal component 111. The metal component 111 includes a metal sidewall 111a and a metal top surface 111b connected to the metal sidewall 111a. The metal top surface 111b is a surface of the metal component 111 away from the substrate 10.

[0047] The metal component 111 may include at least one of a metal block and a metal wire. The shape of the metal block may be at least one of a rectangle, a chamfered rectangle, a circle, and an irregular shape. The metal wire may include at least one of a straight line segment and a non-straight line segment.

[0048] In some embodiments, the metal top surface 111 b may include an uneven surface. The metal top surface 111 b may also include a planar surface.

[0049] In some embodiments, the slope angle of the metal sidewall 111a is greater than or equal to 40 degrees and less than 90 degrees. Optionally, the slope angle of the metal sidewall 111a is greater than or equal to 50 degrees and less than or equal to 80 degrees. The slope angle of the metal sidewall 111a is equal to the angle between the orthographic projection of the metal bottom surface 111c of the metal component 111 on the substrate 10 and the metal sidewall 111a, and the metal bottom surface 111c is arranged opposite to the metal top surface 111b. In this way, the slope angle of the metal sidewall 111a is small, reducing the risk of fracture of the film layer climbing on the metal sidewall 111a of the metal component 111.

[0050] In some embodiments, the thickness of the first metal layer 11 is greater than or equal to 1000 angstroms and less than or equal to 6000 angstroms. Optionally, the thickness of the first metal layer 11 is greater than or equal to 2000 angstroms and less than or equal to 5000 angstroms. Optionally, the thickness of the first metal layer 11 is greater than or equal to 2500 angstroms and less than or equal to 4500 angstroms. In this way, the thickness of the first metal layer 11 is ensured to be thicker to reduce the impedance of the first metal layer 11, improve the problem of increased process difficulty caused by the first metal layer 11 being too thick, and reduce the risk of easy fracture of the film layer climbing on the metal sidewall 111a due to the first metal layer 11 being too thick.

[0051] In some embodiments, the first metal layer 11 includes at least one of a copper layer, a molybdenum layer, an aluminum layer, a titanium layer, a copper alloy layer, a titanium alloy layer, a molybdenum alloy layer, and an aluminum alloy layer. For example, the first metal layer 11 includes a copper layer to reduce the impedance of the first metal layer 11.

[0052] like Figure 1 and Figure 2 As shown, the first transparent conductive layer 12 includes a transparent conductive member 121, and the transparent conductive member 121 overlaps the metal member 111. The transparent conductive member 121 includes a first transparent conductive sublayer 122 and a second transparent conductive sublayer 123. The first transparent conductive sublayer 122 extends from the substrate 10 to contact the metal side wall 111a. The second transparent conductive sublayer 123 is located on the side of the first transparent conductive sublayer 122 away from the substrate 10 and extends from the first transparent conductive sublayer 122 to contact the metal top surface 111b. In this way, the first transparent conductive sublayer 122 acts as a step to reduce the climbing height and climbing slope when the second transparent conductive sublayer 123 overlaps the metal top surface 111b of the metal member 111, thereby reducing the risk of fracture of the second transparent conductive sublayer 123 due to the large climbing height and climbing slope. Furthermore, the first transparent conductive sublayer 122 contacts the metal sidewall 111 a of the metal component 111 , which can increase the contact area between the transparent conductive component 121 and the metal component 111 and reduce the overlap impedance between the transparent conductive component 121 and the metal component 111 .

[0053] It should be noted that in some related technologies, when the transparent electrode overlaps the metal electrode, factors such as the film thickness of the transparent electrode and the slope of the side wall of the metal electrode affect the overlapping effect. Specifically, these factors may cause overlapping defects when the transparent electrode climbs on the side wall of the metal electrode. The overlapping defects include transparent electrode breakage, transparent electrode thinness, and poor contact between the transparent electrode and the metal electrode.

[0054] In the present application, compared with the related art, the transparent conductive component 121 of the present application is additionally provided with a first transparent conductive sub-layer 122. The first transparent conductive sub-layer 122 can reduce the risk of the second transparent conductive sub-layer 123 breaking during the climbing process, and increase the contact area between the transparent conductive component 121 and the metal component 111, reduce the risk of the local thickness of the transparent conductive component 121 being too thin and the contact being poor, and reduce the overlap impedance between the transparent conductive component 121 and the metal component 111.

[0055] like Figure 1 and Figure 2 As shown, the first transparent conductive sublayer 122 includes a first transparent side wall 122 a away from the metal member 111 , and the first transparent side wall 122 a may be tilted relative to the substrate 10 .

[0056] like Figure 1 and Figure 2As shown, the first transparent conductive sublayer 122 also includes a first transparent bottom surface 122b, which is connected to the first transparent side wall 122a. The first transparent bottom surface 122b is the surface of the first transparent conductive sublayer 122 close to the substrate 10. The first transparent bottom surface 122b extends from the substrate 10 to contact the metal side wall 111a of the metal component 111. In this way, the film thickness of the transparent conductive component 121 at the metal side wall 111a is increased, and the risk of the transparent conductive component 121 having a thin local thickness at the metal side wall 111a is reduced. In addition, the first transparent bottom surface 122b is in contact with the metal side wall 111a, which can also increase the contact area between the transparent conductive component 121 and the metal component 111, and further reduce the risk of poor contact between the transparent conductive component 121 and the metal component 111.

[0057] like Figure 1 and Figure 2 As shown, in some embodiments, the first transparent conductive sublayer 122 further includes a fourth transparent sidewall 122c connected to the first transparent bottom surface 122b and disposed adjacent to the metal sidewall 111a, and at least a portion of the fourth transparent sidewall 122c is coplanar with at least a portion of the metal top surface 111b. In this way, the flatness of the second transparent conductive sublayer 123 when extending from the fourth transparent sidewall 122c of the first transparent conductive sublayer 122 to the metal top surface 111b is improved, and the risk of the second transparent conductive sublayer 123 being broken is reduced.

[0058] It should be noted that if Figure 3 As shown, the entire transparent conductive layer is patterned to form a first initial transparent conductive sublayer 126, which extends from the gate insulating layer 14 along the sidewalls of the active layer 15 and the sidewalls of the drain 112 to the surface of the drain 112 away from the substrate 10. Figure 4 As shown, the portion of the first initial transparent conductive sublayer 126 located on the metal top surface 111b of the metal component 111 is removed to form the first transparent conductive sublayer 122. The portion of the first transparent conductive sublayer 122 located on the metal top surface 111b of the metal component 111 can be removed by a grinding process.

[0059] The second transparent conductive sublayer 123 includes a second transparent sidewall 123 a away from the metal member 111 , and the second transparent sidewall 123 a is disposed adjacent to the first transparent sidewall 122 a .

[0060] The second transparent conductive sublayer 123 further includes a second transparent bottom surface 123b, which is connected to the second transparent side wall 123a. The second transparent bottom surface 123b is the surface of the second transparent conductive sublayer 123 close to the substrate 10. The second transparent bottom surface 123b extends from the surface of the first transparent conductive sublayer 122 away from the substrate 10 to the fourth transparent side wall 122c of the first transparent conductive sublayer 122 and the metal top surface 111b of the metal component 111.

[0061] In some embodiments, the ratio of the area of ​​the metal top surface 111b in contact with the second transparent conductive sub-layer 123 to the area of ​​the metal top surface 111b is greater than or equal to 1 / 2 and less than 1. In this way, the contact area between the second transparent conductive sub-layer 123 and the metal top surface 111b is ensured to be larger, and the risk of the second transparent conductive sub-layer 123 contacting another metal side wall of the metal component 111 (the metal side wall C disposed opposite to the metal side wall 111a) is reduced, thereby reducing the risk of the second transparent conductive sub-layer 123 breaking.

[0062] In some embodiments, Figure 1 and Figure 2 As shown, the transparent conductive member 121 further includes a third transparent conductive sublayer 124. The third transparent conductive sublayer 124 is located on the side of the second transparent conductive sublayer 123 away from the substrate 10 and extends from the second transparent conductive sublayer 123 to contact the metal top surface 111b. In this way, the thickness of the transparent conductive member 121 is further increased, and the overlapping area between the transparent conductive member 121 and the metal top surface 111b is increased, the impedance between the transparent conductive member 121 and the metal member 111 is reduced, and the risk of overlapping failure between the transparent conductive member 121 and the metal member 111 is reduced.

[0063] The third transparent conductive sub-layer 124 includes a third transparent side wall 124 a away from the metal component 111 , and the third transparent side wall 124 a is disposed adjacent to the second transparent side wall 123 a .

[0064] In some embodiments, the transparent conductive member 121 may further include a fourth transparent conductive sublayer (not shown), which is located on the side of the third transparent conductive sublayer 124 away from the substrate 10. Therefore, the transparent conductive member 121 may include four transparent conductive sublayers. It is understood that the transparent conductive member 121 may also include more than four transparent conductive sublayers.

[0065] In some embodiments, the thickness of the third transparent conductive sublayer 124 and the thickness of the second transparent conductive sublayer 123 are less than the thickness of the first transparent conductive sublayer 122. In this way, the first transparent conductive sublayer 122 is ensured to be thicker, and the first transparent conductive sublayer 122 can better reduce the climbing height and climbing slope of the second transparent conductive sublayer 123. In addition, the thickness of the first transparent conductive sublayer 122 is relatively large, which can also significantly reduce the risk of the local thickness of the transparent conductive component 121 being too thin, and reduce the impedance of the transparent conductive component 121.

[0066] In some embodiments, the thickness of the third transparent conductive sublayer 124 and the thickness of the second transparent conductive sublayer 123 are both greater than or equal to 80 angstroms and less than or equal to 150 angstroms. The thickness of the first transparent conductive sublayer 122 is greater than or equal to 160 angstroms and less than or equal to 250 angstroms. In this way, the thickness of the first transparent conductive sublayer 122 is greater than the thickness of the third transparent conductive sublayer 124 and the thickness of the second transparent conductive sublayer 123. If the thickness of the first transparent conductive sublayer 122 is too thin, the effect of reducing the climbing height and climbing slope of the second transparent conductive sublayer 123 is not obvious. If the thickness of the first transparent conductive sublayer 122 is too thick, the difficulty of the manufacturing process of the first transparent conductive sublayer 122 increases. If the thickness of the third transparent conductive sublayer 124 and the thickness of the second transparent conductive sublayer 123 are too thin, it is not conducive to reducing the impedance of the transparent conductive component 121. If the thickness of the third transparent conductive sublayer 124 and the thickness of the second transparent conductive sublayer 123 are too thick, the difficulty of the manufacturing process of both increases.

[0067] In some embodiments, the density of the third transparent conductive sublayer 124 and the second transparent conductive sublayer 123 is greater than that of the first transparent conductive sublayer 122. In this way, the first transparent conductive sublayer 122 can better play a stepping role, reduce the difficulty of the manufacturing process of the first transparent conductive sublayer 122, and ensure that the third transparent conductive sublayer 124 and the second transparent conductive sublayer 123 have better electrical properties.

[0068] It should be noted that the first transparent conductive sublayer 122 can be prepared by a high-speed film-forming process, and the third transparent conductive sublayer 124 and the second transparent conductive sublayer 123 can be prepared by a low-speed film-forming process, so that the density of the third transparent conductive sublayer 124 and the second transparent conductive sublayer 123 is greater than the density of the first transparent conductive sublayer 122.

[0069] In some embodiments, Figure 1 As shown, the first transparent sidewall 122a, the second transparent sidewall 123a and the third transparent sidewall 124a are coplanar. Thus, a single patterning process can be used to form the third transparent conductive sublayer 124, the second transparent conductive sublayer 123 and the first transparent conductive sublayer 122, simplifying the manufacturing process of the transparent conductive component 121.

[0070] In some embodiments, Figure 2 As shown, the second transparent side wall 123a is located on the side of the first transparent side wall 122a close to the metal component 111, and the third transparent side wall 124a is located on the side of the second transparent side wall 123a close to the metal component 111. In this way, the second transparent side wall 123a is retracted relative to the first transparent side wall 122a, and the third transparent side wall 124a is retracted relative to the second transparent side wall 123a, so as to adapt to the manufacturing process of forming the third transparent conductive sub-layer 124, the second transparent conductive sub-layer 123 and the first transparent conductive sub-layer 122 respectively.

[0071] In some embodiments, the first transparent conductive sublayer 122, the second transparent conductive sublayer 123 and the third transparent conductive sublayer 124 include at least one of an indium tin oxide layer and an indium zinc oxide layer. Specifically, the first transparent conductive sublayer 122, the second transparent conductive sublayer 123 and the third transparent conductive sublayer 124 include an indium tin oxide layer.

[0072] In some embodiments, Figure 1 and Figure 2 As shown, the metal component 111 includes the drain electrode 112, and the transparent conductive component 121 includes the pixel electrode, so as to reduce the risk of overlapping failure between the pixel electrode and the drain electrode 112.

[0073] It should be noted that the metal component 111 and the transparent conductive component 121 may also include other structures, for example, the metal component 111 may include a metal portion of a binding pin, and the transparent conductive component 121 may include a transparent conductive portion of a binding pin. The binding pin may be connected to a driving unit, and the driving unit may be a driving chip or a flip chip film.

[0074] In some embodiments, Figure 1 and Figure 2As shown, in the case where the metal component 111 includes the drain electrode 112, the first metal layer 11 also includes a source electrode 113 spaced apart from the drain electrode 112. The array substrate 100 also includes a second metal layer 13, a gate insulating layer 14, an active layer 15, and a passivation layer 16. The second metal layer 13 is disposed between the first metal layer 11 and the substrate 10 and includes a gate 131. The gate insulating layer 14 is disposed between the second metal layer 13 and the first metal layer 11 and covers the second metal layer 13 and the substrate 10. The active layer 15 is disposed between the first metal layer 11 and the gate insulating layer 14, at least a portion of the source electrode 113 and at least a portion of the drain electrode 112 are disposed on the active layer 15, and the pixel electrode 125 extends from the gate insulating layer 14 through the sidewall of the active layer 15 and the sidewall of the drain electrode 112 to the surface of the drain electrode 112 away from the substrate 10. The passivation layer 16 covers the first metal layer 11, the first transparent conductive layer 12, the active layer 15 and the gate insulating layer 14. Therefore, the array substrate 100 includes a thin film transistor, which is a bottom-gate thin film transistor. The thin film transistor includes a source electrode 113, a drain electrode 112, a gate electrode 131 and the active layer 15.

[0075] It is understandable that the second metal layer 13 may also be disposed on the side of the first metal layer 11 facing away from the substrate 10. In this case, the thin film transistor is a top-gate thin film transistor.

[0076] The second metal layer 13 may include at least one of a copper layer, a molybdenum layer, an aluminum layer, a titanium layer, a copper alloy layer, a titanium alloy layer, a molybdenum alloy layer, and an aluminum alloy layer.

[0077] The gate insulating layer 14 and the passivation layer 16 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The thickness of the gate insulating layer 14 may be greater than or equal to 800 angstroms and less than or equal to 1500 angstroms. The thickness of the passivation layer 16 may be greater than the thickness of the gate insulating layer 14. The thickness of the passivation layer 16 may be greater than or equal to 3000 angstroms and less than or equal to 5000 angstroms. The active layer 15 includes at least one of polycrystalline silicon, amorphous silicon, and metal oxide. The thickness of the active layer 15 is greater than or equal to 800 angstroms and less than or equal to 1200 angstroms.

[0078] In some embodiments, Figure 1 and Figure 2 As shown, the array substrate 100 may further include a second transparent conductive layer 17, which is disposed on the side of the passivation layer 16 away from the substrate 10, and the second transparent conductive layer 17 may include a common electrode. The common electrode may include a slit.

[0079] for Figure 1 and Figure 2 The array substrate shown can be manufactured by using five photomasks, thereby reducing the number of photomasks required for manufacturing the array substrate 100 and lowering the cost of manufacturing the array substrate 100 .

[0080] Based on the same inventive concept, the present application also provides a display panel, which may be any one of a liquid crystal display panel, an organic light emitting diode display panel, a quantum dot display panel, a micro light emitting diode display panel, and a sub-millimeter light emitting diode display panel. The display panel may include the array substrate 100 of any of the above embodiments.

[0081] In a specific embodiment, the display panel may be a liquid crystal display panel. In addition to the array substrate 100, the display panel may also include an opposing substrate disposed opposite to the array substrate 100. The opposing substrate may include an opposing base, and any one of a color filter layer and a common electrode may be disposed on the surface of the opposing base close to the array substrate 100.

[0082] In another specific embodiment, the display panel can be an organic light emitting diode display panel or a quantum dot display panel. In addition to the above-mentioned array substrate 100, the array substrate 100 includes a thin film transistor but does not include the second transparent conductive layer 17, and can also include an organic light emitting array layer or a quantum light emitting array layer.

[0083] In another specific embodiment, the display panel may be any one of a micro light emitting diode display panel and a sub-millimeter light emitting diode display panel.

[0084] In the present application, the overlap yield between the metal component 111 and the transparent conductive component 121 of the array substrate 100 of the display panel is improved, which is beneficial to improving the display effect of the display panel. In addition, when the overlap yield is high, the thickness of the metal component 111 can be thicker, which is beneficial for the display panel to achieve high refresh rate and high charge rate display.

[0085] Based on the same inventive concept, the present application also provides a display device, which can be applied to a mobile terminal, a tablet computer, a notebook, and a display screen. The display device includes the above-mentioned display panel.

[0086] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A first metal layer is disposed on one side of the substrate and includes a metal component, wherein the metal component includes a metal sidewall and a metal top surface connected to the metal sidewall, and the metal top surface is a surface of the metal component away from the substrate; as well as A first transparent conductive layer is arranged on one side of the substrate and includes a transparent conductive component, wherein the transparent conductive component includes a first transparent conductive sublayer and a second transparent conductive sublayer, wherein the first transparent conductive sublayer extends from the substrate to contact the metal side wall, and the second transparent conductive sublayer is located on a side of the first transparent conductive sublayer away from the substrate and extends from the first transparent conductive sublayer to contact the metal top surface.

2. The array substrate according to claim 1, characterized in that: The transparent conductive component further includes: a third transparent conductive sublayer, which is located on a side of the second transparent conductive sublayer away from the substrate and extends from the second transparent conductive sublayer to contact the metal top surface.

3. The array substrate according to claim 2, characterized in that: The thickness of the third transparent conductive sublayer and the thickness of the second transparent conductive sublayer are smaller than the thickness of the first transparent conductive sublayer.

4. The array substrate according to claim 2, characterized in that: The density of the third transparent conductive sublayer and the second transparent conductive sublayer is greater than the density of the first transparent conductive sublayer.

5. The array substrate according to claim 2, characterized in that: The first transparent conductive sublayer includes a first transparent side wall away from the metal component; The second transparent conductive sublayer comprises a second transparent side wall away from the metal component, and the second transparent side wall is disposed adjacent to the first transparent side wall; as well as The third transparent conductive sublayer comprises a third transparent side wall away from the metal component, and the third transparent side wall is arranged adjacent to the second transparent side wall; The second transparent side wall is located on a side of the first transparent side wall close to the metal component, and the third transparent side wall is located on a side of the second transparent side wall close to the metal component; or the first transparent side wall, the second transparent side wall and the third transparent side wall are coplanar.

6. The array substrate according to claim 2, characterized in that: The first transparent conductive sublayer, the second transparent conductive sublayer and the third transparent conductive sublayer include at least one of an indium tin oxide layer and an indium zinc oxide layer, and the first metal layer includes at least one of a copper layer, a molybdenum layer, an aluminum layer, a titanium layer, a copper alloy layer, a titanium alloy layer, a molybdenum alloy layer and an aluminum alloy layer.

7. The array substrate according to claim 1, characterized in that: The first transparent conductive sublayer includes a first transparent bottom surface, the first transparent bottom surface extends from the substrate to contact the metal side wall of the metal component, and the first transparent bottom surface is a surface of the first transparent conductive sublayer close to the substrate; The first transparent conductive sublayer also includes a fourth transparent side wall, which is connected to the first transparent bottom surface and is arranged adjacent to the metal side wall, at least a portion of the fourth transparent side wall is coplanar with at least a portion of the metal top surface, and the second transparent conductive sublayer extends from the surface of the first transparent conductive sublayer away from the substrate to the fourth transparent side wall and the metal top surface.

8. The array substrate according to any one of claims 1 to 7, characterized in that: The metal member includes a drain electrode, and the transparent conductive member includes a pixel electrode.

9. The array substrate according to claim 8, characterized in that: The first metal layer further includes a source electrode spaced apart from the drain electrode, and the array substrate further includes: A second metal layer, disposed between the first metal layer and the substrate, and comprising a gate; a gate insulating layer, disposed between the second metal layer and the first metal layer, and covering the second metal layer and the substrate; an active layer, disposed between the first metal layer and the gate insulating layer, at least a portion of the source electrode and at least a portion of the drain electrode being disposed on the active layer, and the pixel electrode extending from the gate insulating layer through a side wall of the active layer and a side wall of the drain electrode to a surface of the drain electrode away from the substrate; a passivation layer, covering the first metal layer, the first transparent conductive layer, the active layer and the gate insulating layer; and The second transparent conductive layer is arranged on a side of the passivation layer away from the substrate.

10. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 9.

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