Power chip packaging structure and printed circuit board assembly

Abstract

The utility model relates to the technical field of chip packaging, in particular to a power chip packaging structure and a printed circuit board assembly, the power chip packaging structure of the utility model comprises a power chip and an insulating frame, the power chip is embedded in the insulating frame, and the other side of the insulating frame is provided with a first dielectric layer for insulation. Good insulation is formed through the insulation frame and the first dielectric layer, meanwhile, the electrode on the single-electrode side of the power chip is led to the double-electrode side to be connected with the electrode of the power chip packaging structure, a lead does not need to be additionally led to bond the chip, packaging parasitic inductance is reduced, meanwhile, the size of the power chip packaging structure is greatly reduced, and the packaging cost is reduced. Meanwhile, the whole packaging structure is simple, and the process manufacturing difficulty is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of chip packaging, in particular to a power chip packaging structure and a printed circuit board assembly. Background Art

[0002] Power semiconductor devices are a type of electronic components, specially designed to handle high voltage, high current power conversion and control, and are the core components of power electronics technology. They play a vital role in modern electronic systems and are widely used in various fields, including but not limited to industrial control, consumer electronics, new energy (such as solar and wind energy), electric vehicles, traction systems, power management and conversion (such as AC / DC, DC / DC converters), lighting control, and aerospace.

[0003] In the prior art, power devices are packaged in a way that wire bonding is often used to interconnect chips. This packaging method results in a larger volume of the power device and a lower level of integration due to the presence of a lead frame. Utility Model Content

[0004] The embodiment of the utility model provides a power chip packaging structure and a printed circuit board assembly to solve the problem that the power device packaging in the prior art has a large volume and a low integration due to the existence of a lead frame.

[0005] In a first aspect, the utility model provides a power chip packaging structure, comprising: a power chip and an insulating frame, wherein the power chip is embedded in the insulating frame, and a coplanar first electrode, a second electrode, and a third electrode are provided on one side of the insulating frame, wherein the first electrode is electrically connected to the first electrode on the dual-electrode side of the power chip, the second electrode is electrically connected to the second electrode on the dual-electrode side of the power chip, and the third electrode is electrically connected to the third electrode on the single-electrode side of the power chip;

[0006] A first dielectric layer for insulation is arranged on the other side of the insulation frame.

[0007] In one embodiment, a second dielectric layer for fixing is provided between the power chip and the insulating frame.

[0008] In one embodiment, the third electrode on the single electrode side of the power chip is metallically connected to the third electrode of the power chip packaging structure to form a first interconnection structure.

[0009] In one embodiment, a first blind hole is opened on one side of the second dielectric layer, and metal is filled in the first blind hole to form a third electrode on the single electrode side of the power chip. The third electrode is connected to the third electrode of the power chip packaging structure through a metal column to form a second interconnection structure.

[0010] In one embodiment, a second blind hole is further opened on one side of the second dielectric layer, and the metal filled in the second blind hole and the metal filled in the first blind hole together form a third electrode on the single electrode side of the power chip, and the third electrode is connected to the third electrode of the power chip packaging structure through the metal column to form a third interconnection structure.

[0011] In one embodiment, the metal column passes through the insulating frame.

[0012] In a second aspect, this embodiment provides a printed circuit board assembly, the printed circuit board assembly comprising a printed circuit board, in which the power chip packaging structure as described in the first aspect and its improvement is embedded.

[0013] In one embodiment, the power chip packaging structure further includes: an insulating dielectric plate with a metal layer on its surface, and the insulating dielectric plate with a metal layer on its surface is fixedly welded to the non-electrode side of the power chip packaging structure.

[0014] In one embodiment, the printed circuit board assembly further includes: a heat sink, which is mounted on the back side of the power chip packaging structure.

[0015] In one embodiment, a third dielectric layer for fixing is provided between the printed circuit board and the power chip packaging structure.

[0016] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0017] The power chip packaging structure of the utility model comprises a power chip and an insulating frame, wherein the power chip is embedded in the insulating frame, and a first dielectric layer for insulation is arranged on the other side of the insulating frame, and good insulation is formed by utilizing the insulating frame and the first dielectric layer, and at the same time, the electrode on the single electrode side of the power chip is led to the double electrode side and connected with the third electrode of the power chip packaging structure, and no additional lead wire is required to bond the chip, thereby reducing the parasitic inductance of the package and greatly reducing the volume of the power chip packaging structure. At the same time, the entire packaging structure is simple, and the difficulty of process manufacturing is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the description of the embodiments of the utility model will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1This is a schematic diagram of the module structure of a power chip packaging structure provided by an embodiment of the utility model;

[0020] Figure 2 This is a schematic diagram of the module structure of a power chip packaging structure provided by an embodiment of the utility model;

[0021] Figure 3-1 It is a schematic flow chart of a method for preparing a power chip packaging structure provided by an embodiment of the utility model;

[0022] Figure 3-2 This is a schematic diagram of a structural preparation process of a power chip packaging structure provided by an embodiment of the utility model;

[0023] Figure 4 This is a schematic diagram of the module structure of a power chip packaging structure provided by an embodiment of the utility model;

[0024] Figure 5 This is a schematic diagram of the module structure of a power chip packaging structure provided by an embodiment of the utility model;

[0025] Figure 6-1 It is a schematic flow chart of a method for preparing a power chip packaging structure provided by an embodiment of the utility model;

[0026] Figure 6-2 This is a schematic diagram of a structural preparation process of a power chip packaging structure provided by an embodiment of the utility model;

[0027] Figure 7 This is a schematic diagram of a module structure of a printed circuit board assembly provided by an embodiment of the utility model;

[0028] Figure 8-1 It is a schematic flow chart of a method for preparing a printed circuit board assembly provided in one embodiment of the utility model;

[0029] Figure 8-2 This is a schematic diagram of a structural preparation process of a printed circuit board assembly provided by an embodiment of the utility model;

[0030] Figure 9-1 It is a schematic flow chart of a method for preparing a printed circuit board assembly provided in one embodiment of the utility model;

[0031] Figure 9-2 This is a schematic diagram of a structural preparation process of a printed circuit board assembly provided by an embodiment of the utility model;

[0032] Among them, 1. power chip, 2. insulating frame, 3. power chip packaging structure electrode, 4. first dielectric layer, 5. second dielectric layer, 6. first interconnection structure, 7. high temperature tape, 8. circuit layer area, 9. power device area, 10. third dielectric, 11. power chip body, 12 power chip electrode, 13. heat sink, 14. insulating dielectric plate, 21. second interconnection structure, 31. third interconnection structure. DETAILED DESCRIPTION

[0033] In order to make the technical problems, technical solutions and beneficial effects solved by the utility model more clear, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model and are not used to limit the utility model.

[0034] In the description of the present invention, it should be understood that the terms "longitudinal", "radial", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0035] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0036] In order to thoroughly understand the present invention, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0038] In one embodiment, if Figure 1 As shown, a schematic diagram of a module structure of a power chip 1 packaging structure is provided, comprising: a power chip 1 and an insulating frame 2, wherein the power chip 1 is embedded in the insulating frame 2, and a coplanar first electrode, a second electrode and a third electrode are provided on one side of the insulating frame 2, wherein the first electrode is electrically connected to the first electrode on the dual-electrode side of the power chip 1, the second electrode is electrically connected to the second electrode on the dual-electrode side of the power chip 1, and the third electrode is electrically connected to the third electrode on the single-electrode side of the power chip 1;

[0039] A first dielectric layer 4 for insulation is disposed on the other side of the insulation frame 2 .

[0040] It is understandable that the power chip 1 can be any type of power chip. The power chip 1 can be an insulated gate bipolar transistor (IGBT), or a metal-oxide-semiconductor field-effect transistor (MOSFET). The electrode on the single electrode side of the power chip 1 can be a collector or an emitter, or the electrode on the single electrode side of the power chip 1 can be a drain or a source.

[0041] Specifically, the insulating frame 2 can be a frame formed by any insulating material. The insulating material of the insulating frame 2 can be an organic resin. Further, the organic resin can be FR4 or BT for preparing circuit boards. The insulating material of the insulating frame 2 can also be ceramic. Further, the ceramic can be alumina, aluminum nitride, silicon nitride, diamond or zirconium oxide toughened alumina. The insulating material of the insulating frame 2 can also be glass, and the size of the insulating frame 2 can be set according to actual application conditions.

[0042] The first electrode and the second electrode on the dual-electrode side of the power chip 1 can directly serve as the first electrode and the second electrode of the power chip packaging structure, or can be respectively connected to the first electrode and the second electrode of the power chip packaging structure through a conductive structure. It can be understood that the first electrode, the second electrode and the third electrode of the power chip packaging structure are insulated from each other. Preferably, an insulating medium is used to insulate the electrodes of the power chip packaging structure from each other, and a blind hole is set in the insulating medium. The electrodes of the power chip 1 are connected to the respective electrodes of the power chip packaging structure through the conductive material of the blind hole in the insulating medium. Furthermore, a blind hole can be set in the insulating frame 2, and the electrodes of the power chip 1 are connected to the respective electrodes of the power chip packaging structure through the conductive material of the blind hole in the insulating medium and the conductive material of the blind hole in the insulating frame 2.

[0043] It is understandable that the dielectric material of the first dielectric layer 4 is an insulating material. Preferably, the dielectric material of the first dielectric layer 4 is a resin material. Further, the resin material can be an epoxy molding compound, or the resin material can be an Ajinomoto laminated film. The first dielectric layer 4 of the power chip packaging structure should cover the conductive structure on the other side of the power chip packaging structure so that the power chip packaging structure has good insulation.

[0044] The power chip packaging structure of the present embodiment includes a power chip 1 and an insulating frame 2. The power chip 1 is embedded in the insulating frame 2, and a first dielectric layer 4 for insulation is provided on the other side of the insulating frame 2. The insulating frame 2 and the first dielectric layer 4 are used to form good insulation. At the same time, the electrode on the single-electrode side of the power chip 1 is led to the double-electrode side and connected to the electrode of the power chip packaging structure. There is no need to introduce additional leads to bond the chip, which reduces the parasitic inductance of the package and greatly reduces the volume of the power chip packaging structure. At the same time, the entire packaging structure is simple, which reduces the difficulty of process manufacturing.

[0045] like Figure 2 As shown, a schematic diagram of a module structure of a power chip packaging structure is provided.

[0046] In one embodiment, if Figure 2 As shown in the above Figure 1 On the basis of the power chip packaging structure shown, a second dielectric layer 5 for fixing is arranged between the power chip 1 and the insulating frame 2 .

[0047] The medium in the second dielectric layer 5 and the medium in the first dielectric layer 4 can be the same medium, or the medium in the second dielectric layer 5 and the medium in the first dielectric layer 4 can be different mediums. Preferably, the medium in the second dielectric layer 5 and the medium in the first dielectric layer 4 are the same medium. The second dielectric layer 5 is mainly used to fix the power chip 1. The second dielectric layer 5 is also used to insulate the electrodes of the power chip packaging structure from each other. A blind hole can be prepared in the second dielectric layer 5, and the electrode on the single electrode side of the power chip 1 is connected to the third electrode of the power chip packaging structure through the metal material in the blind hole of the second dielectric layer 5. A through hole can also be prepared in the insulating frame 2, and the electrode on the single electrode side of the power chip 1 is connected to the third electrode of the power chip packaging structure through the metal material in the through hole of the insulating frame 2. Further, the electrode on the single electrode side of the power chip 1 is connected to the third electrode of the power chip packaging structure through the metal material in the blind hole of the second dielectric layer 5 and the metal material in the through hole of the insulating frame 2, respectively.

[0048] The power chip packaging structure of this embodiment is provided with a second dielectric layer 5 to fix the power chip 1, and also uses the second dielectric layer 5 to insulate the electrodes of the power chip packaging structure, which can improve the stability and reliability of the power chip packaging structure.

[0049] In one embodiment, if Figure 2 As shown, based on the above embodiment, the third electrode on the single electrode side of the power chip 1 is metallically connected to the third electrode of the power chip packaging structure to form a first interconnection structure 6.

[0050] Specifically, the electrode on the single electrode side of the power chip 1 is connected to the third electrode of the power chip packaging structure through the metal in the dielectric layer and the metal column in the insulating frame 2. Preferably, the metal is copper.

[0051] The power chip packaging structure of this embodiment realizes metallic connection between the third electrode of the power chip 1 and the third electrode of the power chip packaging structure, ensuring that electronic signals can be efficiently transmitted between the power chip 1 and the third electrode of the power chip packaging structure. Moreover, metal has good thermal conductivity, and the metal connection can better dissipate heat for the power chip 1.

[0052] The preparation method of the utility model is further described as follows: Figure 3-1 As shown, a schematic diagram of a process for preparing a power chip packaging structure is provided, such as Figure 3-2 As shown, a schematic diagram of a structure preparation process of a power chip packaging structure is provided, and the preparation method of the power chip packaging structure includes the following steps:

[0053] Step S101: Provide an insulating board. Preferably, the insulating material of the insulating board is organic resin.

[0054] Step S102: one or more through holes are opened in the first preset area of ​​the insulating plate to obtain an insulating plate with through holes opened. The through holes can be opened by mechanical processing, laser processing or etching processing.

[0055] Step S103: metallizing the through hole, preferably, filling the through hole by copper electroplating.

[0056] Step S104: a first through groove is formed in the second preset area of ​​the insulating plate. The shape and size of the first through groove can be set according to actual application conditions. Preferably, the shape of the first through groove is square.

[0057] Step S105: Affix a high temperature tape to one side surface of the insulating board with the first through groove formed therein.

[0058] Step S106: Mount one side of one or more power chips 1 on the high-temperature tape in the first through groove. Preferably, mount the single-electrode side of the power chip 1 on the high-temperature tape in the first through groove.

[0059] Step S107: Pressing a second dielectric on the dual-electrode side of the power chip 1, the upper surface of the high-temperature tape and the other side surface of the insulating plate to form a second dielectric layer 5.

[0060] Step S108: removing the high temperature tape.

[0061] Step S109: preparing a blind hole in a third preset area of ​​the second dielectric layer 5, where the third preset area should at least include three electrode positions on the same plane of the power chip packaging structure.

[0062] Step S1010: Perform hole-filling electroplating and patterning on the power chip packaging structure. It is understandable that the circuit pattern on the electrode side of the power chip packaging structure should at least include the pads corresponding to the electrodes of the power chip packaging structure. Furthermore, the circuit pattern that can assist assembly and manufacturing can be prepared on the electrode side of the power chip packaging structure; the circuit pattern on the non-electrode side of the power chip packaging structure should at least include a metal layer covering the power chip packaging structure, preferably, the metal layer is a copper layer.

[0063] Step S1011: Pressing a first dielectric on the single-electrode side surface of the power chip 1 to form a first dielectric layer 4.

[0064] In one embodiment, if Figure 4 As shown, a schematic diagram of a module structure of a power chip packaging structure is provided. Figure 2On the basis of the power chip packaging structure shown, a first blind hole is opened on one side of the second dielectric layer 5, and metal is filled in the first blind hole to form a third electrode on the single electrode side of the power chip 1. The third electrode is connected to the third electrode of the power chip packaging structure through a metal column to form a second interconnection structure 21.

[0065] It is understandable that the first blind hole should be located on the single electrode side of the power chip 1, and the electrode on the single electrode side of the power chip 1 is connected to the third electrode of the power chip packaging structure through the metal of the blind hole and the metal column in the insulating frame 2. Preferably, the metal is copper.

[0066] The power chip packaging structure of this embodiment uses a blind hole to achieve electrical connection between the third electrode of the power chip 1 and the third electrode of the power chip packaging structure. The blind hole helps to achieve a higher wiring density in a limited space and can reduce signal cross interference.

[0067] like Figure 5 As shown, a schematic diagram of a module structure of a power chip packaging structure is provided.

[0068] In one embodiment, if Figure 5 As shown in the above Figure 4 On the basis of the power chip packaging structure shown, a second blind hole is also opened on one side of the second dielectric layer 5. The metal filled in the second blind hole and the metal filled in the first blind hole together form a third electrode on the single electrode side of the power chip 1. The third electrode is connected to the third electrode of the power chip packaging structure through the metal column to form a third interconnection structure 31.

[0069] The power chip packaging structure of this embodiment utilizes multiple blind holes to realize the electrical connection between the third electrode of the power chip 1 and the third electrode of the power chip packaging structure. While ensuring the signal transmission between the third electrode of the power chip 1 and the third electrode of the power chip packaging structure, the multiple blind holes can enable the power chip 1 to dissipate heat better.

[0070] In one embodiment, if Figure 5 As shown, based on the above embodiment, the metal column passes through the insulating frame 2.

[0071] Specifically, through holes are prepared on the insulating frame 2, and connections are made through metal columns in the through holes.

[0072] The power chip packaging structure of this embodiment uses a through hole to achieve electrical connection between the third electrode of the power chip 1 and the third electrode of the power chip packaging structure, which can enhance the fixing strength of the power chip 1, prevent desoldering and breakage due to external force, and improve the overall mechanical stability.

[0073] The preparation method of the utility model is further described as follows: Figure 6-1 As shown, a schematic diagram of a process for preparing a power chip packaging structure is provided, such as Figure 6-2 As shown, a schematic diagram of a structure preparation process of a power chip packaging structure is provided, and the preparation method of the power chip packaging structure includes the following steps:

[0074] Step S201: Provide an insulating board. Preferably, the insulating material of the insulating board is organic resin.

[0075] Step S202: one or more through holes are opened in the first preset area of ​​the insulating plate to obtain an insulating plate with through holes opened. The through holes can be opened by mechanical processing, laser processing or etching processing.

[0076] Step S203: metallizing the through hole, preferably, filling the through hole by copper electroplating.

[0077] Step S204: a first through groove is formed in the second preset area of ​​the insulating plate. The shape and size of the first through groove can be set according to actual application conditions. Preferably, the shape of the first through groove is square.

[0078] Step S205: Affix a high temperature tape to one side surface of the insulating board with the first through groove formed therein.

[0079] Step S206: Mount one side of one or more power chips 1 on the high-temperature tape in the first through groove. Preferably, mount the single-electrode side of the power chip 1 on the high-temperature tape in the first through groove.

[0080] Step S207: Pressing a second dielectric on the dual-electrode side of the power chip 1 , the upper surface of the high-temperature tape and the other side surface of the insulating plate to form a second dielectric layer 5 on the dual-electrode side of the power chip 1 .

[0081] Step S208: removing the high temperature tape.

[0082] Step S209: Laminating the second dielectric on the original tape side of the insulating plate to form a second dielectric layer 5 on the single electrode side of the power chip 1.

[0083] Step S2010: Prepare a blind hole in the third preset area of ​​the second dielectric layer 5 formed on the dual-electrode side of the power chip 1, and prepare a blind hole in the fourth preset area of ​​the second dielectric layer 5 formed on the single-electrode side of the power chip 1. The third preset area should include at least three electrode positions on the same plane of the power chip packaging structure, and the fourth preset area should include at least two blind holes. The first blind hole is used to lead out the third electrode of the power chip 1; the second blind hole is used to electrically connect the led-out third electrode to the third electrode of the power chip packaging structure through the metal layer.

[0084] Step S2011: Perform hole-filling electroplating and patterning on the power chip packaging structure. It is understandable that the circuit pattern on the electrode side of the power chip packaging structure should at least include pads corresponding to each electrode of the power chip packaging structure. Furthermore, the circuit pattern that can assist assembly and manufacturing can be prepared on the electrode side of the power chip packaging structure; the circuit pattern on the non-electrode side of the power chip packaging structure should at least include a metal layer covering the power chip packaging structure, preferably, the metal layer is a copper layer.

[0085] Step S2012: Pressing a first dielectric on the single-electrode side surface of the power chip 1 to form a first dielectric layer 4.

[0086] like Figure 7 As shown, a schematic diagram of the module structure of a printed circuit board assembly is provided.

[0087] In one embodiment, if Figure 7 As shown, the printed circuit board assembly includes a printed circuit board, in which the power chip packaging structure mentioned in any of the above embodiments is embedded.

[0088] A through groove or recess is provided in the printed circuit board to bury the power chip packaging structure in the printed circuit board. It is understandable that the electrodes of the power chip packaging structure should be provided on the surface of the printed circuit board, or be led out to the surface of the printed circuit board through lines, so as to facilitate electrical connection between the power chip packaging structure and the circuit of the printed circuit board.

[0089] The power chip packaging structure can be first embedded in the printed circuit board, and then the circuit pattern can be prepared on the surface of the printed circuit board according to the actual application situation; or the relevant circuit pattern can be prepared on the printed circuit board according to the actual application situation, and then the power chip packaging structure can be embedded in the printed circuit board. Furthermore, a dielectric layer can be filled between the power chip packaging structure and the printed circuit board to fix the power chip packaging structure.

[0090] In this embodiment, the power chip packaging structure with coplanar power electrodes is buried in the printed circuit board, which avoids unstable connection between the power chip packaging structure and the circuit board, improves the stability and long-term reliability of the overall circuit, and significantly saves the surface space of the circuit board, so that more components can be integrated on a smaller board surface, greatly improving the integration.

[0091] In one embodiment, if Figure 7 As shown, based on the above embodiment, the power chip packaging structure further includes: an insulating dielectric plate 14 with a metal layer on its surface, and the insulating dielectric plate 14 with a metal layer on its surface is fixedly welded on the non-electrode side of the power chip packaging structure.

[0092] It is understandable that metal layers are provided on both sides of the insulating dielectric plate 14. Preferably, the metal layers are copper layers. The insulating dielectric plate 14 with metal layers is a double-sided copper-clad ceramic plate, which is welded by mechanical welding or manual welding.

[0093] It is understandable that a welding layer may be provided between the double-sided copper-clad ceramic board and the non-electrode side of the power chip packaging structure, and the double-sided copper-clad ceramic board may be welded by using the welding layer. It is also possible that the first dielectric layer 4 is not prepared when preparing the power chip packaging structure, and the double-sided copper-clad ceramic board is welded on the metal layer on the non-electrode side of the power chip packaging structure. The insulating dielectric plate 14 of the double-sided copper-clad ceramic board may be any ceramic material, and the ceramic material may be silicon nitride, the ceramic material may also be aluminum nitride ceramic, the ceramic material may also be aluminum oxide, the ceramic material may also be zirconium oxide toughened aluminum oxide, the ceramic material may also be silicon carbide ceramic, and the ceramic material may also be diamond. Preferably, the ceramic material is silicon nitride or aluminum nitride ceramic, and the thickness of the copper layer is greater than the thickness of the ceramic material. It is understandable that the total thickness of the power chip packaging structure, the welding layer and the double-sided copper-clad ceramic board should be less than the thickness of the printed circuit board.

[0094] As another embodiment, a metal layer may be provided outside the first dielectric layer 4 , and the metal layer may be used to dissipate heat and fix the heat sink at the same time.

[0095] In the printed circuit board assembly of this embodiment, a double-sided copper-clad ceramic board is welded on the non-electrode side of the power chip packaging structure. The double-sided copper-clad ceramic board can not only dissipate heat for the power chip packaging structure, but also fix the heat sink.

[0096] In one embodiment, if Figure 7 As shown, based on the above embodiment, the printed circuit board assembly further includes: a heat sink 13, which is installed on the back side of the power chip packaging structure.

[0097] The back side of the power chip packaging structure refers to the non-electrode side of the power chip packaging structure. It can be understood that the radiator 13 in this embodiment is any kind of heat dissipation device, which can be a water-cooled radiator 13 or an air-cooled radiator 13. Preferably, the radiator 13 in this embodiment is a water-cooled radiator 13. The size of the radiator 13 can be selected according to the specific application situation. The size of the radiator 13 can be larger than the size of the power chip packaging structure, the size of the radiator 13 can also be smaller than the size of the power chip packaging structure, and the size of the radiator 13 can also be equal to the size of the power chip packaging structure.

[0098] In the printed circuit board assembly of this embodiment, a heat sink 13 is disposed on the back of the power chip packaging structure to further ensure that the power chip packaging structure can fully dissipate heat.

[0099] In one embodiment, if Figure 7 As shown, based on the above embodiment, a third dielectric layer for fixing is provided between the printed circuit board and the power chip packaging structure.

[0100] The second medium in the second medium layer 5 is used to fix the power chip 1 and isolate the electrodes of the power chip 1. The third medium layer is used to fix the power chip packaging structure. The third medium can be the same as the second medium or different from the second medium. Preferably, the second medium has lower water absorption and stronger insulation and anti-aging capabilities.

[0101] In the printed circuit board assembly of this embodiment, a third dielectric layer is provided to fix the power chip packaging structure, thereby ensuring the stability and reliability of the printed circuit board assembly.

[0102] The preparation method of the utility model is further described as follows: Figure 8-1 As shown, a schematic diagram of a process for preparing a power chip embedded printed circuit board assembly is provided, such as Figure 8-2 As shown, a schematic diagram of the structural preparation process of a power chip embedded printed circuit board assembly is provided, and the preparation method of the power chip packaging structure includes the following steps:

[0103] Step S301: providing a printed circuit board with a circuit pattern prepared in a circuit layer area.

[0104] Step S302: A second through groove is opened in the power device area of ​​the printed circuit board. The shape and size of the second through groove can be set according to actual application conditions. Preferably, the shape of the second through groove is rectangular. The number of second through grooves can be set according to actual application conditions. Only one power chip packaging structure can be embedded in the printed circuit board, or multiple power chip packaging structures can be embedded in the printed circuit board.

[0105] Step S303: affixing a high temperature tape to one side surface of the printed circuit board provided with the second through groove.

[0106] Step S304: Mount the non-electrode side of one or more power chip packaging structures on the high-temperature tape of the second through groove. Preferably, a metal layer is provided on the non-electrode side of the power chip packaging structure.

[0107] Step S305: On the electrode side of the power chip packaging structure, a third dielectric is pressed onto the upper surface of the temperature-resistant adhesive layer and the other side surface of the printed circuit board to form a third dielectric layer.

[0108] Step S306: removing the high temperature tape.

[0109] Step S307: preparing a blind hole in the fifth preset area of ​​the dielectric layer on the electrode side of the power chip packaging structure, the blind hole is used to lead out the electrode of the power chip packaging structure and the pad on the printed circuit board that needs to be electrically connected to the outside world.

[0110] Step S308: The printed circuit board assembly is subjected to hole-filling electroplating and circuit pattern production. Preferably, the metal layer on the non-electrode side of the power chip packaging structure can be thickened to enhance the heat transfer efficiency between the power chip packaging structure and the heat sink 13.

[0111] Step S309: Install a heat sink 13 on the metal layer of the power chip packaging structure.

[0112] The preparation method of the utility model is further described as follows: Figure 9-1 As shown, a schematic diagram of a process for preparing a power chip 1 embedded printed circuit board assembly is provided, such as Figure 9-2 As shown, a schematic diagram of the structural preparation process of a power chip 1 embedded printed circuit board assembly is provided. The preparation method of the power chip packaging structure includes the following steps:

[0113] Step S301: providing a printed circuit board with a circuit pattern prepared in a circuit layer area.

[0114] Step S302: A second through groove is opened in the power device area of ​​the printed circuit board. The shape and size of the second through groove can be set according to actual application conditions. Preferably, the shape of the second through groove is rectangular. The number of second through grooves can be set according to actual application conditions. Only one power chip packaging structure can be embedded in the printed circuit board, or multiple power chip packaging structures can be embedded in the printed circuit board.

[0115] Step S303: affixing a high temperature tape to one side surface of the printed circuit board provided with the second through groove.

[0116] Step S304: Mount the non-electrode side of one or more power chip packaging structures on the high-temperature tape of the second through groove. Preferably, the non-electrode side of the power chip packaging structure is provided with a double-sided copper-clad ceramic plate.

[0117] Step S305: On the electrode side of the power chip packaging structure, a third dielectric is pressed onto the upper surface of the temperature-resistant adhesive layer and the other side surface of the printed circuit board to form a third dielectric layer.

[0118] Step S306: removing the high temperature tape.

[0119] Step S307: preparing a blind hole in the fifth preset area of ​​the dielectric layer on the electrode side of the power chip packaging structure, the blind hole is used to lead out the electrode of the power chip packaging structure and the pad on the printed circuit board that needs to be electrically connected to the outside world.

[0120] Step S308: The printed circuit board assembly is subjected to hole-filling electroplating and circuit pattern production. Preferably, the outer metal layer of the double-sided copper-clad ceramic board on the non-electrode side of the power chip packaging structure can be thickened to enhance the heat transfer efficiency between the power chip packaging structure and the heat sink 13.

[0121] Step S309: Install a heat sink 13 on the outer metal layer of the double-sided copper-clad ceramic board of the power chip packaging structure.

[0122] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.

Claims

1. A power chip packaging structure, characterized in that: include: A power chip and an insulating frame, wherein the power chip is embedded in the insulating frame, and a coplanar first electrode, a second electrode and a third electrode are provided on one side of the insulating frame, wherein the first electrode is electrically connected to the first electrode on the dual-electrode side of the power chip, the second electrode is electrically connected to the second electrode on the dual-electrode side of the power chip, and the third electrode is electrically connected to the third electrode on the single-electrode side of the power chip; A first dielectric layer for insulation is arranged on the other side of the insulation frame.

2. The power chip packaging structure according to claim 1, characterized in that: A second dielectric layer for fixing is arranged between the power chip and the insulating frame.

3. The power chip packaging structure according to claim 2, characterized in that: The third electrode on the single electrode side of the power chip is metallically connected to the third electrode of the power chip packaging structure to form a first interconnection structure.

4. The power chip packaging structure according to claim 3, characterized in that: A first blind hole is opened on one side of the second dielectric layer. The first blind hole is filled with metal to form a third electrode on the single electrode side of the power chip. The third electrode is connected to the third electrode of the power chip packaging structure through a metal column to form a second interconnection structure.

5. The power chip packaging structure according to claim 4, characterized in that: A second blind hole is also opened on one side of the second dielectric layer. The metal filled in the second blind hole and the metal filled in the first blind hole together form a third electrode on the single electrode side of the power chip. The third electrode is connected to the third electrode of the power chip packaging structure through the metal column to form a third interconnection structure.

6. The power chip packaging structure according to claim 5, characterized in that: The metal column passes through the insulating frame.

7. A printed circuit board assembly, characterized in that: include: A printed circuit board, wherein the power chip packaging structure as claimed in any one of claims 1 to 6 is embedded in the printed circuit board.

8. The printed circuit board assembly according to claim 7, characterized in that: The power chip packaging structure further includes: an insulating dielectric plate with a metal layer on its surface, and the insulating dielectric plate with a metal layer on its surface is fixedly welded to the non-electrode side of the power chip packaging structure.

9. The printed circuit board assembly according to claim 8, characterized in that The printed circuit board assembly also includes: a heat sink, which is installed on the back side of the power chip packaging structure.

10. The printed circuit board assembly according to claim 9, characterized in that A third dielectric layer for fixing is arranged between the printed circuit board and the power chip packaging structure.

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