Anti-static wafer

Abstract

The anti-static wafer comprises a plurality of chips, each chip in the plurality of chips comprises a plurality of pins, scribing channels, an anti-static lead, the scribing channels are located between two adjacent chips in the plurality of chips, the anti-static lead is configured to be connected with two or more pins in the plurality of pins, and the scribing channels are arranged between the scribing channels and the anti-static lead. At least one part of the anti-static lead is located outside the scribing channel in the extending direction of the scribing channel. According to the anti-static wafer, the yield of chips can be improved in the manufacturing process of the chips.

Description

Technical Field

[0001] The utility model relates to an antistatic wafer. Background Art

[0002] With the rapid development of the mobile communications industry, the application frequency of many electrostatic discharge (ESD) sensitive chips has gradually increased. The design size of the chip is getting smaller and smaller, and the importance of anti-static discharge for product reliability is gradually increasing. At present, the chip layout design is basically arranged independently, and there is no connection method and structural design between chips. However, for ESD-sensitive chips, independent arrangement cannot achieve a good anti-static discharge effect. During the manufacturing process, static electricity is easily accumulated on ESD-sensitive chips, and once static discharge occurs, the chip may be damaged.

[0003] At present, the anti-electrostatic discharge of chips is generally to reduce the introduction of static electricity as much as possible during the process manufacturing process. However, it may not be possible to completely avoid static electricity during the manufacturing process. Therefore, it is necessary to reduce the impact of static electricity as much as possible in the chip layout design. Therefore, a wafer that can avoid static electricity discharge of chips during the manufacturing process is desired. Utility Model Content

[0004] According to at least one embodiment of the present disclosure, an antistatic wafer is provided, characterized in that it includes: a plurality of chips, each chip of the plurality of chips includes a plurality of pins, a scribe line located between two adjacent chips of the plurality of chips, and an antistatic lead, the antistatic lead being configured to connect two or more of the plurality of pins, and at least a portion of the antistatic lead being located outside the scribe line in a direction extending along the scribe line.

[0005] According to at least one embodiment of the wafer disclosed herein, it is characterized in that at least a portion of the antistatic lead is located within the scribe line in a direction extending along the scribe line.

[0006] According to at least one embodiment of the wafer disclosed herein, it is characterized in that at least a portion of the anti-static lead between connected adjacent pins is located within the dicing lane.

[0007] The wafer according to at least one embodiment of the present disclosure is characterized in that at least one pair of antistatic leads is included between two adjacent chips, the at least one pair of antistatic leads extends along the scribe line direction and is located on both sides of the scribe line, and the at least one pair of antistatic leads intersects within the scribe line.

[0008] According to the wafer of at least one embodiment of the present disclosure, it is characterized in that the anti-static lead is also configured to connect all the pins among the plurality of pins.

[0009] According to the wafer of at least one embodiment of the present disclosure, it is characterized in that the anti-static lead is also configured to connect all ground pins among the plurality of pins.

[0010] According to at least one embodiment of the wafer disclosed herein, the anti-static lead is further configured to connect a ground pin and a portion of the input pins among the plurality of pins.

[0011] According to at least one embodiment of the wafer disclosed herein, it is characterized in that the intersection of the at least one pair of antistatic leads in the dicing lane is in an X-shape.

[0012] According to at least one embodiment of the wafer disclosed herein, it is characterized in that the intersecting portion of the at least one pair of antistatic leads in the dicing lane is in an I-shape.

[0013] According to at least one embodiment of the wafer disclosed herein, it is characterized in that the intersecting portion of the at least one pair of antistatic leads in the dicing lane is two tangent semicircles.

[0014] A wafer according to at least one embodiment of the present disclosure is characterized in that the multiple chips include a first chip, the first chip includes a first pin and a second pin adjacent to the first pin, the multiple chips include a second chip adjacent to the first chip, the second chip includes a third pin opposite to the first pin and a fourth pin opposite to the second pin, the first antistatic lead of the at least one pair of antistatic leads is connected between the first pin and the fourth pin, and the second antistatic lead of the at least one pair of antistatic leads is connected between the second pin and the third pin.

[0015] According to at least one embodiment of the wafer disclosed herein, it is characterized in that at least a portion of the at least one pair of antistatic leads along the scribe line direction is located outside the scribe line, and the at least one pair of antistatic leads intersect within the scribe line between connected adjacent pins.

[0016] According to at least one embodiment of the wafer disclosed herein, it is characterized in that a portion of the antistatic lead located within the scribe line is thinner than a portion of the antistatic lead located outside the scribe line.

[0017] According to at least one embodiment of the wafer disclosed herein, it is characterized in that a portion of the antistatic lead located within the scribe line has a higher conductivity than a portion of the antistatic lead located outside the scribe line.

[0018] According to at least one embodiment of the wafer disclosed herein, it is characterized in that a portion of the antistatic lead located within the scribe line has a lower hardness than a portion of the antistatic lead located outside the scribe line.

[0019] According to at least one embodiment of the wafer of the present disclosure, it is characterized in that after a dicing operation is performed on the wafer, any two of the plurality of pins that were previously connected are not connected through the antistatic lead.

[0020] According to at least one embodiment of the wafer disclosed herein, the plurality of chips are surface acoustic wave filters.

[0021] According to at least one embodiment of the wafer disclosed herein, it is characterized in that the antistatic lead is located at a layer in the wafer that is different from the layer where the multiple chips are located.

[0022] The wafer according to at least one embodiment of the present disclosure can improve the yield of the chip during the manufacturing process of the chip. For example, the wafer according to at least one embodiment of the present disclosure can avoid or alleviate the impact of static electricity accumulation or static electricity discharge on ESD-sensitive chips during the manufacturing process of the chip, reduce the damage to the chip caused by static electricity discharge, and thus improve the yield of the chip. In addition, the wafer according to at least one embodiment of the present disclosure can reduce the content of metal present in the dicing lane, significantly reducing the probability of edge collapse of the wafer during the dicing process, thereby improving the yield of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other aspects, features and advantages of the exemplary embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0024] Figure 1 is a schematic diagram of the wafer;

[0025] Figure 2 is a wafer according to at least one embodiment of the present disclosure;

[0026] Figure 3A is a wafer according to at least one embodiment of the present disclosure;

[0027] Figure 3B is a wafer according to at least one embodiment of the present disclosure;

[0028] Figure 3C is a wafer according to at least one embodiment of the present disclosure;

[0029] Figure 3D The present invention relates to a wafer according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] Before proceeding to the following detailed description, it may be advantageous to set forth definitions of certain words and phrases used throughout this disclosure. The terms "include" and "comprising" and their derivatives mean including, but not limited to. The phrase "at least one," when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one item in the list may be required. For example, "at least one of A, B, C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0031] Definitions for other specific words and phrases are provided throughout this disclosure. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.

[0032] The various embodiments of the principles of the present disclosure in this patent application document are described below in conjunction with the accompanying drawings for illustration only, and should not be interpreted as limiting the scope of the present disclosure in any way. It will be appreciated by those skilled in the art that the principles of the present disclosure can be implemented in any appropriately arranged system or device. In some cases, the actions described in the present disclosure can be performed in different orders, and the desired results can still be achieved. In addition, the process depicted in the accompanying drawings does not necessarily require the specific order shown or the sequential order to achieve the desired results. In a specific embodiment, multitasking and parallel processing may be advantageous.

[0033] The text and drawings are provided as examples only to help understand the present disclosure. They should not be interpreted as limiting the scope of the claims attached to the present disclosure in any way. Throughout the drawings, the same reference numerals generally indicate the same elements. Although certain embodiments and examples have been provided, based on the contents of the present disclosure, it is clear to those skilled in the art that the embodiments and examples shown may be changed without departing from the scope of the present disclosure.

[0034] Figure 1 is a schematic diagram of a wafer.

[0035] like Figure 1 As shown, the wafer 100 includes chips 1100, 1200, 1300, and 1400. One or more of the chips 1100, 1200, 1300, and 1400 may be ESD-sensitive chips, such as surface acoustic wave filters. Figure 1 Although the number of chips included in the wafer 100 is shown as four, the wafer 100 may include more or less chips.

[0036] Chip 1100 may include a plurality of pins and functional units. For example, chip 1100 may include input pin 1110, ground pin 1120, and functional unit 1130. Functional unit 1130 may be a resonator or a defective microstrip structure (Defected Microstrip Structure) DMS unit. Input pin 1110 and ground pin 1120 may be connected to functional unit 1130 to implement the function of chip 1100 when the chip is used. Those skilled in the art should understand that chip 1100 may include more or fewer pins and more or fewer functional units. Components identified with the same pattern in chip 1100, chip 1200, chip 1300, and chip 1400 represent components of the same type (e.g., pins or functional units of the same type).

[0037] During the manufacturing process of chip 1100, chip 1200, chip 1300, and chip 1400, electrostatic charges may be generated on the pins of different chips. For example, a negative charge may be generated on a ground pin of chip 1100, a positive charge may be generated on another ground pin of chip 1100, and a negative charge may be generated on an input pin of chip 1200. When the electrostatic charges accumulated on each pin reach a certain amount, electrostatic discharge may occur. For example, electrostatic discharge may occur between a ground pin of chip 1100 and another ground pin, and electrostatic discharge may occur between a ground pin of chip 1100 and an input pin of chip 1200, but the present disclosure is not limited thereto. Such electrostatic discharge may cause ESD-sensitive chips in chip 1100, chip 1200, chip 1300, and chip 1400 to be damaged, resulting in a reduction in the yield of the chip.

[0038] At present, the introduction of electrostatic charge can be reduced as much as possible during the chip manufacturing process. For example, operators can use anti-static wristbands to reduce the introduction of electrostatic charge. In addition, operators can use ion blowers to reduce the electrostatic charge generated during the manufacturing process. However, during such a manufacturing process, electrostatic charge may still exist on the chip, leading to electrostatic discharge.

[0039] Figure 2 The present invention relates to a wafer according to at least one embodiment of the present disclosure.

[0040] like Figure 2 As shown, the wafer 200 may include a plurality of chips including a chip 2100. For simplicity, only the chip 2100 is shown. The chip 2100 may be an ESD-sensitive chip, such as a surface acoustic wave filter. Figure 2 Only the chip 2100 is shown in the wafer 200 , but the wafer 200 may include more chips.

[0041] The chip 2100 may include a plurality of pins and functional units. For example, the chip 2100 may include an input pin 2110, a ground pin 2120, and a functional unit 2130. The functional unit 2130 may be a resonator or a DMS unit. The input pin 2110 and the ground pin 2120 may be connected to the functional unit 2130 to implement the functions of the chip 2100 when the chip is used. It should be understood by those skilled in the art that the chip 2100 may include more or fewer pins and more or fewer functional units. The components identified with the same pattern in the chip 2100 represent the same type of components (e.g., the same type of pins or functional units).

[0042] like Figure 2 As shown, two or more of the plurality of pins of chip 2100 can be connected by antistatic lead 2200. When two or more of the plurality of pins of chip 2100 are connected, the generated electrostatic charge can be distributed to the plurality of pins. In this way, it is not easy to generate electrostatic charge accumulation and / or reduce the adverse effects of electrostatic charge accumulation between the various pins of chip 2100.

[0043] like Figure 2 As shown, the chip 2100 includes a dicing lane 2300 (shown in a shaded area) around it. The dicing lane 2300 may be located between multiple chips (eg, Figure 1 The wafer 200 is cut along the dicing lane 2300 to separate the chip 2100 into individual chips.

[0044] After the scribing operation is performed, the antistatic leads connected between different pins can be cut off to avoid short circuits caused by incorrect connections between different pins of the chip. For example, a portion of the antistatic leads 2200 can be located within the scribing lane 2300 (e.g., the protrusion 2210) to cut off the antistatic leads 2200 between different pins through the scribing operation. For example, at least a portion of the antistatic leads 2200 between all adjacent pins that are connected can be located within the scribing lane, so that after the scribing operation is performed, any two adjacent pins that were previously connected are not connected through the antistatic leads 2200. Although Figure 2In the figure, the portion of the anti-static lead 2200 located in the scribe lane 2300 is shown as a triangular protrusion, but those skilled in the art will appreciate that other shapes (e.g., rectangular protrusions, semicircular protrusions, etc.) may be applied to the present disclosure. However, the protrusion 2210 is not necessary, that is, the anti-static lead 2200 may be entirely located outside the scribe lane 2300. For example, the anti-static lead 2200 may not include the protrusion 2210, and other methods may be used to cut off the anti-static lead between different pins.

[0045] The scribing operation can be performed by blades, lasers, and other methods. If there is metal in the scribing lane, it may have an adverse effect on the scribing operation. For example, the metal in the scribing lane may cause edge collapse during the scribing operation of the wafer. Although the laser scribing operation is less affected by the metal in the scribing lane, the cost of the laser scribing operation is high, which is not conducive to reducing the cost of chip manufacturing.

[0046] The antistatic lead 2200 may have at least a portion located outside the scribing path in the direction extending along the scribing path (e.g., the portion 2220 of the antistatic lead 2200 in the direction extending along the scribing path). In this way, the content of metal in the scribing path can be reduced. By reducing the content of metal in the scribing path, the scribing operation can be performed in a relatively low-cost manner while reducing the possibility of edge collapse. In addition, the material of the antistatic lead 2200 can be a metal or alloy material commonly used in semiconductor processes, thereby further reducing costs.

[0047] Figure 2 Wafers in the chip manufacturing process can improve the chip yield rate. For example, Figure 2 Wafers in the chip manufacturing process can avoid or alleviate the impact of static electricity accumulation or static electricity discharge on ESD-sensitive chips, reduce the damage of static electricity discharge to chips, and thus improve the chip yield. Figure 2 The wafer in the dicing lane can reduce the metal content in the dicing lane, significantly reducing the probability of wafer edge collapse during the dicing process, thereby improving the chip yield.

[0048] Figure 3A The present invention relates to a wafer according to at least one embodiment of the present disclosure.

[0049] like Figure 3A As shown, the wafer 300 includes chips 3100, 3200, 3300, and 3400. One or more of the chips 3100, 3200, 3300, and 3400 may be ESD-sensitive chips, such as surface acoustic wave filters. Figure 3A Although the number of chips included in the wafer 300 is shown as four, the wafer 300 may include more or less chips.

[0050] Chip 3100 may include multiple pins and functional units. For example, chip 3100 may include input pin 3110, ground pin 3120, and functional unit 3130. Functional unit 3130 may be a resonator or a DMS unit. Input pin 3110 and ground pin 3120 may be connected to functional unit 3130 to implement the function of chip 3100 when the chip is used. It should be understood by those skilled in the art that chip 3100 may include more or fewer pins and more or fewer functional units. Components identified with the same pattern in chip 3100, chip 3200, chip 3300, and chip 3400 represent components of the same type (e.g., pins or functional units of the same type).

[0051] like Figure 3A As shown, at least one pair of antistatic leads (e.g., antistatic lead 3510 and antistatic lead 3520) may be included between two adjacent chips (e.g., chip 3100 and chip 3200) included in wafer 300. At least one pair of antistatic leads extends along the direction of the scribe line and is located on both sides of the scribe line. At least one pair of antistatic leads (e.g., antistatic lead 3510 and antistatic lead 3520) may intersect within the scribe line (e.g., antistatic lead intersection 3530). Although Figure 3A The antistatic lead is shown as a straight line, but it should be understood by those skilled in the art that the antistatic lead can be one or more of a straight line, an oblique line, and a curve. The antistatic lead can be made using the same layer as the layer of the chip included in the wafer 300, or a different layer can be used to make the antistatic lead. For example, when the antistatic lead is made using a layer different from the layer in which a plurality of chips are located in the wafer, the film thickness can be increased to achieve a better antistatic effect and electrostatic shielding effect, while also being able to block the intrusion of the film flow of the coating during the packaging process. In this way, more or fewer chips can be connected with antistatic leads.

[0052] In the subsequent manufacturing process, the wafer 300 may be diced in the dicing lanes to separate the multiple chips. For example, the wafer may be cut along the dicing lanes to separate the chip 3100 , the chip 3200 , the chip 3300 , and the chip 3400 into separate chips.

[0053] After performing the scribing operation, the antistatic lead wires connected between different pins can be cut off to avoid the short circuit caused by the wrong connection between the different pins of the chip. For example, the part where at least one pair of antistatic leads intersects between two adjacent chips can be located in the scribing road (for example, antistatic lead wire intersection 3530), to cut off the antistatic leads between different pins by scribing operation. For example, the antistatic leads can be located in the scribing road at least a portion between all adjacent pins connected, so that after performing the scribing operation, any two adjacent pins previously connected are not connected by the antistatic leads. That is to say, at least one pair of antistatic leads between two adjacent chips are located outside the scribing road at least a portion along the scribing road direction, and the at least one pair of antistatic leads intersect in the scribing road between all adjacent pins connected.

[0054] In one embodiment, the antistatic lead can connect all pins in a plurality of pins of chip 3100, chip 3200, chip 3300, and chip 3400. In this way, when electrostatic charge is generated in chip 3100, chip 3200, chip 3300, and chip 3400, the electrostatic charge generated can be distributed in the pins of a plurality of chips. Thereby, it is not easy to generate electrostatic charge accumulation and / or reduce the adverse effects brought by electrostatic charge accumulation between each pin of each chip. For example, by connecting all pins of all chips, the ability to release static electricity can be further enhanced for wafers that do not need probe test (Probe), and the structural unit between the input pin and the ground pin is prevented from accumulating electrostatic charge.

[0055] In one embodiment, the anti-static lead can connect all ground pins in the plurality of pins of chip 3100, chip 3200, chip 3300, and chip 3400. For example, by connecting all ground pins in the plurality of pins, the anti-static effect can be ensured while not affecting the wafer from being tested by probes.

[0056] In one embodiment, the anti-static lead may connect a portion of the ground pins and the input pins among the plurality of pins of the chip 3100 , the chip 3200 , the chip 3300 , and the chip 3400 .

[0057] At least one pair of antistatic lead intersection portions between two adjacent chips (for example, antistatic lead intersection portion 3530) can be arranged in an X shape. By arranging the antistatic lead intersection portion 3530 in an X shape, the metal content in the scribe lane can be greatly reduced, and at the same time, after the wafer is separated by scribe, the connection of the corresponding pins is disconnected. In addition, after the scribe operation, the ground lead located within the scribe lane is removed, and the previously connected corresponding pins are disconnected without short circuit; the ground lead located outside the scribe lane is retained, and the retained ground lead can continue to be connected to the corresponding pin to produce an electromagnetic shielding effect, thereby avoiding mutual inductance between the internal structure of the chip and the structure outside the chip.

[0058] although Figure 3A In the embodiment, the intersection of at least one pair of anti-static leads between two adjacent chips is shown as an X-shape, but those skilled in the art will appreciate that other shapes may also be applied to the present disclosure. FIG. 3B to FIG. 3D Describes the intersection of other shapes.

[0059] Figure 3B The present invention relates to a wafer according to at least one embodiment of the present disclosure. Figure 3B Zhongyu Figure 3A The same parts will not be described again. Figure 3B As shown, at least one pair of antistatic lead intersections between two adjacent chips can be located in the scribing lane (for example, antistatic lead intersection 3530), and the antistatic lead intersection 3530 can be an I-shaped. By arranging the antistatic lead intersection 3530 in an I-shaped shape, the metal content in the scribing lane can be reduced, and at the same time, the antistatic lead intersection 3530 is kept at a 90-degree right angle to avoid the generation of sharp-angle graphics. Since right-angle graphics are relatively easier to achieve when the photolithography process approaches the resolution limit, the antistatic lead intersection 3530 keeps a 90-degree right angle, which can reduce the requirements for the process capability of the photolithography. In addition, after the scribing operation, the ground lead located in the scribing lane is removed, and the corresponding pins previously connected are disconnected without short circuit; the ground lead located outside the scribing lane is retained, and the retained ground lead can continue to be connected to the corresponding pin to produce an electromagnetic shielding effect, thereby avoiding mutual inductance between the internal structure of the chip and the structure outside the chip.

[0060] Figure 3C The present invention relates to a wafer according to at least one embodiment of the present disclosure. Figure 3C Zhongyu Figure 3A The same parts will not be described again. Figure 3CAs shown, the wafer 300 includes a chip 3100, a chip 3200, a chip 3300, and a chip 3400. The chip 3100 may include a first pin located at the upper right corner of the chip 3100 and a second pin adjacent to the first pin and located at the lower right corner of the chip 3100. The chip 3200 adjacent to the chip 3100 includes a third pin relative to the first pin and a fourth pin relative to the second pin. The third pin may be located at the upper left corner of the chip 3200, and the fourth pin may be located at the lower right corner of the chip 3200. The first antistatic lead in at least one pair of antistatic leads between two adjacent chips (e.g., chip 3100 and chip 3200) may be connected between the first pin and the fourth pin, and the second antistatic lead in the at least one pair of antistatic leads may be connected between the second pin and the third pin. By setting at least one pair of antistatic leads between two adjacent chips in this way, the requirements for the manufacturing process can be reduced, thereby reducing the manufacturing cost. In this way, while reducing the metal content in the scribe lane, the connection between the corresponding pins is more direct, the parasitic inductance in the anti-static lead is smaller, and the electrostatic discharge effect is better. In addition, after the scribe operation, the ground lead located within the scribe lane is removed, and the previously connected corresponding pins are disconnected without short circuit; the ground lead located outside the scribe lane is retained, and the retained ground lead can continue to be connected to the corresponding pin to produce an electromagnetic shielding effect, thereby avoiding mutual inductance between the internal structure of the chip and the structure outside the chip.

[0061] Figure 3D The present invention relates to a wafer according to at least one embodiment of the present disclosure. Figure 3D Zhongyu Figure 3A The same parts will not be described again. Figure 3D As shown, the portion where at least one pair of antistatic leads intersects between two adjacent chips can be located within the scribing path (e.g., the antistatic lead intersection portion 3530), and the antistatic lead intersection portion 3530 can be two tangent semicircles. By arranging the antistatic lead intersection portion 3530 as two tangent semicircles, the angle at which the scribing knife intersects with the antistatic lead can be increased when the scribing knife cuts in, so that it is less likely to produce chip edge collapse at the intersection, further improving the manufacturing yield. In addition, after the scribing operation, the ground lead located within the scribing path is removed, and the corresponding pins previously connected are disconnected without short circuit; the ground lead located outside the scribing path is retained, and the retained ground lead can continue to be connected to the corresponding pin to produce an electromagnetic shielding effect, thereby avoiding mutual inductance between the internal structure of the chip and the structure outside the chip.

[0062] Return to reference Figure 3A, the scribing operation can be performed by blades, lasers, and other methods. If there is metal in the scribing lane, it may have an adverse effect on the scribing operation. For example, the metal in the scribing lane may cause edge collapse during the scribing operation of the wafer. Although the laser scribing operation is less affected by the metal in the scribing lane, the cost of the laser scribing operation is high, which is not conducive to reducing the cost of chip manufacturing.

[0063] Since at least a portion of at least one pair of antistatic leads between two adjacent chips is located outside the scribing path along the scribing path, the metal content in the scribing path can be reduced. By reducing the metal content in the scribing path, the scribing operation can be performed in a low-cost manner while reducing the possibility of edge collapse.

[0064] In one embodiment, the portion of the antistatic lead located within the scribing lane can be thinner than the portion of the antistatic lead located outside the scribing lane. For example, the portion of the antistatic lead located within the scribing lane can be made thinner, and additionally or alternatively, the portion of the antistatic lead located outside the scribing lane can be made thicker. In this way, the metal content in the scribing lane can be reduced while maintaining or reducing the resistance of the antistatic lead.

[0065] In one embodiment, the portion of the antistatic lead located within the scribing path has a higher conductivity than the portion of the antistatic lead located outside the scribing path. For example, the portion of the antistatic lead located within the scribing path can be made of a conductive material with a higher conductivity. In this way, the portion of the antistatic lead located within the scribing path can be made thinner to reduce the metal content in the scribing path while maintaining or reducing the resistance of the antistatic lead. This can have a technical advantage in terms of cost when the conductive material with a higher conductivity is more expensive.

[0066] In one embodiment, the portion of the antistatic lead located within the scribing path may have a lower hardness than the portion of the antistatic lead located outside the scribing path. For example, the portion of the antistatic lead located within the scribing path may be made of a conductive material with a lower hardness. In this way, the hardness of the portion of the antistatic lead located within the scribing path is reduced, thereby reducing the probability of edge collapse.

[0067] The above-mentioned embodiments of the present disclosure are only for easy description and help comprehensive understanding of the present disclosure, and are not intended to limit the scope of the present disclosure. Therefore, it should be understood that, in addition to the above-mentioned embodiments disclosed herein, all modifications and changes or forms of modifications and changes derived from the technical concept of the present disclosure fall within the scope of the present disclosure.

Claims

1. An anti-static wafer, characterized in that: include: a plurality of chips, each of the plurality of chips comprising a plurality of pins, The dicing lane is located between two adjacent chips in a plurality of chips. an anti-static lead configured to connect two or more of the plurality of pins, At least a portion of the antistatic lead is located outside the scribe line in a direction extending along the scribe line.

2. The wafer according to claim 1, characterized in that At least a portion of the antistatic lead is located within the dicing street in a direction extending along the dicing street.

3. The wafer according to claim 2, characterized in that At least a portion of the anti-static lead between connected adjacent pins is located within the dicing lane.

4. The wafer according to claim 1, characterized in that At least one pair of anti-static leads is provided between two adjacent chips, the at least one pair of anti-static leads extends along the direction of the dicing path and is located on both sides of the dicing path, and, The at least one pair of anti-static leads intersects within the scribe line.

5. The wafer according to claim 1, characterized in that The anti-static lead is also configured to connect all of the plurality of pins.

6. The wafer according to claim 1, characterized in that The anti-static lead is also configured to connect all ground pins among the plurality of pins.

7. The wafer according to claim 1, characterized in that The anti-static lead is further configured to connect a ground pin and a portion of the input pins among the plurality of pins.

8. The wafer according to claim 4, characterized in that: The intersection of the at least one pair of antistatic leads in the scribe line is in an X shape.

9. The wafer according to claim 4, characterized in that: The intersection of the at least one pair of antistatic leads in the scribe line is in an I-shape.

10. The wafer according to claim 4, characterized in that The intersecting parts of the at least one pair of antistatic leads in the dicing lane are two tangent semicircles.

11. The wafer according to claim 4, characterized in that The plurality of chips include a first chip, the first chip includes a first pin and a second pin adjacent to the first pin, The plurality of chips include a second chip adjacent to the first chip, the second chip including a third pin opposite to the first pin and a fourth pin opposite to the second pin, The first antistatic lead of the at least one pair of antistatic leads is connected between the first pin and the fourth pin, and the second antistatic lead of the at least one pair of antistatic leads is connected between the second pin and the third pin.

12. The wafer according to any one of claims 8 to 11, characterized in that: At least a portion of the at least one pair of anti-static leads along the direction of the scribe line is located outside the scribe line, and the at least one pair of anti-static leads intersects within the scribe line between adjacent connected pins.

13. The wafer according to claim 1, characterized in that A portion of the anti-static lead located within the scribe line is thinner than a portion of the anti-static lead located outside the scribe line.

14. The wafer according to claim 1, characterized in that The portion of the anti-static lead located within the scribe line has a higher conductivity than the portion of the anti-static lead located outside the scribe line.

15. The wafer according to claim 1, characterized in that The portion of the anti-static lead located within the scribe line has a lower hardness than the portion of the anti-static lead located outside the scribe line.

16. The wafer according to claim 1, characterized in that After the wafer is diced, any two of the plurality of pins are not connected by the anti-static wire.

17. The wafer according to claim 1, characterized in that The plurality of chips are surface acoustic wave filters.

18. The wafer according to claim 1, characterized in that The anti-static lead is located at a layer in the wafer that is different from a layer where the plurality of chips are located.

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