Array substrate, display panel and display device

Abstract

The embodiment of the utility model provides an array substrate, a display panel and a display device, relates to the technical field of display, and can release static electricity on a signal line. The array substrate comprises a substrate, a plurality of pixel circuits, a first conductive layer and a second conductive layer. The plurality of pixel circuits are arranged on the substrate, and the plurality of pixel circuits are arranged in a plurality of rows and a plurality of columns. The first conductive layer comprises a plurality of conductive patterns, the plurality of conductive patterns and the plurality of pixel circuits are spaced, and each conductive pattern comprises at least two contact parts which are arranged at intervals. The second conductive layer is arranged on the side, away from the substrate, of the first conductive layer. The second conductive layer comprises a plurality of first signal lines, and the first signal lines are arranged at intervals in the first direction and extend in the second direction; one first signal line is electrically connected with at least one conductive pattern, and the first signal line is connected with at least two contact parts of the conductive pattern. The array substrate is used for preparing a display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) display panels have gradually become one of the mainstream products in the display field due to their excellent properties such as self-luminescence, no need for backlight, high contrast, thin thickness, wide viewing angle, fast response speed, can be used for flexible panels, wide operating temperature range, simple structure and process. OLED display panels can be widely used in terminal products such as smart phones, tablets, TVs and wearable devices (such as watches).

[0003] The OLED display panel includes an array substrate and a light-emitting device disposed on the array substrate. The array substrate includes a plurality of signal lines, which are used to transmit corresponding control signals to the array substrate to drive the display panel to display images. How to avoid static electricity accumulation on the signal line is a technical problem that needs to be solved in the display panel. Utility Model Content

[0004] An object of the embodiments of the present disclosure is to provide an array substrate, a display panel and a display device, which are used to release static electricity on a signal line and improve the reliability of the display panel.

[0005] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0006] On the one hand, an array substrate is provided. The array substrate includes a substrate, a plurality of pixel circuits, a first conductive layer and a second conductive layer. The plurality of pixel circuits are arranged on the substrate, and the plurality of pixel circuits are arranged in a plurality of rows and a plurality of columns. The first conductive layer includes a plurality of conductive patterns, the plurality of conductive patterns are spaced apart from the plurality of pixel circuits, and the pixel circuits include at least two contact portions spaced apart. The second conductive layer is arranged on a side of the first conductive layer away from the substrate. The second conductive layer includes a plurality of first signal lines, the plurality of first signal lines are spaced apart along a first direction, and all extend along a second direction; one of the first signal lines is electrically connected to at least one conductive pattern, and the first signal line is connected to at least two contact portions of the conductive pattern. The first direction is the row direction in which the plurality of pixel circuits are arranged, and the second direction is the column direction in which the plurality of pixel circuits are arranged.

[0007] In the array substrate provided by the embodiment of the present disclosure, the conductive pattern and the plurality of pixel circuits are spaced apart, which means that the conductive pattern is not directly connected to the pixel circuit, or the conductive pattern is not used to transmit signals to the pixel circuit. The first signal line located on the second conductive layer is electrically connected to at least one conductive pattern located on the first conductive layer, and at the connection position between the first signal line and the conductive pattern, the first signal line protrudes toward the side close to the substrate to form a protrusion. In the case of static electricity on the first signal line, the static electricity will accumulate on the protrusion, corner or other protruding sharp corner position of the first signal line, that is, the static electricity will be transmitted to the connection position between the first signal line and the conductive pattern, and transmitted to the conductive pattern. The conductive pattern includes at least two contact portions arranged at intervals, and the first signal line is connected to at least two contact portions of the conductive pattern, that is, the first signal line includes two positions connected to the contact portion, so that the first signal line can form two protrusions at the position where it is connected to the conductive pattern, which is more conducive to the transmission of static electricity to the conductive pattern. After the static electricity is transmitted to the conductive pattern, tip discharge can occur at the end or edge of the conductive pattern, thereby releasing the static electricity into the insulating layer in contact with the conductive pattern. The static electricity has a small charge, and the insulating layer can absorb and release a small amount of static electricity, thereby releasing the static electricity on the first signal line, thereby avoiding reliability issues such as breakdown of the first signal line due to accumulation of static electricity on the first signal line.

[0008] In some embodiments, the first conductive layer further comprises a plurality of first connection lines, the plurality of first connection lines are arranged at intervals along the second direction, and all extend along the first direction. The second conductive layer further comprises a plurality of data lines, one data line is electrically connected to a column of pixel circuits; the plurality of data lines comprises a plurality of first data lines and a plurality of second data lines, the plurality of first data lines are respectively located on both sides of the plurality of second data lines; one first data line is connected to one first connection line. The plurality of first signal lines comprises a plurality of fan-out lines, one fan-out line is electrically connected to one first connection line. The plurality of conductive patterns comprises a plurality of first conductive patterns, the fan-out line is electrically connected to at least one first conductive pattern.

[0009] In some embodiments, the fan-out line includes a plurality of fan-out sub-lines spaced apart along the second direction, and two ends of two adjacent fan-out sub-lines close to each other are electrically connected to the same first conductive pattern.

[0010] In some embodiments, the first conductive pattern includes an extension portion and two contact portions, the extension portion extends along the second direction, the two contact portions are respectively connected to two ends of the extension portion along the second direction, and the size of the contact portion along the first direction is larger than the size of the extension portion along the first direction. An opening is provided between two adjacent fan-out sub-lines, and the two ends of the two adjacent fan-out sub-lines close to each other are respectively electrically connected to the two contact portions of the same first conductive pattern.

[0011] In some embodiments, the fan-out line is continuous along the second direction; the first conductive pattern includes a plurality of contact portions and at least one extension portion alternately connected along the second direction, the extension portion extends along the second direction, and the size of the contact portion along the first direction is greater than the size of the extension portion along the first direction. The fan-out line is electrically connected to the plurality of contact portions of the first conductive pattern.

[0012] In some embodiments, the plurality of first conductive patterns are arranged in a plurality of columns along the first direction, and each column includes a plurality of first conductive patterns arranged along the second direction. A fan-out line is electrically connected to the plurality of first conductive patterns in one column.

[0013] In some embodiments, along the second direction, the plurality of first conductive patterns are evenly arranged, and the arrangement density of the pixel circuits is an integer multiple of the arrangement density of the first conductive patterns.

[0014] In some embodiments, the array substrate includes a display area and a peripheral area surrounding the display area, and the plurality of pixel circuits are arranged in the display area. The array substrate also includes a first power bus, which is located in the peripheral area and is configured to be electrically connected to the cathode of the light-emitting device. The plurality of first signal lines also include a plurality of first power signal lines, and along the second direction, at least one end of the plurality of first power signal lines is electrically connected to the first power bus. The plurality of conductive patterns also include a plurality of second conductive patterns, and one first power signal line is electrically connected to at least one second conductive pattern.

[0015] In some embodiments, along the second direction, one first power signal line is electrically connected to a plurality of second conductive patterns, and the plurality of second conductive patterns are evenly arranged.

[0016] In some embodiments, the plurality of conductive patterns include a plurality of first conductive patterns; the plurality of first conductive patterns have the same structure as the plurality of second conductive patterns, and the plurality of first conductive patterns have the same arrangement density as the plurality of second conductive patterns.

[0017] In another aspect, a display device is provided, comprising a plurality of light emitting devices and an array substrate as described in any one of the above embodiments, wherein the plurality of light emitting devices are arranged on the array substrate, and one light emitting device is connected to one pixel circuit of the array substrate.

[0018] In another aspect, a display device is provided, wherein the display device comprises the above-mentioned display panel.

[0019] The above-mentioned display panel and display device have the same structure and beneficial technical effects as the array substrate provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0021] Figure 1 is a schematic diagram of a display device according to some embodiments;

[0022] Figure 2 is a driving architecture diagram of a display device according to some further embodiments;

[0023] Figure 3 is a cross-sectional structural diagram of a display panel according to some embodiments;

[0024] Figure 4 is a top view of a first conductive layer and a second conductive layer according to some embodiments;

[0025] Figure 5 for Figure 4 A partial enlarged view of the middle B area;

[0026] Figure 6 For along Figure 5 A cross-sectional view along the middle section line A1-A1;

[0027] Figure 7 is a partial structural diagram of an array substrate according to some embodiments;

[0028] Figure 8 is a top view of a first conductive layer and a second conductive layer according to some embodiments;

[0029] Fig. 9 for Figure 8 A partial enlarged view of the middle C area;

[0030] Fig.10 For along Fig. 9 A cross-sectional view along the middle section line A2-A2;

[0031] Fig.11 is a connection structure diagram of a first signal line and a conductive pattern according to some embodiments;

[0032] Fig.12FIG. 4 is a top view of the structure of an array substrate when the second conductive layer is not included according to some embodiments. DETAILED DESCRIPTION

[0033] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0034] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0035] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0036] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0037] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0038] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0039] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0040] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0041] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0042] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0043] See also Figure 1 The embodiment of the present disclosure provides a display device 1000, which is a product having an image display function. Exemplarily, the display device 1000 may be any device that displays either moving (e.g., video) or fixed (e.g., still image) and either text or image.

[0044] For example, the display device 1000 may be a television, a laptop computer, a tablet computer, a personal digital assistant (PDA), a mobile phone (cell phone), a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a display of a camera view (e.g., a display of a rear-view camera in a vehicle), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a vehicle display, a flight display, or any other product or component having a display function. For example, Figure 1 As shown, the display device 1000 may be a mobile phone.

[0045] From the perspective of the light-emitting type of the display device 1000, the display device 1000 may be an organic light-emitting diode display device, a quantum dot electroluminescent display device (Quantum Dot Light Emitting Diodes; referred to as: QLED) or a miniature light-emitting diode (Mini / Micro Light Emitting Display; referred to as: MLED), etc. From the perspective of the form of the display device 1000, the display device 1000 may be a flat display device, a curved display device or a foldable display device, etc. From the perspective of the shape of the display device 1000, the display device 1000 may be rectangular or circular, etc. The embodiments of the present disclosure do not specifically limit this. The following is an example of a rectangular and planar organic light-emitting diode display device to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited to this, and any other display device may also be considered as long as the same technical idea is applied.

[0046] See also Figure 2 In some embodiments, the display device 1000 includes a display panel 1100 and a driving circuit board 1200. The driving circuit board 1200 may include, for example, a timing controller (TCON), a power management chip DC / DC, and an adjustable resistor divider circuit (generating Vcom) and other driving circuits. The driving circuit board 1200 may also include other circuit structures, which are not listed here one by one. The driving circuit board 1200 is electrically connected to the display panel 1100, and is used to transmit a control signal to the display panel 1100, thereby driving the display panel 1100 to realize image display. In addition, the display device 1000 may also include a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording, fingerprint recognition or face recognition, which are not specifically limited here.

[0047] Continue reading Figure 2 The display panel 1100 has a display area AA and a peripheral area BB, and the peripheral area BB is at least located on one side of the display area AA. Exemplarily, the peripheral area BB is arranged around the display area AA.

[0048] The display area AA is an area on the display panel 1100 for displaying images. The display area AA is provided with a plurality of sub-pixels P. The sub-pixel P is the smallest light-emitting unit on the display panel 1100, and the sub-pixel P is used to display images. The peripheral area BB can be used to set a gate driver on array (GOA) and control signal lines (such as clock signal lines, power supply voltage signal lines, etc.), etc. Of course, the functions of the peripheral area BB are not limited thereto, and the undisclosed embodiments will not be described one by one.

[0049] The multiple sub-pixels P may emit light of different colors. For example, the multiple sub-pixels P include a red light sub-pixel emitting red light, a green light sub-pixel emitting green light, and a blue light sub-pixel emitting blue light.

[0050] A plurality of sub-pixels P are arranged in a plurality of rows and a plurality of columns, each row includes a plurality of sub-pixels P arranged along a first direction X, and a plurality of rows of sub-pixels P are arranged along a second direction Y. Each column includes a plurality of sub-pixels P arranged along a second direction Y, and a plurality of columns of sub-pixels P are arranged along the first direction X. The first direction X and the second direction Y intersect, for example, the first direction X is perpendicular to the second direction Y.

[0051] The sub-pixel P includes a pixel circuit 120 and a light-emitting device 200. The pixel circuit 120 includes a plurality of thin film transistors (TFT) and at least one capacitor Cst. Exemplarily, the pixel circuit 120 may be a "3T1C" circuit, a "7T1C" circuit, or an "8T1C" circuit, etc. The embodiments of the present disclosure are not limited thereto, and any other pixel circuits may also be considered as long as the same technical concept is applied. Among them, "T" refers to TFT, and the number before "T" refers to the number of TFTs; "C" refers to the capacitor Cst, and the number before "C" refers to the number of capacitors Cst.

[0052] See also Figure 3 In some embodiments, the display panel 1100 includes an array substrate 100, a light emitting device 200, and an encapsulation layer 300 which are stacked. Of course, the display panel 1100 may also include a functional stack disposed on the side of the encapsulation layer 300 away from the array substrate 100. The functional stack may be, for example, one or more of a touch function layer, an anti-reflection layer, a hardening layer, and an anti-fingerprint layer, so that the display panel can achieve corresponding functions. The embodiments of the present disclosure do not specifically limit the types and quantities of the above functional stacks.

[0053] The light emitting device 200 includes an anode 201, a light emitting functional layer 202 and a cathode layer 203 arranged in a stacked manner. The cathode layers 203 of the plurality of light emitting devices 200 are interconnected to form a continuous whole layer structure. The display panel 1100 may further include a pixel defining layer PDL, which is arranged on a side of the anode 201 away from the array substrate 100, and the pixel defining layer PDL includes a plurality of openings, and at least a portion of each light emitting functional layer 202 is located in one opening.

[0054] The encapsulation layer 300 is configured to reduce the risk of water vapor and oxygen in the external environment entering the light emitting device 200, thereby increasing the service life of the display panel 1100. The encapsulation layer 300 may be an encapsulation film or an encapsulation substrate. Figure 3 As shown, the encapsulation layer 300 may be an encapsulation film. In this case, the encapsulation layer 300 may include a first inorganic encapsulation layer 301 , an organic encapsulation layer 302 , and a second inorganic encapsulation layer 303 which are sequentially stacked.

[0055] The array substrate 100 includes a substrate 110 and a pixel circuit disposed on the substrate 110. One pixel circuit is connected to one light emitting device and is configured to drive the light emitting device to emit light. The substrate 110 may be a rigid substrate, and the material of the rigid substrate may include glass, for example. Alternatively, the substrate 110 may be a flexible substrate, and the material of the flexible substrate may include any one of polyimide (PI), polycarbonate (PC), or polyvinylchloride (PVC).

[0056] The array substrate 100 may include a plurality of conductive layers, and the plurality of conductive layers are configured to form a plurality of pixel circuits and a plurality of signal lines for driving the pixel circuits. For example, the plurality of conductive layers may include a first semiconductor layer ACT1, a first gate conductive layer GT1, a second gate conductive layer GT2, a second semiconductor layer ACT2, a third gate conductive layer GT3, a first source-drain conductive layer SD1, and a second source-drain conductive layer SD2, which are sequentially arranged in a direction perpendicular to the substrate 110 and away from the substrate 110. Of course, the array substrate may also include other conductive layers, such as a third source-drain conductive layer, which is not specifically limited here, as long as the same technical idea is adopted. Among them, the thin film transistor TFT may include a semiconductor pattern 101 located in the first semiconductor layer ACT1, a gate 102 located in the first gate conductive layer GT1, and a source 103 and a drain 104 located in the first source-drain conductive layer SD1; the storage capacitor Cst may include a first electrode C1 located in the first gate conductive layer GT1 and a second electrode C2 located in the second gate conductive layer GT2.

[0057] The array substrate 100 may further include an insulating layer between adjacent conductive layers, for example, the array substrate 100 may include a first gate insulating layer GI1 between the first semiconductor layer ACT1 and the first gate conductive layer GT1, a second gate insulating layer GI2 between the first gate conductive layer GT1 and the second gate conductive layer GT2, a first interlayer dielectric layer ILD1 between the second gate conductive layer GT2 and the second semiconductor layer ACT2, a second interlayer dielectric layer ILD2 between the second semiconductor layer ACT2 and the third gate conductive layer GT3, a first planar layer PLN1 between the third gate conductive layer GT3 and the first source-drain conductive layer SD1, and a second planar layer PLN2 between the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2. Of course, the array substrate 100 may further include other insulating film layers, which will not be described one by one here.

[0058] See also Figure 4 , Figure 5 and Figure 6 The array substrate 100 provided by the embodiment of the present disclosure includes a first conductive layer 10 and a second conductive layer 20 , and the second conductive layer 20 is arranged on a side of the first conductive layer 10 away from the substrate 110 .

[0059] The first conductive layer 10 includes a plurality of conductive patterns 11, and the plurality of conductive patterns 11 are spaced apart from the plurality of pixel circuits. The spaced apart between the conductive patterns 11 and the plurality of pixel circuits means that the conductive patterns 11 are not directly connected to the pixel circuits 120, or the conductive patterns 11 are not used to transmit signals to the pixel circuits 120. Exemplarily, in the case where the first conductive layer 10 is the first source-drain conductive layer SD1, the pixel circuit may include a source and a drain located on the first source-drain conductive layer SD1, and the conductive patterns are spaced apart from the source and the drain of the pixel circuit; moreover, the conductive patterns 11 are not connected to other conductive layers (such as the first gate conductive layer and the second gate conductive layer, etc.) on the side of the first conductive layer 10 close to the substrate, and the semiconductor layer.

[0060] The second conductive layer 20 includes a plurality of first signal lines 21, which are arranged at intervals along a first direction X and extend along a second direction Y. The first direction X is a row direction in which the plurality of pixel circuits 120 are arranged ( Figure 4 The first direction X is a horizontal direction in the image, the second direction Y is a column direction in which the plurality of pixel circuits 120 are arranged, and the first direction X and the second direction Y intersect. For example, the first direction X is perpendicular to the second direction Y.

[0061] A first signal line 21 is electrically connected to at least one conductive pattern 11. Since the conductive pattern 11 is spaced apart from the pixel circuit, the first signal line 21 does not transmit electrical signals to the pixel circuit through the conductive pattern 11. Based on this, the position of the conductive pattern 11 can be arbitrarily set as long as it does not interfere with other structures of the array substrate (such as contact or electrical coupling).

[0062] In the event of static electricity on the first signal line 21, the static electricity will gather at the protrusions, corners or other protruding sharp corners of the first signal line 21. At the connection position between the first signal line 21 and the conductive pattern 11, a via 105 is formed in the insulating layer between the first conductive layer 10 and the second conductive layer 20, and a portion of the first signal line 21 is located in the via 105, and a protrusion is formed in the via 105. In other words, the first signal line 21 protrudes toward the side close to the substrate 110 to form a protrusion. Based on this, static electricity will gather at the connection position between the first signal line 21 and the conductive pattern 11 (the portion of the first signal line 21 located in the via 105), and be transmitted to the conductive pattern 11, and then be released through the conductive pattern 11, thereby releasing the static electricity on the first signal line 21. Figure 6 As shown, the conductive pattern 11 includes at least two contact portions 1112 disposed at intervals, and the first signal line 21 is connected to at least two contact portions 1112 of the conductive pattern 11, that is, the first signal line 21 includes two positions connected to the contact portions 1112, so that the first signal line 21 can form two protrusions at the position where it is connected to the conductive pattern 11, which is more conducive to the transmission of static electricity to the conductive pattern 11.

[0063] The first conductive layer 10 may be Figure 3 Among the multiple conductive layers included in the array substrate 100 shown, except for the conductive layer farthest from the substrate 110, the second conductive layer 20 can be any conductive layer on the side of the first conductive layer 10 far from the substrate 110. Exemplarily, the second conductive layer 20 can be a film layer for setting signal routing in the array substrate 100, and the first conductive layer 10 is any conductive layer on the side of the second conductive layer 20 close to the substrate 110. For example, the first conductive layer 10 is a conductive layer adjacent to the second conductive layer 20. In this way, the depth of the via hole in the insulating layer between the first conductive layer 10 and the second conductive layer 20 at the connection position between the first signal line 21 and the conductive pattern 11 can be reduced, thereby reducing the difficulty of connecting the first signal line 21 and the conductive pattern 11.

[0064] Exemplarily, the first conductive layer 10 may be the third gate conductive layer GT3, and the second conductive layer 20 may be the first source-drain conductive layer SD1; or, the first conductive layer 10 may be the first source-drain conductive layer SD1, and the second conductive layer 20 may be the second source-drain conductive layer SD2; or, in the case where the array substrate includes the third source-drain conductive layer, the first conductive layer 10 may be the second source-drain conductive layer SD2, and the second conductive layer 20 may be the third source-drain conductive layer. Of course, the first conductive layer 10 and the second conductive layer 20 may not be adjacent conductive layers. Exemplarily, the first conductive layer 10 may be the third gate conductive layer GT3, and the second conductive layer 20 may be the second source-drain conductive layer SD2. It is understandable that the first conductive layer 10 and the second conductive layer 20 may also be other suitable combinations, and the embodiments of the present disclosure are no longer listed one by one, as long as the same technical ideas are adopted.

[0065] In the following embodiments of the present disclosure, the first conductive layer 10 is the first source-drain conductive layer SD1, and the second conductive layer 20 is the second source-drain conductive layer SD2. However, the embodiments of the present application are not limited thereto, as long as the same technical concept is adopted.

[0066] In some embodiments, Figure 4 and Figure 7As shown, the first conductive layer 10 further includes a plurality of first connection lines 12, which are arranged at intervals along the second direction Y and extend along the first direction X. The second conductive layer 20 further includes a plurality of data lines 22, and one data line 22 is electrically connected to a column of pixel circuits. The plurality of data lines 22 include a plurality of first data lines 221 and a plurality of second data lines 222, and the plurality of first data lines 221 are respectively located on both sides of the plurality of second data lines 222 along the first direction X. For example, the plurality of first data lines 221 may be located in the edge area AA2 of the display area AA along the first direction X, and the plurality of second data lines 222 may be located in the center area AA1 of the display area AA along the first direction X. One first data line 221 is connected to one first connection line 12. The plurality of first signal lines 21 included in the second conductive layer 20 include a plurality of fan-out lines 211, and one fan-out line 211 is electrically connected to one first connection line 12. A plurality of fan-out lines 211 may be located in the central area AA1 of the display area AA along the first direction X. Based on this, the first data line 221 located in the edge area AA2 of the display area AA along the first direction X is connected to the central area AA1 of the display area AA along the first direction X through a first connection line 12 and a fan-out line 211 in sequence, and is led out from the edge of the central area AA1 close to the peripheral area. The above-mentioned arrangement of the data line 22 is also called display area fan-out (Fanout In AA; abbreviated as: FIAA) or panel fan-out (Fanout In Panel; abbreviated as: FIP). It is beneficial to reduce the size of the peripheral area along the second direction Y, that is, to reduce the frame width of the array substrate 100, which is beneficial to the display device 1000 to achieve a narrow frame. The fan-out line 211 is arranged in the central area AA1 of the display area AA, and is not used to transmit data signals to the pixel circuit of the central area AA1, that is, the fan-out line 211 is electrically insulated from the pixel circuit located on the side of the fan-out line 211 close to the substrate 110.

[0067] In the related art, the fan-out line 211 is disposed in a single film layer, and is not connected to other structures except the first connection line 12 in the display area AA, resulting in a lack of a path for the generated static electricity to be released; and the fan-out line 211 extends between sub-pixels, and needs to avoid some conductive structures in the pixel circuit, so it has a certain pattern shape, such as corners or protrusions, and static electricity may accumulate at the corners or protrusion edges of the fan-out line 211. For the above reasons, static electricity is easily accumulated in the fan-out line, resulting in low reliability of the array substrate.

[0068] See also Figure 5 and Figure 6In the embodiment of the present disclosure, in order to solve the above problem, the plurality of conductive patterns 11 include a plurality of first conductive patterns 111, a fan-out line 211 is electrically connected to at least one first conductive pattern 111, and a protruding structure protruding toward the side close to the substrate 110 is formed at the position where the fan-out line 211 is connected to the first conductive pattern 111. Based on this, when static electricity appears on the fan-out line 211, the static electricity will be transmitted toward the position where the fan-out line 211 is connected to the first conductive pattern 111, and then transmitted to the first conductive pattern 111, and the static electricity will be released on the first conductive pattern 111, which can improve the reliability of the array substrate.

[0069] In some embodiments, Figure 5 and Figure 6 As shown, the fan-out line 211 includes a plurality of fan-out sub-lines 2111 spaced apart along the second direction Y. In other words, the fan-out line 211 includes a plurality of fan-out sub-lines 2111 that are disconnected from each other, and an opening 2112 is included between two adjacent fan-out sub-lines 2111. The two ends that belong to two adjacent fan-out sub-lines 2111 and are close to each other are electrically connected to the same first conductive pattern 111, that is, the two adjacent fan-out sub-lines 2111 are electrically connected through one first conductive pattern 111. In this way, when the fan-out line 211 is transmitting current, the current can flow through each first conductive pattern 111, ensuring that the static electricity on the fan-out line 211 can be transmitted to the first conductive pattern 111 and released through the first conductive pattern 111.

[0070] See also Figure 5 and Figure 6 The first conductive pattern 111 includes an extension portion 1111 and two contact portions 1112. The extension portion 1111 extends along the second direction Y. The two contact portions 1112 are respectively connected to two ends of the extension portion 1111 along the second direction Y. An opening 2112 is provided between two adjacent fan-out sub-lines 2111. The orthographic projection of the opening 2112 on the substrate 110 overlaps with the orthographic projection of the extension portion 1111 on the substrate 110. Two ends of the two adjacent fan-out sub-lines 2111 and close to each other are respectively electrically connected to the two contact portions 1112 of the same first conductive pattern 111. The size of the contact portion 1112 along the first direction X is greater than the size of the extension portion 1111 along the first direction X. This is beneficial for reducing the alignment accuracy requirement between the fan-out sub-line 2111 and the contact portion 1112, reducing the connection difficulty between the fan-out sub-line 2111 and the contact portion 1112, and increasing the contact area between the fan-out sub-line 2111 and the contact portion 1112, thereby reducing the resistance at the connection between the fan-out sub-line 2111 and the contact portion 1112.

[0071] In other embodiments, see Figure 8 and Fig. 9The fan-out line 211 is continuous along the second direction Y, that is, there is no opening on the fan-out line 211. In this way, the fan-out line 211 is arranged in parallel with the first conductive pattern 111. The first conductive pattern 111 can not only release the static electricity on the fan-out line 211, but also reduce the resistance of the fan-out line 211.

[0072] See also Fig. 9 , Fig.10 and Fig.11 The first conductive pattern 111 includes a plurality of contact portions 1112 and at least one extension portion 1111 alternately connected along the second direction Y. The size of the contact portion 1112 along the first direction X is larger than the size of the extension portion 1111 along the first direction X, which is conducive to reducing the alignment accuracy requirements between the fan-out line 211 and the contact portion 1112, reducing the connection difficulty between the fan-out line 211 and the contact portion 1112, and increasing the contact area between the fan-out line 211 and the contact portion 1112, and reducing the resistance at the connection between the fan-out line 211 and the contact portion 1112. The fan-out line 211 is electrically connected to the plurality of contact portions 1112 of the first conductive pattern 111. In other words, the fan-out line 211 includes a plurality of connection points with the same first conductive pattern 111, which is conducive to increasing the connection reliability and stability between the fan-out line 211 and the same first conductive pattern 111, and is conducive to reducing the resistance of the fan-out line 211.

[0073] Exemplarily, a contact portion 1112 is provided at each end of the first conductive pattern 111 along the second direction Y, and two adjacent contact portions 1112 are connected via an extension portion 1111. Fig.10 As shown, the first conductive pattern 111 includes two contact portions 1112 and an extension portion 1111; or, see Fig.11 The first conductive pattern 111 may also include three contact portions 1112 and two extension portions 1111. The first conductive pattern 111 may also include other numbers of two contact portions 1112 and extension portions 1111, as long as the same technical concept is adopted.

[0074] In some embodiments, Fig.12 As shown, a plurality of first conductive patterns 111 are arranged in a plurality of columns along a first direction X, and each column includes at least one first conductive pattern 111 arranged along a second direction Y. A fan-out line 211 is electrically connected to a plurality of first conductive patterns 111 in a column, so that the density of the first conductive patterns 111 connected to the fan-out line 211 can be increased, and static electricity generated at any position on the fan-out line 211 can be transmitted to the adjacent first conductive pattern 111, further improving the static electricity release effect of the fan-out line 211. It can be understood that in Fig.12In order to distinguish the first conductive pattern 111 from the second conductive pattern 112, different filling patterns are used for the two, but the two are in the same film layer and are prepared together by the same film forming process.

[0075] like Fig.12 As shown, along the second direction Y, a plurality of first conductive patterns 111 are evenly arranged, which is beneficial to improving the uniformity of the first conductive patterns 111 and improving the pattern uniformity of the first conductive layer 10. The arrangement density of the pixel circuits 120 is an integer multiple of the arrangement density of the first conductive patterns 111. In other words, the spacing of the first conductive patterns 111 in the second direction Y (the Pitch of the first conductive patterns 111) is an integer multiple of the spacing of the pixel circuits 120 in the second direction Y (the Pitch of the pixel circuits 120), that is, a first conductive pattern 111 is provided on a side away from the substrate for each integer number of pixel circuits 120, which is beneficial to improving the uniformity of the structure of the array substrate 100 and reducing the risk of the display panel having a blanking problem due to the distribution difference of the first conductive patterns 111.

[0076] For example, Fig.12 As shown, the arrangement density of the pixel circuits 120 is equal to the arrangement density of the first conductive patterns 111. In this way, the pattern uniformity of the first conductive layer 10 can be improved to the maximum extent, and the structural uniformity of the array substrate can be improved to the maximum extent.

[0077] like Figure 7 As shown, the array substrate 100 also includes a first power bus VSS, which is located in the peripheral area BB. The first power bus VSS is configured to be electrically connected to the cathode of the light-emitting device 200, that is, the first power bus VSS is electrically connected to the cathode layer 203. The plurality of first signal lines 21 included in the second conductive layer 20 also include a plurality of first power signal lines 212, and at least one end of the plurality of first power signal lines 212 is electrically connected to the first power bus VSS along the second direction Y. The plurality of first power signal lines 212 are arranged at intervals along the first direction X, and the plurality of first power signal lines 212 extend along the second direction Y, and are electrically connected to the cathode layer. The plurality of first power signal lines 212 can reduce the resistance of the cathode layer, thereby reducing the voltage drop on the cathode layer, and improving the display uniformity of the display area AA. The configuration method using the above-mentioned power auxiliary line 50 is also called SIP (VSS InPanel) technology.

[0078] like Figure 4 and Figure 8As shown, the plurality of conductive patterns 11 further include a plurality of second conductive patterns 112, a first power signal line 212 is electrically connected to at least one second conductive pattern 112, and the first power signal line 212 protrudes toward the side close to the substrate at the position where it is connected to the second conductive pattern 112 to form a protrusion. When static electricity appears on the first power signal line 212, the static electricity will be accumulated at the protruding position of the first power signal line 212, that is, the static electricity will be transmitted to the connection position between the first power signal line 212 and the second conductive pattern 112, and transmitted to the second conductive pattern 112, and a tip discharge will occur at the edge or end of the second conductive pattern 112, thereby releasing the static electricity to the insulating layer in contact with the conductive pattern 112, and the static electricity charge is usually small, and the insulating layer (such as a passivation layer or a planarization layer) can absorb and release a small amount of static electricity, thereby releasing the static electricity on the first power signal line 212. It can be understood that the static electricity charge is small, and although the insulating layer is electrically insulated, it can absorb static electricity and release it.

[0079] Continue reading Figure 4 and Figure 8 Along the second direction Y, a first power signal line 212 is electrically connected to a plurality of second conductive patterns 112, and the plurality of second conductive patterns 112 are evenly arranged. In this way, the density of the second conductive patterns 112 connected to the first power signal line 212 can be increased, and static electricity generated at any position on the first power signal line 212 can be transmitted to the adjacent second conductive patterns 112, thereby further improving the static electricity release effect of the first power signal line 212.

[0080] In some embodiments, Figure 4 and Figure 8 As shown, the plurality of conductive patterns 11 include a plurality of first conductive patterns 111 and a plurality of second conductive patterns 112. The plurality of first conductive patterns 111 have the same structure as the plurality of second conductive patterns 112, that is, the shape of the orthographic projection of the first conductive pattern 111 on the substrate is the same as the shape of the orthographic projection of the second conductive pattern 112 on the substrate, and the size of the orthographic projection of the first conductive pattern 111 on the substrate is equal to the size of the orthographic projection of the second conductive pattern 112 on the substrate. The arrangement density of the plurality of first conductive patterns 111 and the plurality of second conductive patterns 112 is the same. In this way, the structural uniformity of the first conductive layer 10 can be further improved, and the risk of image fading in the display panel can be reduced.

[0081] Of course, in some other embodiments, the first conductive pattern 111 and the second conductive pattern 112 may also be different. For example, when the first conductive pattern 111 includes two contact portions 1112, the second conductive pattern 112 may include one, three, or other number of contact portions; the embodiments of the present disclosure are not limited thereto, as long as the same technical concept is adopted.

[0082] In some embodiments, Figure 4 As shown, in the case where the fan-out line 211 includes a plurality of fan-out sub-lines 2111 spaced apart along the second direction Y, the first power signal line 212 may also include a plurality of power sub-lines 2121 spaced apart along the second direction Y, and the structure of the fan-out sub-line 2111 is the same as that of the power sub-line 2121, that is, the shape and size of the orthographic projection of the fan-out sub-line 2111 on the substrate are respectively the same as the shape and size of the orthographic projection of the power sub-line 2121 on the substrate. Or, as Figure 8 As shown, when the fan-out line 211 is continuous along the second direction, the first power signal line 212 may also be continuous along the second direction Y. This is beneficial to improving the structural uniformity of the second conductive layer 20 .

[0083] It can be understood that, in some other embodiments, when the fan-out line 211 includes a plurality of fan-out sub-lines 2111 spaced apart along the second direction Y, the first power signal line 212 may also be continuous along the second direction Y. Alternatively, when the fan-out line 211 is continuous along the second direction, the first power signal line 212 may also include a plurality of power sub-lines spaced apart along the second direction Y. Of course, the embodiments of the present disclosure are not limited thereto, as long as the same technical concept is adopted.

[0084] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An array substrate, characterized in that: include: substrate; A plurality of pixel circuits are disposed on the substrate, and the plurality of pixel circuits are arranged in a plurality of rows and a plurality of columns; A first conductive layer, comprising a plurality of conductive patterns, wherein the plurality of conductive patterns are spaced apart from the plurality of pixel circuits, and the conductive pattern comprises at least two contact portions spaced apart from each other; The second conductive layer is arranged on a side of the first conductive layer away from the substrate, and includes a plurality of first signal lines, which are arranged at intervals along a first direction and all extend along a second direction, a first signal line is electrically connected to at least one conductive pattern, and the first signal line is connected to at least two contact portions of the conductive pattern; the first direction is a row direction in which the plurality of pixel circuits are arranged, and the second direction is a column direction in which the plurality of pixel circuits are arranged.

2. The array substrate according to claim 1, characterized in that: The first conductive layer further includes a plurality of first connection lines, which are arranged at intervals along the second direction and extend along the first direction; The second conductive layer further comprises a plurality of data lines, one data line being electrically connected to a column of pixel circuits; the plurality of data lines comprising a plurality of first data lines and a plurality of second data lines, the plurality of first data lines being respectively located on both sides of the plurality of second data lines; one first data line being connected to one first connecting line; The plurality of first signal lines include a plurality of fan-out lines, one fan-out line being electrically connected to one first connection line; The plurality of conductive patterns include a plurality of first conductive patterns, and the fan-out line is electrically connected to at least one of the first conductive patterns.

3. The array substrate according to claim 2, characterized in that: The fan-out line includes a plurality of fan-out sub-lines spaced apart along the second direction, and two ends of two adjacent fan-out sub-lines close to each other are electrically connected to the same first conductive pattern.

4. The array substrate according to claim 3, characterized in that: The first conductive pattern includes an extension portion and two contact portions, the extension portion extends along the second direction, the two contact portions are respectively connected to two ends of the extension portion arranged along the second direction, and the size of the contact portion along the first direction is greater than the size of the extension portion along the first direction; There is an opening between two adjacent fan-out sub-lines, and two ends of the two adjacent fan-out sub-lines close to each other are electrically connected to two contact portions of the same first conductive pattern respectively.

5. The array substrate according to claim 2, characterized in that: The fan-out line is continuous along the second direction; The first conductive pattern includes a plurality of contact portions and at least one extension portion alternately connected along the second direction, the extension portion extends along the second direction, and a size of the contact portion along the first direction is greater than a size of the extension portion along the first direction; The fan-out line is electrically connected to a plurality of contact portions of the first conductive pattern.

6. The array substrate according to claim 2, characterized in that: The plurality of first conductive patterns are arranged in a plurality of columns along the first direction, and one column includes at least one first conductive pattern arranged along the second direction; One fan-out line is electrically connected to a plurality of first conductive patterns in one column.

7. The array substrate according to claim 6, characterized in that: Along the second direction, the plurality of first conductive patterns are evenly arranged; and the arrangement density of the pixel circuits is an integer multiple of the arrangement density of the first conductive patterns.

8. The array substrate according to any one of claims 1 to 7, characterized in that: The array substrate comprises a display area and a peripheral area surrounding the display area, and the plurality of pixel circuits are arranged in the display area; The array substrate further comprises a first power bus, which is located in the peripheral area and is configured to be electrically connected to the cathode of the light emitting device; The plurality of first signal lines further include a plurality of first power signal lines, and along the second direction, at least one end of the plurality of first power signal lines is electrically connected to the first power bus; The plurality of conductive patterns further include a plurality of second conductive patterns, and one first power signal line is electrically connected to at least one second conductive pattern.

9. The array substrate according to claim 8, characterized in that: Along the second direction, one first power signal line is electrically connected to a plurality of second conductive patterns, and the plurality of second conductive patterns are evenly arranged.

10. The array substrate according to claim 8, characterized in that: The plurality of conductive patterns further include a plurality of first conductive patterns; the plurality of first conductive patterns have the same structure as the plurality of second conductive patterns, and the plurality of first conductive patterns have the same arrangement density as the plurality of second conductive patterns.

11. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 10; A plurality of light emitting devices are arranged on the array substrate, and one light emitting device is connected to one pixel circuit of the array substrate.

12. A display device, characterized in that: include: The display panel as claimed in claim 11; The driving circuit board is electrically connected to the display panel and is configured to transmit a control signal to the display panel.

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