Package

Abstract

The utility model discloses a packaging piece. The packaging piece comprises a carrier plate; a redistribution layer disposed on the substrate, the redistribution layer including a conductive layer, a dielectric layer disposed on the conductive layer, and a bump disposed on the dielectric layer, the bump connected to the conductive layer via a conductive via penetrating the dielectric layer, the conductive via including an adhesive layer in contact with the dielectric layer, the projection range of the bottom surface of the bump on the dielectric layer is smaller than the coverage range of the bonding layer. According to the technical scheme, higher-strength adhesive force and bonding capacity can be provided at the interface between the bonding layer and the dielectric layer, and the problem of bump inversion or falling off is avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a package. Background Art

[0002] In the process of manufacturing the UBM (under bump metal) under the bump, due to the poor adhesion between the conductive material (such as Cu (copper)) and the dielectric material, a seed layer is not directly formed on the dielectric material. Figure 1A As shown in FIG. 1 , in most cases, an adhesion layer 30 is first formed on the dielectric material 20, and then a start-plating layer 40 is formed on the adhesion layer 30, and then a bump 80 of a conductive material is formed. After the bump structure is completed, an etching process is required to remove the adhesion layer 30 and the start-plating layer 40 outside the bump 80. Figure 1B As shown, the etching process removes the plating layer 40 outside the range of the bump 80; Figure 1C As shown, the etching process removes the adhesion layer 30 outside the area of ​​the bump 80 .

[0003] But if Figure 1C As shown, at the interface between the dielectric material 20 and the bonding layer 30, the etching process will form an undercut 90 at the bottom of the edge portion of the bonding layer 30, which will be magnified in proportion to the size of the micro-bump, affecting the structural strength of the bump, such as Figure 1D As shown, the problem of the bump 80 falling over or falling off occurs in the subsequent process. This problem occurs more and more in the case of a fine pitch less than 5 μm between bumps, for example. Utility Model Content

[0004] In view of the above problems, the present application proposes a package that can at least solve the problem of bump inversion or falling off.

[0005] According to one aspect of the present application, a package is provided, which includes: a carrier; a redistribution layer disposed on the carrier, the redistribution layer including a conductive layer, a dielectric layer disposed on the conductive layer, and a bump disposed on the dielectric layer, the bump being connected to the conductive layer via a conductive via penetrating the dielectric layer, the conductive via including an adhesive layer in contact with the dielectric layer, wherein a projection range of a bottom surface of the bump on the dielectric layer is smaller than a coverage range of the adhesive layer.

[0006] In some embodiments, the conductive via includes a seed layer, the seed layer includes an adhesive layer and a plating layer disposed between the adhesive layer and the bump, and from the perspective of a vertical cross-section perpendicular to the upper surface of the dielectric layer, the width of the plating layer in the horizontal direction is smaller than the width of the adhesive layer in the horizontal direction.

[0007] In some embodiments, the width of the plated layer is smaller than the width of the bump in the horizontal direction.

[0008] In some embodiments, the conductive via includes a seed layer, the seed layer includes an adhesive layer and a plating layer arranged between the adhesive layer and the bump, the dielectric layer has an upper surface, the plating layer and the adhesive layer each have a horizontal extension portion extending between the bump and the upper surface, wherein the thickness of the horizontal extension portion of the plating layer away from its edge is greater than the thickness of the horizontal extension portion of the adhesive layer below the portion.

[0009] In some embodiments, a thickness of an edge portion of the horizontally extending portion of the plating layer is less than a thickness of a horizontally extending portion of the adhesive layer below the edge portion.

[0010] In some embodiments, the side surface of the plated layer is vertically coplanar with the side surface of the bump in a vertical direction perpendicular to the upper surface of the dielectric layer, and the adhesive layer protrudes from the side surface of the plated layer.

[0011] In some embodiments, the plating layer covers the adhesive layer and covers the side surfaces of the adhesive layer.

[0012] In some embodiments, the upper surface of the dielectric layer contacts the adhesive layer, and outside the adhesive layer, the upper surface of the dielectric layer also contacts the plating layer.

[0013] In some embodiments, the adhesive layer has a horizontally extending portion extending horizontally above the upper surface of the dielectric layer, wherein an entirety of the horizontally extending portion is in continuous contact with the upper surface of the dielectric layer.

[0014] In some embodiments, the plating start layer overlapping the bump is conformally disposed on the adhesive layer, and outside the bump, the adhesive layer protrudes beyond the side surface of the plating start layer and the side surface of the bump.

[0015] In the above technical solution, by increasing the coverage of the adhesive layer to exceed the projection range of the bottom surface of the bump, the adhesive layer provides a larger bonding area, and can provide higher strength adhesion and bonding ability at the interface between the adhesive layer and the dielectric layer, avoiding over-etching caused by etching manufacturing, and the problem of bump inversion or falling off, and improving the bonding efficiency between the bump and the dielectric layer. Sufficient strength of metal-to-metal bonding can be provided at the corner of the plating layer adjacent to the adhesive layer, and the bonding efficiency between the adhesive layer and the plating layer is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figures 1A to 1C is a schematic cross-sectional view of a bump structure formed in the prior art.

[0018] Figure 1D It is a schematic cross-sectional view of a bump structure in the prior art when a column inversion problem occurs.

[0019] Figure 2 is a schematic cross-sectional view of a package according to an embodiment of the present application.

[0020] Figure 3A Shows Figure 2 An enlarged schematic diagram of area A1 of the package in FIG.

[0021] Figure 3B Shows Figure 2 Multiple sizes of packages in.

[0022] FIG. 4A to FIG. 4N Schematic cross-sectional views at various stages of forming a package according to an embodiment of the present application.

[0023] Figures 5 to 7 They are schematic cross-sectional views of packages according to other embodiments of the present application. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of this application.

[0025] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. Moreover, the present invention may repeatedly refer to numbers and / or letters in various examples. This repetition is only for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0026] In addition, the embodiments and features in the embodiments of the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0027] According to an embodiment of the present application, a package is provided. Figure 2 is a schematic cross-sectional view of a package 100 according to an embodiment of the present application. Figure 2 As shown, the package 100 may include a redistribution (RDL) layer 110, which may also be referred to as a wiring layer. The package 100 may also include a carrier (not shown), which may be, for example, a substrate or a chip. The redistribution layer 110 may be disposed on the carrier. In some embodiments. The redistribution layer 110 may include a conductive layer 115, a dielectric layer 112 disposed on the conductive layer 115, and a bump 180 disposed on the dielectric layer 112. The bump 180 is connected to the conductive layer 115 by a conductive via 160 that penetrates the dielectric layer 112. The conductive layer 115 may be embedded in the bottom dielectric layer 111.

[0028] In some embodiments, the conductive layer 115 connected to the conductive via 160 may be a pad. In some embodiments, the material of the dielectric layer 112 may be polyimide (PI), epoxy, ABF (Ajinomoto stacked film), polypropylene (PP) and / or acrylic, etc. In some embodiments, the material of the dielectric layer 112 may be an organic photosensitive liquid material and / or an organic non-photosensitive liquid material and / or an organic photosensitive dry film material and / or an organic non-photosensitive dry film material.

[0029] The conductive via 160 may include an adhesive layer 162 in contact with the dielectric layer 112. In some embodiments, the projection range of the bottom surface of the bump 180 on the dielectric layer 112 is smaller than the coverage range of the adhesive layer 162. In other words, the coverage range of the adhesive layer 162 exceeds the projection range of the bottom surface of the bump 180. The bottom surface of the bump 180 refers to the surface of the bump 180 at the level L1, which is flush with the upper surface of the adhesive layer 162.

[0030] In the above technical solution, by increasing the coverage of the adhesive layer 162 to exceed the projection range of the bottom surface of the bump 180, the adhesive layer 162 provides a larger bonding area, and can provide higher strength adhesion and bonding ability at the interface between the adhesive layer 162 and the dielectric layer 112, thereby avoiding over-etching caused by etching manufacturing and the problem of the bump 180 falling over or falling off, thereby improving the bonding efficiency between the bump 180 and the dielectric layer 112.

[0031] Continue to refer Figure 2As shown, the conductive via 160 may include a seed layer, and the seed layer may include the above-mentioned adhesive layer 162 and a plating layer 164 disposed between the adhesive layer 162 and the bump 180. In some embodiments, the adhesive layer 162 is conformally disposed on the dielectric layer 112, and the plating layer 164 overlapping the bump 180 is conformally disposed on the adhesive layer 162. In some embodiments, the material of the adhesive layer 162 is different from the material of the plating layer 164. In some embodiments, the material of the adhesive layer 162 may be, for example, Ti (titanium), and the material of the plating layer 164 may be, for example, Cu. The conductive via 160 may also include a filling portion 166, and the upper surface of the filling portion 166 may be flush with the upper surface of the plating layer 164, that is, flush with the level L1.

[0032] Specifically, the bump 180 may include a conductive column 182 located on the conductive via 160 and the plating layer 164, a barrier layer 184 located on the conductive column 182, a bonding layer 186 located on the barrier layer 184, and a solder ball 188 located on the bonding layer 186. In some embodiments, the conductive column 182 may also be a pad or a micro pad. In some embodiments, the filling portion 166 of the conductive via 160 and the conductive column 182 of the bump 180 are the same conductive material and are formed integrally. In some embodiments, the materials of the conductive column 182 of the bump 180, the filling portion 166 of the conductive via 160, the bonding layer 162 and the plating layer 164 may be respectively made of Cu, gold (Au), silver (Ag), aluminum (Al), palladium (Pd), platinum (Pt), nickel (Ni) and their alloys. In some embodiments, the height of the conductive column 182 can be adjusted to make the bump 180 reach the desired height for bonding.

[0033] The side surfaces of the conductive pillar 182 , the barrier layer 184 , and the bonding layer 186 of the bump 180 may be vertically coplanar in a vertical direction perpendicular to the upper surface 112 u of the dielectric layer 112 , and together form a side surface S1 of the bump 180 . Figure 3A Shows Figure 2 FIG. 1 is an enlarged schematic diagram of a region A1 of the package 100. Figure 2 and Figure 3A As shown, in some embodiments, the side of the plated layer 164 can be vertically coplanar with the side S1 of the bump 180 in a vertical direction perpendicular to the upper surface 112u of the dielectric layer 112. The side of the plated layer 164 is not vertically aligned with the side of the adhesive layer 162. Outside the bump 180, the adhesive layer 162 protrudes from the side of the plated layer 164 and the side S1 of the bump 180. The adhesive layer 162 protrudes from the side of the plated layer 164. Figure 3AAs shown, in some embodiments, a ratio of a distance that the plating layer 164 extends horizontally above the dielectric layer 112 to a distance that the adhesion layer 162 extends horizontally above the dielectric layer 112 is in a range of 0.1:1 to 0.95:1.

[0034] By designing the adhesive layer 162 to protrude from the plated layer 164 , a metal-to-metal bond of sufficient strength can be provided at the corner 164 c of the plated layer 164 adjacent to the adhesive layer 162 (which is the point of maximum bending stress), thereby improving the bonding efficiency between the adhesive layer 162 and the plated layer 164 .

[0035] Figure 3B Shows Figure 2 Multiple sizes of package 100 in. Figure 3B The cross section shown is a vertical cross section perpendicular to the upper surface 112u of the dielectric layer 112, and the vertical cross section is also perpendicular to the bottom surface of the bump 180. Figure 3B From the perspective of the vertical cross section shown, the width AS of the plating layer 164 in the horizontal direction is less than the width BD of the bonding layer 162 in the horizontal direction. In some embodiments, the ratio of the width BD of the plating layer 164 to the width AS of the bonding layer 162 is in the range of 0.1:1 to 0.95:1. In some embodiments, the ratio BD / AS of the width of the bump 180 (equal to BD) to the width AS of the bonding layer 162 is in the range of 0.1:1 to 0.95:1. In some embodiments, the ratio VD / BD of the width AD of the partial conductive via 160 passing through the dielectric layer 112 to the width of the bump 180 (equal to BD) can be in the range of 0.5:1 to 1:1.

[0036] In some embodiments, the width of the bump 180 (equal to BD) may be less than 10 μm. In some embodiments, the pitch P between adjacent bumps 180 may be in the range of 2 μm to 20 μm. In such an embodiment, the width of the bump 180 (equal to BD) may be in the range of 1 μm to 10 μm, and the spacing between adjacent bumps 180 may be in the range of 1 μm to 10 μm. In some embodiments, the pitch P between adjacent bumps 180 may also be less than 5 μm, for example, in the range of 2 μm to 5 μm.

[0037] In some embodiments, the thickness of the adhesive layer 162 may be in the range of tens of nanometers (e.g., 10 nm) to hundreds of nanometers (e.g., 900 nanometers). In some embodiments, the thickness of the plating layer 164 may be in the range of tens of nanometers (e.g., 10 nm) to hundreds of nanometers (e.g., 900 nanometers). In some embodiments, the angle θ between the sidewall of the conductive via 160 passing through the dielectric layer 112 and the vertical direction may be in the range of 5° to 85°. In some embodiments, the thickness of the dielectric layer 112 in the redistribution layer 110 may be in the range of 2 μm to 20 μm. The distance AE by which the adhesive layer 162 protrudes from the plating layer 164 may be in the range of hundreds of nm (e.g., 100 nm) to several μm (e.g., 9 μm).

[0038] The dielectric layer 112 has an upper surface 112u, and the plating layer 164 has a horizontal extension 164a extending between the bump 180 and the upper surface 112u. The adhesive layer 162 has a horizontal extension 162a extending between the bump 180 and the upper surface 112u. In some embodiments, the thickness of the portion of the horizontal extension 164a of the plating layer 164 away from its edge (for example, the portion in area A2) can be greater than the thickness of the horizontal extension 162a of the adhesive layer 162 below the portion (the horizontal extension 162a in area A2). The thickness of the edge portion of the horizontal extension 164a of the plating layer 164 (the horizontal extension 164a in area A3) can be less than the thickness of the horizontal extension 162a of the adhesive layer 162 below the edge portion (the horizontal extension 162a in area A3). This is because the plating layer 164 is formed by an etching process, and the edge portion of the horizontal extension portion 164a of the plating layer 164 (the horizontal extension portion 164a in the area A3) is etched by the etching solution (e.g., isotropic etching), so the thickness of the edge portion of the plating layer 164 is reduced. Since the edge portion of the horizontal extension portion 164a of the plating layer 164 is etched by the etching solution, in some embodiments, the width of the plating layer 164 can be smaller than the width of the bump 180.

[0039] When etching the plating layer 164, the selectivity between the two metal materials of the bonding layer 162 and the plating layer 164 can make the etching process (e.g., its etching solution) have no effect on the bonding layer 162, so the portion of the bonding layer 162 protruding from the bump 180 can be unetched. Therefore, in some embodiments, the thickness of the portion of the bonding layer 162 protruding from the bump 180 is uniform. In some embodiments, the thickness of the horizontal extension portion 162a of the bonding layer 162 is uniform. In some embodiments, the entirety of the horizontal extension portion 162a of the bonding layer 162 can be in continuous contact with the upper surface 112u of the dielectric layer 112.

[0040] Embodiments of the present application also provide a method of forming a package. FIG. 4A to FIG. 4N The package (such as Figure 2 Schematic cross-sectional views of the package 100 at multiple stages. FIG. 4A to FIG. 4N A method of forming the package 100 will be described.

[0041] First reference Figure 4A As shown, a bottom dielectric layer 111 and a conductive layer 115 disposed in the bottom dielectric layer 111 are provided. The conductive layer 115 is embedded in the bottom dielectric layer 111 and exposed by the bottom dielectric layer 111.

[0042] refer to Figure 4B As shown in FIG. 1 , a dielectric layer 112 is covered on the bottom dielectric layer 111 and the conductive layer 115 to form a redistribution layer 110. The dielectric layer 112 can be used as a top dielectric layer. The dielectric layer 112 is subjected to a photolithography process to form a conductive through hole ( Figure 2 The conductive through hole 160) has an opening 411, such as Figure 4C The opening 411 is located on the conductive layer 115 and exposes the conductive layer 115 .

[0043] refer to Figure 4D As shown, a photoresist layer 431 is conformally formed on the upper surface 112 u of the dielectric layer 112 and in the opening 411 , for example, by a lamination process.

[0044] refer to Figure 4E As shown, the photoresist layer 431 is subjected to a photolithography process to remove a portion of the photoresist layer 431 in and around the opening 411. Then, an adhesion layer 162 (e.g., a Ti layer) is deposited on the remaining photoresist layer 431, in the opening 411, and on the upper surface 112u of the dielectric layer 112 around the opening 411, for example, by processes such as PVD (Physical Vapor Deposition), electroplating, chemical plating, printing, or potting.

[0045] Remove the photoresist layer 431 and the adhesive layer 162 on the photoresist layer 431, refer to Figure 4F As shown, the adhesive layer 162 is retained in and around the opening 411. The adhesive layer 162 passes through the opening 411 and contacts the conductive layer 115. Since the coverage of the adhesive layer 162 is formed by the photoresist layer 431 (see Figure 4E ), so no etching process is required to form a pattern of the adhesive layer 162. Since no etching process is required to form a pattern of the adhesive layer 162, the adhesion and bonding ability at the interface between the adhesive layer 162 and the dielectric layer 112 will not be damaged.

[0046] refer to Figure 4GAs shown, a plating layer 164 (eg, a Cu layer) is conformally deposited on the dielectric layer 112 and the adhesion layer 162 by, for example, PVD, electroplating, chemical plating, printing, or potting.

[0047] refer to Figure 4H As shown, for example, by lamination process, the photoresist layer 433 is covered on the plating layer 164, and the photoresist layer 433 fills the opening 411 (see Figure 4G ) of the remaining space.

[0048] refer to Fig. 4I As shown, the photoresist layer 433 is subjected to a photolithography process to form an opening 413. Then, a conductive material 420 is formed in the opening 413 by, for example, PVD, electroplating, chemical plating, printing, or potting. The conductive material 420 forms the above-mentioned filling portion 166 and the conductive column 182.

[0049] refer to Figure 4J As shown, a barrier layer 184 is formed on the conductive material 420 in the opening 413 , for example, by an electroplating process, and a bonding layer 186 is formed on the barrier layer 184 .

[0050] refer to Figure 4K As shown, solder 188' is formed in opening 413 by, for example, electroplating process. In some embodiments, the inner wall of opening 413 is vertical, and the sides of conductive pillar 182, barrier layer 184, bonding layer 186 and solder 188' along the inner wall of 413 are vertically coplanar.

[0051] refer to Figure 4L As shown, remove Figure 4K At this time, the plating layer 164 covers the adhesive layer 162. Then, the plating layer 164 is etched to remove the plating layer 164 that does not overlap with the conductive column 182, forming a Figure 4M When etching the plating layer 164, the selectivity between the two metal materials of the bonding layer 162 and the plating layer 164 can make the etching process (such as etching solution) have no effect on the bonding layer 162, so the portion of the bonding layer 162 protruding from the bump 180 may not be etched.

[0052] like Figure 4M As shown, after etching the plating layer 164, a reflow process 440 is performed to form the solder 188' into a solder ball 188, as shown in FIG. Figure 4N So far, the above reference is formed. Figure 2 The package 100 is described.

[0053] In some embodiments, the package 100 can be formed by panel level (PNL) and wafer level (WL) processes. The use of an overall WL (or PNL) process can be used for a low-cost solution. In the above formation process, a through hole for interconnecting with the conductive layer 115 is first made in the dielectric layer 112 through the PNL (or WL) platform. An adhesive layer 162 is made on the upper surface of the dielectric layer 112 around the through hole by a PVD process. Next, a plating layer 164 is made on the entire PNL (or WL) surface. Secondly, a conductive material 420 is formed by photolithography and electroplating processes. Then, a barrier layer 184, a bonding layer 186, and a solder 188' are made on the plating layer 164. Finally, the plating layer 164 outside the conductive material 420 is chemically etched, and then reflow heated to form a bump 180 (e.g., a micro bump with a fine pitch of less than 5μm).

[0054] Figure 5 FIG. 2 is a schematic cross-sectional view of a package 200 according to another embodiment of the present application. Figure 5 In the illustrated embodiment, the plating start layer 164 covers the adhesive layer 162 and covers the side of the adhesive layer 162. The plating start layer 164 extends on the adhesive layer 162 along the adhesive layer 162 and terminates at the upper surface 112u of the dielectric layer 112. The upper surface 112u of the dielectric layer 112 is in contact with the adhesive layer 162, and outside the adhesive layer 162, the upper surface 112u of the dielectric layer 112 is also in contact with the plating start layer 164. The outermost side of the plating start layer 164 is vertically coplanar with the side of the conductive column 182 of the bump 180 in a vertical direction perpendicular to the upper surface 112u of the dielectric layer 112. By forming the adhesive layer 162 to be completely embedded between the plating start layer 164 and the dielectric layer 112, it is possible to facilitate the realization of a smaller spacing between adjacent bumps 180.

[0055] Figure 6 FIG. 1 is a schematic cross-sectional view of a package 300 according to another embodiment of the present application. Figure 6 In the illustrated embodiment, the bump 180 includes only the solder ball 188. The material of the filling portion 166 of the conductive via 160 and the material of the solder ball 188 may be the same, for example, both are tin. Figure 2 Compared with the embodiment, Figure 6 The illustrated embodiment can reduce costs.

[0056] Figure 7 FIG. 4 is a schematic cross-sectional view of a package 400 according to another embodiment of the present application. Figure 7In the illustrated embodiment, the filling portion 166' of the conductive via 160' is formed by a conductive adhesive 450, and the conductive adhesive 450 includes metal particles 451. The conductive adhesive 450 can extend between two conductive vias 160' above the dielectric layer 112. In some embodiments, the conductive adhesive can be one of ACP (Anisotropic Conductive Paste) / ACF (Anisotropic Conductive Film). The bump 180 is disposed on the conductive adhesive 450. In this embodiment, the bump 480 can be implemented as a pad.

[0057] Figures 5 to 7 Other aspects of the illustrated embodiments may be compared with those described above. Figure 2 The similar or identical ones described are not repeated here.

[0058] In summary, by increasing the coverage of the adhesive layer 162 to exceed the projection range of the bottom surface of the bump 180, the adhesive layer 162 provides a larger bonding area, and can provide a higher strength of adhesion and bonding ability at the interface between the adhesive layer 162 and the dielectric layer 112, avoiding the problem of over-etching caused by etching manufacturing, and causing the bump 180 to collapse or fall off, thereby improving the bonding efficiency between the bump 180 and the dielectric layer 112. By designing the adhesive layer 162 to protrude from the plating layer 164, a metal-to-metal bonding with sufficient strength can be provided at the corner 164c of the plating layer 164 adjacent to the adhesive layer 162 (here is the maximum bending stress point), thereby improving the bonding efficiency between the adhesive layer 162 and the plating layer 164. Since the coverage of the adhesive layer 162 can be the photoresist layer 431 (see Figure 4E ), so no etching process is required to form a pattern of the adhesive layer 162. Since no etching process is required to form a pattern of the adhesive layer 162, the adhesion and bonding ability at the interface between the adhesive layer 162 and the dielectric layer 112 will not be damaged.

[0059] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A package, characterized in that: include: Carrier board; A redistribution layer is disposed on the carrier, the redistribution layer includes a conductive layer, a dielectric layer disposed on the conductive layer, and a bump disposed on the dielectric layer, the bump being connected to the conductive layer via a conductive through hole penetrating the dielectric layer, The conductive via comprises an adhesive layer in contact with the dielectric layer, wherein a projection range of a bottom surface of the bump on the dielectric layer is smaller than a coverage range of the adhesive layer.

2. The package according to claim 1, characterized in that The conductive via includes a seed layer, the seed layer includes the adhesive layer and a plating layer arranged between the adhesive layer and the bump, and from the perspective of a vertical cross-section perpendicular to the upper surface of the dielectric layer, the width of the plating layer in the horizontal direction is smaller than the width of the adhesive layer in the horizontal direction.

3. The package according to claim 2, characterized in that The width of the plating layer is smaller than the width of the bump in the horizontal direction.

4. The package according to claim 1, characterized in that The conductive via comprises a seed layer, the seed layer comprises the adhesive layer and a plating layer disposed between the adhesive layer and the bump, the dielectric layer has an upper surface, the plating layer and the adhesive layer each have a horizontal extension extending between the bump and the upper surface, The thickness of a portion of the horizontally extending portion of the plating layer away from the edge thereof is greater than the thickness of the horizontally extending portion of the adhesive layer below the portion.

5. The package according to claim 4, characterized in that The thickness of an edge portion of the horizontally extending portion of the plating starting layer is smaller than the thickness of the horizontally extending portion of the adhesive layer below the edge portion.

6. The package according to claim 2, characterized in that The side surface of the plating layer is vertically coplanar with the side surface of the bump in a vertical direction perpendicular to the upper surface of the dielectric layer, and the adhesive layer protrudes from the side surface of the plating layer.

7. The package according to claim 2, characterized in that: The plating layer covers the adhesive layer and covers the side surface of the adhesive layer.

8. The package according to claim 7, characterized in that The upper surface of the dielectric layer contacts the adhesive layer, and outside the adhesive layer, the upper surface of the dielectric layer also contacts the starting layer.

9. The package according to claim 1, characterized in that: The adhesive layer has a horizontally extending portion extending horizontally above the upper surface of the dielectric layer, wherein the entirety of the horizontally extending portion is in continuous contact with the upper surface of the dielectric layer.

10. The package according to claim 2, characterized in that The plating start layer overlapping the bump is conformally disposed on the adhesive layer, and outside the bump, the adhesive layer protrudes from the side surface of the plating start layer and the side surface of the bump.

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