Electronic package and interposer

Abstract

An electronic package and an interposer are mainly characterized in that a recess is formed on a conductive via on a back side of an interposer body of the interposer, and a wiring structure electrically connected to the conductive via is directly formed on the back side of the interposer body and in the recess, without making a passivation layer, omitting a CVD process and a CMP process. Therefore, the manufacturing process can be effectively simplified, and a large amount of manufacturing time and material cost are saved.

Description

Technical Field

[0001] The present application relates to a semiconductor packaging technology, and more particularly to an electronic packaging component and an interposer capable of reducing costs. Background Art

[0002] With the booming development of the electronics industry, electronic products are gradually moving towards multi-functionality and high performance. Therefore, in addition to continuing to develop advanced processes, the semiconductor industry is also looking for ways to keep chips small while maintaining high performance. The concept of "heterogeneous integration" has become a popular concept in the contemporary world, and chips have also shifted from the original single-layer to multi-layer stacked advanced packaging.

[0003] Figures 1A to 1E It is a cross-sectional schematic diagram of a method for manufacturing a conventional silicon interposer 1 for chip stacking.

[0004] like Figure 1A As shown, a silicon board 10 having a first side 10a and a second side 10b opposite to each other is provided, and a plurality of conductive through-silicon vias (TSV) 100 composed of an insulating material 102 and a conductive material (such as copper material) 101 are formed in the silicon board 10, and a passivation layer 11 is formed on the first side 10a, and then a circuit redistribution layer (RDL) 12 electrically connected to the conductive silicon via 100 is formed on the passivation layer 11, and then an insulating protection layer 13 is formed on the passivation layer 11 and the circuit redistribution layer 12, so that the insulating protection layer 13 exposes a portion of the circuit redistribution layer 12 for combining a plurality of copper bumps 14 on the exposed surface of the circuit redistribution layer 12. Afterwards, a temporary carrier 5 (such as glass) is bonded to the insulating protection layer 13 of the first side 10a by means of glue 50, so that the copper bump 14 is buried in the glue 50, and then part of the material of the second side 10b is removed by grinding and wet etching, so that the conductive material 101 of the conductive silicon vias 100 protrudes from the second side 10b.

[0005] like Figure 1B As shown, another passivation layer 15 is formed on the second side 10 b by chemical vapor deposition (CVD) to cover the protruding conductive material 101 .

[0006] like Figure 1C As shown, the passivation layer 15 and the protruding conductive material 101 are polished by chemical-mechanical polishing (CMP) so that the end surface of the conductive TSV 100 is flush with the surface of the passivation layer 15 .

[0007] like Figure 1D As shown, an RDL process is performed on the passivation layer 15 to form a wiring structure 16, and the wiring structure 16 includes an insulating layer 160 disposed on the silicon board 10 and a wiring layer 161 formed on the insulating layer 160, so as to combine a plurality of solder bumps 17 of u-bump specifications on the wiring layer 161.

[0008] like Figure 1E As shown, the temporary carrier 5 and the adhesive 50 are removed.

[0009] However, in the conventional method of manufacturing the silicon interposer 1 , a CVD process and a CMP process are required to manufacture the silicon interposer 1 , which consumes a lot of process time and material costs (such as another passivation layer 15 ), resulting in a significant increase in manufacturing costs.

[0010] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Utility Model Content

[0011] In view of the various defects of the above-mentioned prior art, the present application provides an interposer, comprising: an interposer body having a first side and a second side opposite to each other, wherein a plurality of conductive through-holes are formed in the interposer body, and a plurality of recesses corresponding to the plurality of conductive through-holes are formed on the second side of the interposer body; and a wiring structure, which is disposed on the second side of the interposer body and extends into the plurality of recesses to electrically connect the plurality of conductive through-holes.

[0012] The present application also provides an electronic package, including: an intermediate board body, which has a first side and a second side opposite to each other, and a plurality of conductive through-holes are formed in the intermediate board body, and a plurality of recesses corresponding to the plurality of conductive through-holes are formed on the second side of the intermediate board body; a wiring structure, which is arranged on the second side of the intermediate board body and extends into the plurality of recesses to electrically connect the plurality of conductive through-holes; a circuit structure, which is arranged on the first side of the intermediate board body and electrically connected to the conductive through-holes; and an electronic component, which is arranged on the circuit structure and electrically connected to the circuit structure.

[0013] The aforementioned electronic package also includes a coating layer covering the interposer body, which has a first surface and a second surface opposite to each other, so that the circuit structure is arranged on the first surface of the coating layer. For example, it also includes a circuit portion formed on the second surface of the coating layer and electrically connected to the plurality of conductive through-holes. Furthermore, the circuit portion is combined with a plurality of conductive bumps.

[0014] Alternatively, it further comprises a plurality of conductive pillars formed in the cladding layer, which are electrically connected to the wiring structure. For example, another recess is formed on the plurality of conductive pillars, so that the wiring structure extends to the another recess to electrically connect the plurality of conductive pillars.

[0015] Alternatively, a plurality of conductive elements are combined on the wiring structure.

[0016] The present application also provides a method for manufacturing an electronic package, including: providing an intermediate board body having a first side and a second side opposite to each other, and forming a plurality of conductive through-holes in the intermediate board body; forming a plurality of recesses corresponding to the plurality of conductive through-holes on the second side of the intermediate board body; forming a wiring structure on the second side of the intermediate board body, and extending the wiring structure into the plurality of recesses to electrically connect the plurality of conductive through-holes; and placing the intermediate board body with its second side on a circuit portion having a plurality of conductive pillars, so that the wiring structure is electrically connected to the circuit portion through a plurality of conductive elements.

[0017] The aforementioned manufacturing method further includes forming a coating layer on the circuit portion so that the coating layer covers the interposer body and the wiring structure, and then forming a circuit structure on the coating layer and the first side of the interposer body so that the circuit structure is electrically connected to the conductive through hole. It may further include arranging an electronic component on the circuit structure so that the electronic component is electrically connected to the circuit structure.

[0018] The aforementioned manufacturing method further includes forming a plurality of conductive bumps on the circuit portion.

[0019] The present application further provides a method for manufacturing an electronic package, comprising: providing an intermediate board having a first side and a second side opposite to each other, and forming a plurality of conductive through-holes in the intermediate board; forming a circuit structure on the first side of the intermediate board so that the circuit structure is electrically connected to the conductive through-holes; arranging an electronic component on the circuit structure so that the electronic component is electrically connected to the circuit structure; forming a plurality of recesses corresponding to the plurality of conductive through-holes on the second side of the intermediate board; and forming a wiring structure on the second side of the intermediate board so that the wiring structure extends into the plurality of recesses so as to electrically connect the plurality of conductive through-holes.

[0020] The aforementioned manufacturing method further includes firstly covering the interposer body with a coating layer, and then forming the circuit structure on the coating layer and the first side of the interposer body. It also includes forming a plurality of conductive pillars in the coating layer, so that the plurality of conductive pillars are electrically connected to the circuit structure. Furthermore, another recess is formed on the plurality of conductive pillars, so that the wiring structure extends to the another recess to electrically connect the plurality of conductive pillars.

[0021] In the above-mentioned manufacturing method, a plurality of conductive elements are combined on the wiring structure.

[0022] In the aforementioned electronic package and two manufacturing methods thereof and the interposer, a circuit redistribution layer electrically connected to the plurality of conductive through-holes is formed on the first side of the interposer body.

[0023] From the above, it can be seen that the electronic package and its manufacturing method and the intermediate board of the present application mainly form a wiring structure directly on the second side of the intermediate board body and the recess by forming a recess in the conductive through-hole, without the need to make a passivation layer, omitting the CVD process and the CMP process. Therefore, compared with the prior art, the electronic package of the present application can effectively simplify the process to save a lot of process time and material costs, thereby significantly reducing the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figures 1A to 1E The cross-sectional view is a schematic diagram of a conventional method for manufacturing a silicon interposer.

[0025] FIG. 2A to FIG. 2I It is a cross-sectional schematic diagram of a first embodiment of a method for manufacturing an electronic package of the present application.

[0026] Figure 2F-1 for Figure 2F A cross-sectional schematic diagram of another embodiment of the present invention.

[0027] FIG. 3A to FIG. 3F It is a cross-sectional schematic diagram of a second embodiment of a method for manufacturing an electronic package of the present application.

[0028] DESCRIPTION OF REFERENCE NUMERALS

[0029] 1 Silicon interposer

[0030] 10 Silicon plate

[0031] 10a,21a First side

[0032] 10b,21b Second side

[0033] 100 Conductive Silicon Via

[0034] 102,210a Insulation materials

[0035] 101,210b Conductive materials

[0036] 11,15,211 Passivation layer

[0037] 12,212 redistribution layers

[0038] 13,213 Insulation protective layer

[0039] 14 Copper Bumps

[0040] 16,22,32 wiring structure

[0041] 160,220,320 Insulation layer

[0042] 161,221,321 wiring layer

[0043] 17 Solder Bumps

[0044] 2,3 Electronic packaging

[0045] 2a Intermediary board

[0046] 20 Line Department

[0047] 200 First dielectric layer

[0048] 201 First Circuit Layer

[0049] 21 Intermediate board

[0050] 210 Conductive Perforation

[0051] 214 Conductor

[0052] 215 Dielectric Materials

[0053] 23 Conductive column

[0054] 24,34 Conductive elements

[0055] 25 Coating

[0056] 25a First surface

[0057] 25b Second surface

[0058] 26 Line Structure

[0059] 260 Second dielectric layer

[0060] 261 Second circuit layer

[0061] 262 Electrical contact pads

[0062] 27 Encapsulation layer

[0063] 28 Electronic components

[0064] 280,29 Conductive bumps

[0065] 281 Primer

[0066] 30 Bonding layer

[0067] 5 Temporary Vehicles

[0068] 50 Rubber

[0069] 9 Bearing

[0070] 90 Release layer

[0071] 91 Seed layer

[0072] S recess

[0073] L Cutting path. DETAILED DESCRIPTION

[0074] The following describes the implementation methods of the present application through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification.

[0075] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of this application, so they have no substantial technical significance. Any modification of the structure, change in the proportion relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application. At the same time, the terms such as "on", "first", "second", "one", etc. cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of this application. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of this application without substantially changing the technical contents.

[0076] FIG. 2A to FIG. 2I It is a cross-sectional schematic diagram of a first embodiment of a method for manufacturing an electronic package 2 of the present application.

[0077] like Figure 2A As shown, an intermediate board body 21 is provided, which has a first side 21a and a second side 21b opposite to each other, and a plurality of conductive through holes 210 composed of insulating material 210a and conductive material 210b are formed in the intermediate board body 21, and a passivation layer 211 is formed on the first side 21a, and a circuit redistribution layer 212 electrically connected to the conductive through hole 210 is formed on the passivation layer 211, and then an insulating protection layer 213 is formed on the passivation layer 211 and the circuit redistribution layer 212, so that the insulating protection layer 213 exposes a portion of the circuit redistribution layer 212, so as to provide for combining a plurality of conductors 214 on the exposed surface of the circuit redistribution layer 212 and protruding the insulating protection layer 213. Next, a temporary carrier 5 is bonded to the insulating protective layer 213 of the first side 21a with glue 50, so that the protruding section of the conductor 214 is buried in the glue 50, and then part of the material of the second side 21b is removed by grinding, so that the end surface of the conductive through hole 210 is flush with the surface of the second side 21b of the interposer 21.

[0078] In this embodiment, the interposer 21 is a semiconductor plate such as silicon or glass, and the conductive material 210 b is a metal material such as copper, so that the conductive through-hole 210 becomes a conductive through-silicon via (TSV).

[0079] Furthermore, the conductor 214 is a copper bump, and the temporary carrier 5 is a glass plate.

[0080] like Figure 2B As shown, part of the conductive material 210 b of the conductive through-hole 210 on the second side 21 b is removed to form a plurality of recesses S on the conductive through-hole 210 on the second side 21 b .

[0081] In this embodiment, the recesses S are formed by micro-etching or other methods.

[0082] like Figure 2C As shown, a wiring structure 22 is formed on the second side 21 b of the interposer body 21 to electrically connect the conductive through-hole 210 .

[0083] In this embodiment, the wiring structure 22 includes at least one insulating layer 220 disposed on the interposer body 21 and a wiring layer 221 formed on the insulating layer 220, and the wiring layer 221 extends into the recess S to electrically connect the conductive through-hole 210. For example, the wiring layer 221 is formed by electroplating, coating or other methods using an RDL process.

[0084] Furthermore, a plurality of conductive elements 24 may be formed on the outermost wiring layer 221 by patterning photoresist. For example, the conductive element 24 adopts a u-bump specification, which includes solder material.

[0085] like Figure 2D As shown, remove the temporary carrier 5 and the adhesive 50, and Figure 2C The cutting path L shown is used for performing a singulation process to obtain a plurality of interposers 2 a.

[0086] like Figure 2E As shown, a carrier 9 is provided, on which a circuit portion 20 is formed, so that the interposer 2a is disposed on the circuit portion 20 with its second side 21b, so that the conductive element 24 is electrically connected to the circuit portion 20.

[0087] In this embodiment, the carrier 9 is, for example, a plate of semiconductor material (such as silicon or glass), on which a release layer 90 and a seed layer 91 such as titanium / copper are sequentially formed, for example, by coating, so that the circuit portion 20 can be formed on the carrier 9 by a patterning process.

[0088] Furthermore, the circuit portion 20 is a coreless specification, which includes a first dielectric layer 200 and a first circuit layer 201 disposed on the first dielectric layer 200 and electrically connected to the conductive element 24, such as a circuit redistribution layer (RDL) specification. For example, the material forming the first circuit layer 201 is copper, and the material forming the first dielectric layer 200 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

[0089] In addition, a plurality of conductive pillars 23 electrically connected to the circuit portion 20 may be formed on the circuit portion 20. For example, the conductive pillars 23 are made of a metal material such as copper or a solder material, but are not limited thereto.

[0090] like Figure 2F As shown, a coating layer 25 is formed on the circuit portion 20 of the carrier 9 so that the coating layer 25 covers the intermediate board 2a and the multiple conductive pillars 23, wherein the coating layer 25 has a first surface 25a and a second surface 25b opposite to each other, and the end surfaces of the protruding sections of the conductive pillars 23 and the conductors 214 are exposed to the first surface 25a of the coating layer 25, and the coating layer 25 is bonded to the circuit portion 20 with its second surface 25b.

[0091] In this embodiment, the coating layer 25 is an insulating material, such as polyimide (PI), dry film, packaging colloid or molding compound such as epoxy. For example, the coating layer 25 can be formed on the circuit portion 20 by a process such as liquid compound, injection, lamination or compression molding.

[0092] Furthermore, a flattening process may be performed to make the first surface 25a of the cladding layer 25 flush with the end surfaces of the conductive pillar 23 and the conductor 214, so that the conductive pillar 23 and the conductor 214 are exposed on the first surface 25a of the cladding layer 25. For example, the flattening process removes part of the material of the conductor 214, part of the material of the cladding layer 25, and part of the material of the conductive pillar 23 by grinding.

[0093] Or, if Figure 2F-1 As shown, the intermediate board 2a may also firstly cover the protruding section of the conductor 214 with a dielectric material 215 such as PI (which may be Figure 2A The process stage shown or Figure 2D The intermediate board 2a is then covered with the covering layer 25 and a flattening process is performed.

[0094] like Figure 2G As shown, a circuit structure 26 is formed on the first surface 25 a of the cladding layer 25 , so that the circuit structure 26 electrically connects the conductive pillars 23 and the conductors 214 on the interposer 2 a .

[0095] In this embodiment, the circuit structure 26 includes a plurality of second dielectric layers 260 formed on the first surface 25a and a second circuit layer 261 formed on the second dielectric layer 260, such as a circuit redistribution layer (RDL) specification, so that the second circuit layer 261 electrically connects the conductive column 23 and the conductor 214.

[0096] Furthermore, the outermost second dielectric layer 260 can be used as a solder mask layer to expose the outermost second circuit layer 261 from the solder mask layer to serve as an electrical contact pad 262. Alternatively, the circuit structure 26 can also include only a single second dielectric layer 260 and a single second circuit layer 261.

[0097] In addition, the material forming the second circuit layer 261 is copper, and the material forming the second dielectric layer 260 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), etc., or a solder mask material such as green paint, ink, etc. It should be understood that the materials of the first dielectric layer 200 and the second dielectric layer 260 can be the same or different.

[0098] like Figure 2H As shown, at least one electronic component 28 is disposed on the circuit structure 26 , and then the electronic component 28 is covered by a packaging layer 27 .

[0099] The electronic component 28 is, for example, an active component, a passive component, a packaging structure or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor.

[0100] In this embodiment, the electronic component 28 is a semiconductor chip, which can be disposed on the electrical contact pad 262 of the circuit structure 26 in a flip chip manner through a plurality of solder bumps, copper bumps or other equivalent conductive bumps 280 and electrically connected to the second circuit layer 261, and the conductive bumps 280 can be coated with a primer 281; or, the electronic component 28 can be electrically connected to the second circuit layer 261 through a plurality of welding wires in a wire bonding manner; or, the electronic component 28 can directly contact the second circuit layer 261. It should be understood that there are many ways for the electronic component 28 to be electrically connected to the circuit structure 26, and it is not limited to the above.

[0101] Furthermore, the packaging layer 27 is an insulating material, such as polyimide (PI), dry film, packaging colloid such as epoxy, or molding compound. For example, the packaging layer 27 can be formed on the circuit structure 26 by a process such as liquid compound, injection, lamination, or compression molding. It should be understood that the materials of the packaging layer 27 and the cladding layer 25 can be the same or different.

[0102] like Fig.2I As shown, the carrier 9 and the release layer 90 and the seed layer 91 thereon are removed to expose the circuit portion 20 .

[0103] In this embodiment, the circuit portion 20 exposes a portion of the surface of the first circuit layer 201 to form a plurality of conductive bumps 29 of solder material, such as C4 specification, thereon, so that in subsequent processes, the electronic package 2 can be connected to an electronic device such as a circuit board (not shown) through these conductive bumps 29.

[0104] Furthermore, the packaging layer 27 may be ground to make the surface of the packaging layer 27 flush with the surface of the electronic component 28 so as to expose the electronic component 28 .

[0105] Therefore, the manufacturing method of the intermediate board 2a of the present application is mainly to form a recess S on the conductive through-hole 210 to directly form a wiring structure 22 on the second side 21b of the intermediate board body 21 and the recess S, so that the second side 21b of the intermediate board body 21 does not need to be made into a passivation layer, and thus there is no need to perform a CVD process and a CMP process. Therefore, compared with the prior art, the electronic package 2 of the present application can effectively simplify the process to save a lot of process time and material costs (such as passivation materials), thereby significantly reducing the manufacturing cost.

[0106] FIG. 3A to FIG. 3FThe cross-sectional view of the second embodiment of the manufacturing method of the electronic package 3 of the present application is shown in FIG. The difference between the second embodiment and the first embodiment lies in the manufacturing sequence of the recessed portion, and the other structures are substantially the same, so the same points will not be described in detail below.

[0107] like Figure 3A As shown, a carrier 9 is provided, and a plurality of conductive pillars 23 are formed on a release layer 90 thereof through a seed layer 91 .

[0108] like Figure 3B As shown, at least one Figure 2A The intermediate board 21 shown is subjected to a singulation process, and then its second side 21b is disposed on the carrier 9, and then a coating layer 25 is formed on the carrier 9 so that the coating layer 25 covers the intermediate board 21 and the conductive pillars 23, and the first surface 25a of the coating layer 25 is flush with the end surfaces of the conductive pillars 23 and the conductor 214, so that the conductive pillars 23 and the conductor 214 are exposed on the first surface 25a of the coating layer 25.

[0109] In this embodiment, the interposer 21 is bonded to the seed layer 91 via a bonding layer 30 such as glue.

[0110] like Figure 3C As shown, a circuit structure 26 is formed on the first surface 25 a of the coating layer 25 , so that the circuit structure 26 electrically connects the conductive pillars 23 and the conductors 214 on the interposer 21 , and then at least one electronic component 28 is disposed on the circuit structure 26 , and then the electronic component 28 is coated with a packaging layer 27 .

[0111] like Figure 3D As shown, the carrier 9 and the release layer 90 and the seed layer 91 thereon are removed to expose the second surface 25 b of the cladding layer 25 , and the bonding layer 30 is removed to expose the second side 21 b of the interposer 21 .

[0112] In this embodiment, the end surface of the conductive through hole 210 and the end surface of the conductive pillar 23 are exposed on the second surface 25 b of the packaging layer 27 .

[0113] like Figure 3E As shown, a portion of the conductive material 210 b of the conductive through-hole 210 and a portion of the material of the conductive pillar 23 are removed to form a plurality of recesses S on the conductive through-hole 210 and the conductive pillar 23 .

[0114] In this embodiment, the recesses S are formed by micro-etching or other methods.

[0115] like Figure 3FAs shown, a wiring structure 32 is formed on the second side 21 b of the interposer body 21 and the second surface 25 b of the cladding layer 25 to electrically connect the conductive through-hole 210 and the conductive pillar 23 .

[0116] In this embodiment, the wiring structure 32 includes an insulating layer 320 disposed on the interposer body 21 and the cladding layer 25 and a wiring layer 321 formed on the insulating layer 320, and the wiring layer 321 extends into the recess S to electrically connect the conductive through-hole 210 and the conductive pillar 23. For example, the wiring layer 321 is formed by electroplating, coating or other methods using an RDL process.

[0117] Furthermore, a plurality of conductive elements 34 may be formed on the outermost wiring layer 321 by patterning photoresist, so that in subsequent manufacturing processes, the electronic package 3 may be connected to an electronic device such as a circuit board (not shown) through the conductive elements 34 .

[0118] Therefore, the manufacturing method of the present application forms a recess S in the conductive through-hole 210 to directly form a wiring structure 32 on the second side 21b of the intermediate board 21 and the recess S, without the need to form a passivation layer, thereby omitting the CVD process and the CMP process. Therefore, compared with the prior art, the electronic package 3 of the present application can effectively simplify the process to save a large amount of process time and material costs (such as passivation materials), thereby significantly reducing the manufacturing cost.

[0119] The present application provides an interposer 2 a , including an interposer body 21 and a wiring structure 22 , 32 .

[0120] The interposer 21 has a first side 21 a and a second side 21 b opposite to each other. A plurality of conductive through holes 210 are formed in the interposer 21 , and a plurality of recesses S corresponding to the plurality of conductive through holes 210 are formed on the second side 21 b of the interposer 21 .

[0121] The wiring structures 22 , 32 are disposed on the second side 21 b of the interposer body 21 and extend into the plurality of recesses S to electrically connect the plurality of conductive through-vias 210 .

[0122] The interposer 2 a further includes a redistribution layer 212 disposed on the first side 21 a of the interposer body 21 and electrically connected to the plurality of conductive through vias 210 .

[0123] The present application also provides an electronic package 2 , 3 , including: the aforementioned interposer 2 a , a circuit structure 26 , and at least one electronic component 28 .

[0124] The circuit structure 26 is disposed on the first side 21 a of the interposer body 21 and is electrically connected to the conductive through-hole 210 .

[0125] The electronic component 28 is disposed on the circuit structure 26 and electrically connected to the circuit structure 26 .

[0126] In one embodiment, the electronic package 2 , 3 further includes a covering layer 25 covering the interposer 21 and the wiring structures 22 , 32 , and having a first surface 25 a and a second surface 25 b opposite to each other, so that the circuit structure 26 is disposed on the first surface 25 a of the covering layer 25 .

[0127] In one embodiment, the electronic package 2 further includes a circuit portion 20 formed on the second surface 25b of the coating layer 25, which is electrically connected to the wiring structure 22 through a plurality of conductive elements 24. For example, a plurality of conductive bumps 29 are combined on the circuit portion 20.

[0128] In one embodiment, the electronic package 2, 3 further includes a plurality of conductive pillars 23 formed in the coating layer 25, which are electrically connected to the wiring structure 26. For example, another recess S is formed on the plurality of conductive pillars 23, so that the wiring structure 32 extends to the another recess S to electrically connect the plurality of conductive pillars 23.

[0129] In one embodiment, a plurality of conductive elements 24 , 34 are combined on the wiring structures 22 , 32 .

[0130] In summary, the electronic package and its manufacturing method and the intermediate board of the present application, through the design of the recess, do not need to form a passivation layer on the second side of the intermediate board body, and therefore do not need to perform a CVD process and a CMP process. Therefore, the present application can effectively simplify the process to save a lot of process time and material costs, thereby significantly reducing the manufacturing cost.

[0131] The above embodiments are only used to illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present application. Therefore, the scope of protection of the present application should be as listed in the claims.

Claims

1. An interposer, characterized in that: include: An intermediate board body having a first side and a second side opposite to each other, a plurality of conductive through holes formed in the intermediate board body, and a plurality of recesses corresponding to the plurality of conductive through holes formed on the second side of the intermediate board body; as well as The wiring structure is disposed on the second side of the interposer body and extends into the plurality of recesses to electrically connect the plurality of conductive through holes.

2. The interposer according to claim 1, wherein: The interposer also includes a circuit redistribution layer disposed on the first side of the interposer body and electrically connected to the plurality of conductive through-holes.

3. An electronic package, characterized in that: include: An intermediate board body having a first side and a second side opposite to each other, a plurality of conductive through holes formed in the intermediate board body, and a plurality of recesses corresponding to the plurality of conductive through holes formed on the second side of the intermediate board body; A wiring structure disposed on the second side of the interposer body and extending into the plurality of recesses to electrically connect the plurality of conductive through-holes; A circuit structure disposed on the first side of the interposer body and electrically connected to the conductive through hole; as well as The electronic component is arranged on the circuit structure and electrically connected to the circuit structure.

4. The electronic package as claimed in claim 3, characterized in that The electronic package also includes a covering layer covering the intermediate board body, which has a first surface and a second surface opposite to each other, so that the circuit structure is arranged on the first surface of the covering layer.

5. The electronic package as claimed in claim 4, characterized in that The electronic package also includes a circuit portion which is arranged on the second surface of the covering layer and electrically connected to the plurality of conductive through holes.

6. The electronic package according to claim 5, characterized in that A plurality of conductive bumps are combined on the circuit portion.

7. The electronic package according to claim 4, characterized in that: The electronic package also includes a plurality of conductive pillars formed in the covering layer and electrically connected to the circuit structure.

8. The electronic package according to claim 7, wherein: Another concave portion is formed on the plurality of conductive pillars, so that the wiring structure extends to the another concave portion to electrically connect the plurality of conductive pillars.

9. The electronic package according to claim 5 or 8, characterized in that: The wiring structure is combined with a plurality of conductive elements.

10. The electronic package according to claim 3, wherein: The electronic package also includes a circuit redistribution layer disposed on the first side of the intermediate board body and electrically connected to the plurality of conductive through holes.

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