Display substrate and display device

Abstract

The utility model discloses a display substrate and a display device. The display substrate comprises a substrate which comprises a display area and a frame area surrounding the display area; a plurality of sub-pixels located in the display area; the multiple grid lines are located in the display area and the frame area and electrically connected with the multiple sub-pixels, and the multiple grid lines are configured to provide grid signals for the multiple sub-pixels; the grid driving circuit is located in the frame area and is connected with the plurality of grid lines; the at least one electrostatic protection unit is located in the frame area and connected with the grid line, the at least one electrostatic protection unit is configured to release static electricity in the preparation process of the display substrate, the electrostatic protection unit comprises at least one tip structure, and the extending direction of the tip structure intersects with the plane where the substrate is located.

Description

Technical Field

[0001] The utility model relates to but is not limited to the field of display technology, in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003] Currently, when manufacturing display substrates, the yield rate of transistors is not high. Utility Model Content

[0004] The embodiments of the utility model provide a display substrate and a display device, which can solve the problem of low transistor yield when preparing the display substrate.

[0005] On the one hand, an embodiment of the utility model provides a display substrate, comprising: a substrate, comprising a display area and a frame area surrounding the display area; a plurality of sub-pixels, located in the display area; a plurality of gate lines, located in the display area and the frame area, and electrically connected to the plurality of sub-pixels, the plurality of gate lines being configured to provide gate signals to the plurality of sub-pixels; a gate drive circuit, located in the frame area, and connected to the plurality of gate lines; at least one electrostatic protection unit, located in the frame area and connected to the gate lines, the at least one electrostatic protection unit being configured to release static electricity on the display substrate during the preparation process, the electrostatic protection unit comprising at least one tip structure, the extension direction of the tip structure intersecting with the plane where the substrate is located.

[0006] In an exemplary embodiment, one of the multiple gate lines includes a first line segment, a second line segment, and a third line segment, the first line segment and the second line segment are located in the border area, the third line segment is located in the display area, and the at least one electrostatic protection unit is connected to at least one of the first line segment or the second line segment; the display substrate also includes a transition structure, which is located between the first line segment and the second line segment and connects the first line segment and the second line segment.

[0007] In an exemplary embodiment, the at least one electrostatic protection unit is multiple in number, and the multiple electrostatic protection units are respectively located on both sides of the switching structure and are respectively connected to the first line segment and the second line segment.

[0008] In an exemplary embodiment, the multiple gate lines include a first gate line and a second gate line, the first gate line and the second gate line are adjacent to each other; an electrostatic protection unit connected to a first line segment of the first gate line and an electrostatic protection unit connected to a first line segment of the second gate line are both located between the first gate line and the second gate line; and / or an electrostatic protection unit connected to a second line segment of the first gate line and an electrostatic protection unit connected to a second line segment of the second gate line are both located between the first gate line and the second gate line.

[0009] In an exemplary embodiment, the top angle of the tip structure is set to be greater than or equal to 0 degrees and less than or equal to 160 degrees.

[0010] In an exemplary embodiment, the electrostatic protection unit includes a plurality of the tip structures, and at least some of the tip structures in the plurality of the tip structures have the same top angle.

[0011] In an exemplary embodiment, the tip structure extends in a direction perpendicular to a plane in which the substrate is located.

[0012] In an exemplary embodiment, the display substrate includes a driving circuit layer arranged on the base, and a light-emitting structure layer arranged on a side of the driving circuit layer away from the base, the sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit drives the light-emitting element to emit light, the pixel circuit is located in the driving circuit layer, and the light-emitting element is located in the light-emitting structure layer.

[0013] In an exemplary embodiment, the driving circuit layer of the display area includes a first insulating layer, a first active layer, a second insulating layer, a first gate electrode, a third insulating layer and a source-drain electrode layer arranged in sequence along a direction away from the substrate; the electrostatic protection unit includes a first protective layer, a third protective layer and a fourth protective layer arranged in sequence along a direction away from the substrate; wherein the first protective layer and the first insulating layer are arranged on the same layer, the third protective layer and the second insulating layer are arranged on the same layer, and the fourth protective layer and the first gate electrode are arranged on the same layer.

[0014] In an exemplary embodiment, the electrostatic protection unit also includes a sixth protection layer, and at least one of a second protection layer and a fifth protection layer; wherein the second protection layer and the first active layer are arranged on the same layer, the fifth protection layer and the third insulating layer are arranged on the same layer, and the sixth protection layer and the source-drain electrode layer are arranged on the same layer.

[0015] In an exemplary embodiment, the driving circuit layer of the display area also includes a light-shielding electrode, which is located on a side of the first insulating layer close to the substrate; the frame area includes a light-shielding portion arranged in the same layer as the light-shielding electrode, and the light-shielding portion is located on a side of the electrostatic protection unit close to the substrate.

[0016] In an exemplary embodiment, in a direction away from the substrate, the light-emitting structure layer of the display area includes a flat layer and a light-emitting device arranged on the flat layer, and the electrostatic protection unit includes a seventh protection layer, an eighth protection layer, a ninth protection layer and a tenth protection layer arranged in sequence; the tip structure is located at the seventh protection layer, the eighth protection layer, the ninth protection layer and the tenth protection layer; wherein the seventh protection layer and the flat layer are arranged on the same layer, the eighth protection layer and the anode of the light-emitting device are arranged on the same layer, the ninth protection layer and the organic light-emitting layer of the light-emitting device are arranged on the same layer, and the tenth protection layer and the cathode of the light-emitting device are arranged on the same layer.

[0017] In an exemplary embodiment, the electrostatic protection unit further includes a first color film, a second color film and a third color film stacked in sequence; the third color film is located on a side of the seventh protection layer close to the substrate.

[0018] In an exemplary embodiment, the electrostatic protection unit further includes an electrostatic discharge transistor, and the electrostatic discharge transistor is disposed in the driving circuit layer.

[0019] In an exemplary embodiment, in a direction perpendicular to the substrate, the distance between the surface of the tenth protective layer away from the substrate and the substrate is a first distance, and the distance between the surface of the cathode away from the substrate and the substrate is a second distance; the difference between the first distance and the second distance is set to be greater than or equal to 2.7 microns and less than or equal to 6.6 microns.

[0020] In an exemplary embodiment, the border area includes a circuit area, and the circuit area includes a gate driving circuit; wherein at least one of the electrostatic protection units is located on a side of the circuit area close to the display area, or at least one of the electrostatic protection units is arranged to surround the display area and the circuit area.

[0021] In an exemplary embodiment, the transition structure includes a tip serration, and an extension direction of the tip serration is located in a plane where the base is located.

[0022] In a second aspect, an embodiment of the present invention provides a display device, comprising the display substrate as described above.

[0023] The display substrate proposed in the embodiment of the utility model is provided with at least one electrostatic protection unit in the frame area, and the electrostatic protection unit includes at least one tip structure. The electrostatic protection unit can release the static electricity of the display substrate during the preparation process, thereby facilitating the timely release of the static electricity accumulated during the preparation of the transistor, avoiding the damage to the transistor caused by static electricity, thereby improving the production yield of the transistor when preparing the display substrate. The problem of low yield of transistors when preparing the display substrate is solved.

[0024] Other features and advantages of the utility model will be described in the following description, and partly become apparent from the description, or understood by implementing the utility model. The purpose and other advantages of the utility model can be realized and obtained through the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide a further understanding of the technical solution of the utility model and constitute a part of the specification. Together with the embodiments of the utility model, they are used to explain the technical solution of the utility model and do not constitute a limitation on the technical solution of the utility model.

[0026] Figure 1 is a structural schematic diagram of a display device;

[0027] Figure 2 It is a schematic diagram of a planar structure of a display substrate;

[0028] Figure 3 It is a schematic diagram of the planar structure of a display area in a display substrate;

[0029] Figure 4 A schematic diagram of the cross-sectional structure of a display area in a display substrate;

[0030] Figure 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0031] Figure 6 A top view of a display substrate provided for an exemplary embodiment;

[0032] Figure 7 A top view of a display substrate provided for yet another exemplary embodiment;

[0033] Figure 8 In an exemplary embodiment Figure 6 An enlarged view of the dashed area E;

[0034] Fig. 9 In an exemplary embodiment Figure 6 A cross-sectional view along the BB direction;

[0035] Fig.10 for Figure 8 A cross-sectional view of the tip structure of the electrostatic protection unit;

[0036] Fig.11 is a schematic diagram of a display substrate after a light shielding layer pattern is formed in an exemplary embodiment;

[0037] Fig.12 is a schematic diagram of a display substrate after forming a first insulating layer pattern in an exemplary embodiment;

[0038] Fig.13 is a schematic diagram of a display substrate after a semiconductor layer pattern is formed in an exemplary embodiment;

[0039] Fig.14 is a schematic diagram of a display substrate after a gate layer pattern is formed in an exemplary embodiment;

[0040] Fig.15 is a schematic diagram of a display substrate after a third insulating layer pattern is formed in an exemplary embodiment;

[0041] Fig.16 In yet another exemplary embodiment Figure 6 BB cross-sectional view. DETAILED DESCRIPTION

[0042] The utility model describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the utility model. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0043] The present invention includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features and elements of the present invention may also be combined with any conventional features or elements to form a unique invention scheme defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present invention may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0044] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be appreciated by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the utility model.

[0045] In the drawings, the size of one or more components, the thickness of a layer, or a region may be exaggerated for clarity. In addition, the drawings schematically show ideal examples, and one embodiment of the present invention is not limited to the shapes or numerical values ​​shown in the drawings.

[0046] The ordinal numbers such as "first", "second", "third" and the like in this specification are provided to avoid confusion of constituent elements, rather than to limit the quantity. The "plurality" in this utility model means two or more.

[0047] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. The positional relationship of the constituent elements is appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the specification and can be appropriately replaced according to the circumstances.

[0048] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this utility model can be understood according to the circumstances.

[0049] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0050] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0051] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0052] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0053] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0054] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0055] The term "about" in this specification refers to a numerical value that is not strictly limited and allows for process and measurement errors.

[0056] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line, the light emitting signal line and the data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal suitable for the specification of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specification of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal, and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number. The light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0057] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, in an exemplary embodiment, the display substrate includes a display area 100 and a frame area 300 arranged around the display area 100, and the frame area 300 may include a binding area 200 located on one side of the display area 100 along the second direction Y. The display area 100 includes at least a plurality of pixel units arranged regularly, for example, the plurality of pixel units may be arranged in an array along a first direction X and a second direction Y, the first direction X and the second direction Y intersect, the first direction X may be a row direction, and the second direction Y may be a column direction. The plurality of pixel units are configured to display dynamic pictures or still images, and the display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be deformable, such as curled, bent, folded or rolled up.

[0058] In an exemplary embodiment, the shape of the display area 100 may be a quadrilateral, a circle, an ellipse, a polygon of other shapes or an irregular shape, etc., and the corner shape of the display area 100 may be rounded, which is not limited in the present invention.

[0059] In an exemplary embodiment, the binding area 200 may include a fan-out area, a bending area, a driver chip area, and a binding pin area arranged in sequence along a direction away from the display area 100. The fan-out area is connected to the display area 100 and may include at least a plurality of data lead-out lines parallel to each other. The bending area is connected to the fan-out area and may include a composite insulating layer provided with a groove, configured to bend the binding area to the back of the display area. The driver chip area may include at least an integrated circuit (IC) configured to be connected to a plurality of data fan-out lines. The binding pin area may include at least a plurality of bonding pads (Bonding Pad), configured to be bound and connected to an external flexible printed circuit (FPC).

[0060] In an exemplary embodiment, the border area 300 may include a circuit area, which may be arranged on both sides of the display area 100 along the first direction X and may be connected to the display area 100, and the circuit area may include at least a gate driving circuit 301, which is connected to the scanning signal line and the light-emitting signal line of the pixel driving circuit in the display area 100.

[0061] Figure 3 FIG. 1 is a schematic diagram of a planar structure of a display area in a display substrate. Figure 3As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting unit is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0062] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel or triangular manner, which is not limited in the present invention.

[0063] In an exemplary embodiment, a pixel unit may include four sub-pixels. For example, the four sub-pixels may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel emitting white (W) light. For another example, the four sub-pixels may include a red sub-pixel, a blue sub-pixel, and two green sub-pixels. In an exemplary embodiment, the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a square shape, a diamond shape, etc., which is not limited in the present invention.

[0064] Figure 4 FIG. 1 is a schematic diagram of a cross-sectional structure of a display region in a display substrate, illustrating the structure of three sub-pixels in the display region. Figure 4 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and a packaging structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present invention.

[0065] In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. Figure 4 A single transistor K of the pixel driving circuit is illustrated in the dotted area, and the transistor K may be, for example, a driving transistor, and the transistor K may include a bottom gate electrode, an active layer, a top gate electrode, a source electrode, and a drain electrode. The light emitting structure layer 103 may include a plurality of light emitting units, and each light emitting unit may include at least an anode 131, a pixel definition layer 132, an organic light emitting layer 133, and a cathode 134. The anode 131 is connected to the pixel driving circuit, the organic light emitting layer 133 is connected to the anode 131, and the cathode 134 is connected to the organic light emitting layer 133. The organic light emitting layer 133 emits light of corresponding colors under the drive of the anode 131 and the cathode 134. The encapsulation structure layer 104 may include a first encapsulation layer 141, a second encapsulation layer 142 and a third encapsulation layer 143 stacked together. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, and the second encapsulation layer 142 may be made of organic materials. The second encapsulation layer 142 is arranged between the first encapsulation layer 141 and the third encapsulation layer 143 to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0066] Figure 5 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure, or may adopt other structures, which are not limited by the present invention. Figure 5 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C, and the pixel driving circuit is connected to 7 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS).

[0067] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the second node N2 is respectively connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C, and the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.

[0068] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0069] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3, so that the charge amount of the control electrode of the third transistor T3 is initialized.

[0070] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0071] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between its control electrode and the first electrode.

[0072] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. When the on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.

[0073] The control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. When the on-level light emitting signal is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting device emit light.

[0074] The control electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the on-level scan signal is applied to the second scan signal line S2, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light emitting device to initialize or release the charge accumulated in the first electrode of the light emitting device.

[0075] In an exemplary embodiment, the light-emitting device can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode), or can be an LED.

[0076] In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously provided high level signal. The first scanning signal line S1 is a scanning signal line in the pixel driving circuit of the current display row, and the second scanning signal line S2 is a scanning signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scanning signal line S1 is S(n), and the second scanning signal line S2 is S(n-1), and the second scanning signal line S2 of the current display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.

[0077] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.

[0078] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS for short), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current. The low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO for short) display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0079] In some technologies, taking the formation of a transistor with a top gate structure as an example, the usual preparation process includes: forming an active layer and a gate on a substrate in sequence, then forming an interlayer insulating layer, the interlayer insulating layer includes a source via and a drain via, the source via and the drain via respectively expose the two ends of the active layer, then forming a source and a drain, the source is connected to one end of the active layer through the source via, and the drain is connected to the other end of the active layer through the drain via, thereby forming a transistor. After the transistor is formed, a passivation layer is formed above the source and the drain, and the display substrate is continued to be prepared. The inventor of the present application has found that in the process of forming an interlayer insulating layer above the gate, when an insulating film is deposited and a via is formed on the insulating film, static electricity will be generated on the surface of the gate. In addition, static electricity will be generated on the surface of the source and the drain during the dry etching of the passivation layer. The accumulation of such static electricity can easily damage the transistor, affect the device performance, cause GDS defects, and reduce the production yield of the transistor.

[0080] An embodiment of the utility model provides a display substrate, comprising: a substrate, comprising a display area and a frame area surrounding the display area; a plurality of sub-pixels, located in the display area; a plurality of gate lines, located in the display area and the frame area, and electrically connected to the plurality of sub-pixels, the plurality of gate lines being configured to provide gate signals to the plurality of sub-pixels; a gate drive circuit, located in the frame area, and connected to the plurality of gate lines; at least one electrostatic protection unit, located in the frame area and connected to the gate lines, the at least one electrostatic protection unit being configured to release static electricity on the display substrate during the preparation process, the electrostatic protection unit comprising at least one tip structure, the extension direction of the tip structure intersecting with the plane where the substrate is located.

[0081] The display substrate proposed in the embodiment of the utility model has at least one electrostatic protection unit arranged in the frame area, and the electrostatic protection unit includes at least one tip structure. The electrostatic protection unit can be used to release static electricity in the display substrate during the preparation process, thereby helping to timely release static electricity accumulated in the process of preparing transistors, avoiding damage to transistors caused by static electricity, thereby improving the production yield of transistors when preparing display substrates.

[0082] In an exemplary embodiment, one of the multiple gate lines includes a first line segment, a second line segment, and a third line segment, the first line segment and the second line segment are located in the border area, the third line segment is located in the display area, and the at least one electrostatic protection unit is connected to at least one of the first line segment or the second line segment; the display substrate also includes a transition structure, which is located between the first line segment and the second line segment and connects the first line segment and the second line segment.

[0083] In an exemplary embodiment, the at least one electrostatic protection unit is multiple in number, and the multiple electrostatic protection units are respectively located on both sides of the switching structure and are respectively connected to the first line segment and the second line segment.

[0084] In an exemplary embodiment, the driving circuit layer of the display area includes a first insulating layer, a first active layer, a second insulating layer, a first gate electrode, a third insulating layer and a source-drain electrode layer arranged in sequence along a direction away from the substrate; the electrostatic protection unit includes a first protective layer, a third protective layer and a fourth protective layer arranged in sequence along a direction away from the substrate; wherein the first protective layer and the first insulating layer are arranged on the same layer, the third protective layer and the second insulating layer are arranged on the same layer, and the fourth protective layer and the first gate electrode are arranged on the same layer.

[0085] In an exemplary embodiment, the electrostatic protection unit also includes a sixth protection layer, and at least one of a second protection layer and a fifth protection layer; wherein the second protection layer and the first active layer are arranged on the same layer, the fifth protection layer and the third insulating layer are arranged on the same layer, and the sixth protection layer and the source-drain electrode layer are arranged on the same layer.

[0086] In an exemplary embodiment, in a direction away from the substrate, the light-emitting structure layer of the display area includes a flat layer and a light-emitting device arranged on the flat layer, and the electrostatic protection unit includes a seventh protection layer, an eighth protection layer, a ninth protection layer and a tenth protection layer arranged in sequence; the tip structure is located at the seventh protection layer, the eighth protection layer, the ninth protection layer and the tenth protection layer; wherein the seventh protection layer and the flat layer are arranged on the same layer, the eighth protection layer and the anode of the light-emitting device are arranged on the same layer, the ninth protection layer and the organic light-emitting layer of the light-emitting device are arranged on the same layer, and the tenth protection layer and the cathode of the light-emitting device are arranged on the same layer.

[0087] In an exemplary embodiment, the electrostatic protection unit further includes a first color film, a second color film and a third color film stacked in sequence; the third color film is located on a side of the seventh protection layer close to the substrate.

[0088] In an exemplary embodiment, the electrostatic protection unit further includes an electrostatic discharge transistor, and the electrostatic discharge transistor is disposed in the driving circuit layer.

[0089] In an exemplary embodiment, in a direction perpendicular to the substrate, the distance between the surface of the tenth protective layer away from the substrate and the substrate is a first distance, and the distance between the surface of the cathode away from the substrate and the substrate is a second distance; the difference between the first distance and the second distance is set to be greater than or equal to 2.7 microns and less than or equal to 6.6 microns.

[0090] In an exemplary embodiment, the top angle of the tip structure is set to be greater than or equal to 0 degrees and less than or equal to 160 degrees.

[0091] In an exemplary embodiment, the transition structure includes a tip serration, and an extension direction of the tip serration is located in a plane where the base is located.

[0092] Figure 6 FIG. 1 is a top view of a display substrate provided by an exemplary embodiment, and other structures of the display substrate are omitted for illustration. Figure 6As shown, the display substrate may include a display area 100 and a frame area 300 surrounding the display area 100, the frame area 300 includes a binding area 200 located on one side of the display area 100 along the second direction Y, and two circuit areas 301 respectively located on both sides of the display area 100 in the first direction X, and a gate driving circuit is arranged in the circuit area 301. The display area 100 includes at least a plurality of regularly arranged sub-pixels Pxij, and the plurality of sub-pixels Pxij may include a plurality of sub-pixel rows arranged along the first direction X and a plurality of sub-pixel columns arranged along the second direction Y. The display substrate includes a plurality of gate lines 310, a single gate line 310 may be connected to a plurality of sub-pixels Pxij in a single sub-pixel row, and connected to the gate driving circuit, and the plurality of gate lines 310 are configured to provide gate signals to the plurality of sub-pixels Pxij. The display substrate includes a plurality of data lines 320. A single data line 320 can be connected to a plurality of sub-pixels Pxij in a single sub-pixel column and connected to the binding area 200. The plurality of data lines 320 can be connected to an integrated circuit disposed in the binding area 200 to provide data signals to the plurality of sub-pixels Pxij. The display substrate includes at least one electrostatic protection unit 302. The electrostatic protection unit 302 is located in the frame area 300 and is connected to the gate line 310. The electrostatic protection unit 302 includes at least one tip structure. The extension direction of the tip structure intersects with the plane where the display area 100 is located. The tip structure is configured to release static electricity during the preparation process of the display substrate, which helps to improve the yield of the transistor of the display substrate during the preparation process and can improve the display effect.

[0093] In an exemplary embodiment, the electrostatic protection unit 302 may be disposed between the circuit area 301 and the display area 100. In other embodiments, at least one electrostatic protection unit 302 may be disposed to surround the circuit area 301 and the display area 100, and the present invention is not limited thereto. The electrostatic protection unit 302 may release the static electricity generated by the display area 100 and the circuit area 301 during the preparation process, and may not only release the static electricity of the transistors in the display area 100, but may also release the static electricity of the transistors in the gate drive circuit of the circuit area 301.

[0094] In an exemplary embodiment, the display area 100 may be rectangular, and four electrostatic protection units 302 may be disposed at four corners of the display area 100 . Alternatively, the number and distribution of the electrostatic protection units 302 may be set as required, which is not limited in the present invention.

[0095] Figure 7 A top view of a display substrate is provided for yet another exemplary embodiment, in which other structures of the display substrate are omitted for illustration. Figure 7 and Figure 6 The difference between the two is the number and distribution of the electrostatic protection units 302. The rest of the structure can refer to the above description. Figure 6The description of is not repeated here. Figure 7 As shown, a plurality of electrostatic protection units 302 may be arranged around the display area 100, and the plurality of electrostatic protection units 302 may be evenly distributed around the display area 100. By increasing the number of electrostatic protection units 302 and evenly distributing the plurality of electrostatic protection units 302, it helps to improve the electrostatic discharge effect and avoid static electricity accumulation in the display substrate, thereby improving the display effect of the display substrate.

[0096] Figure 8 In an exemplary embodiment Figure 6 The enlarged view of the dotted line area E of FIG. 2 , omitting other structures of the display substrate. Figure 8 As shown, a gate line 310 may include a first line segment 311, a second line segment 312 and a third line segment 313, wherein the first line segment 311 and the second line segment 312 are located in the frame area 300, and the third line segment 313 is located in the display area 100, and at least one electrostatic protection unit 302 is connected to at least one of the first line segment 311 or the second line segment 312. The display substrate further includes a switching structure 314, which is located between the first line segment 311 and the second line segment 312 and connects the first line segment 311 and the second line segment 312. For example, the first line segment 311 and the second line segment 312 may be located in different conductive layers arranged in a direction away from the substrate, and may be connected through the switching structure 314. At least one electrostatic protection unit 302 may be distributed on the same side or both sides of the switching structure 314 along the first direction X, and the utility model does not limit this.

[0097] In an exemplary embodiment, the electrostatic protection unit 302 located on adjacent gate lines 310 may be disposed between the two adjacent gate lines 310; or, a plurality of electrostatic protection units 302 may be located on the same side of the gate line 310 connected to the same gate line 310 along the second direction Y; or, a plurality of electrostatic protection units 302 connected to the first line segment 311 may be located on one side of the first line segment 311 in the second direction Y, and a plurality of electrostatic protection units 302 connected to the second line segment 312 may be located on the other side of the second line segment 312 in the second direction Y, and the present invention does not impose any restrictions on this. Two gate lines 310 being adjacent means that no other gate lines are included between the two gate lines 310. Figure 8 Two adjacent gate lines 310 are shown in the figure. The gate line 310 located at the top along the second direction Y can be called the first gate line, and the other can be called the second gate line. The electrostatic protection unit connected to the first line segment of the first gate line and the electrostatic protection unit connected to the first line segment of the second gate line can be located between the first gate line and the second gate line at the same time. The electrostatic protection unit connected to the second line segment of the first gate line and the electrostatic protection unit connected to the second line segment of the second gate line can be located between the first gate line and the second gate line at the same time. The utility model does not impose any restriction on this.

[0098] In an exemplary embodiment, the transition structure 314 may include at least one tip serration 333 , and the extension direction of the tip serration 333 may be located within the plane where the substrate is located. Figure 8 The figure shows that a plurality of tip saw teeth 333 are provided on both sides of the adapter structure 314 along the second direction Y. Any number of tip saw teeth 333 can be provided on at least one side of the adapter structure 314 along the second direction Y as required. By providing the tip saw teeth, static electricity can be discharged in the plane where the tip saw teeth are located, which helps to improve the static electricity discharge effect in the process of preparing the display substrate.

[0099] In an exemplary embodiment, the first line segment 311 and the second line segment 312 are respectively located in different conductive layers arranged in a direction away from the substrate, and the tip serration 333 of the transition structure 314 can be arranged in the same layer as at least one of the first line segment 311 or the second line segment 312 .

[0100] Fig. 9 In an exemplary embodiment Figure 6 The BB-direction cross-sectional view of the display substrate is omitted and other structures of the display substrate are shown. Fig. 9 As shown, the display substrate may include a base 10 and a driving circuit layer disposed on the base 10 , the driving circuit layer of the display area 100 may include a plurality of circuit units, and the electrostatic protection unit 302 may be disposed in the driving circuit layer of the frame area 300 . Fig. 9, a first transistor K1 of a single pixel driving circuit is schematically shown, and the first transistor K1 may include a light shielding electrode 11, a first active layer 13, a first gate electrode 15, a first source electrode 17, and a first drain electrode 18. The electrostatic protection unit 302 may be prepared together with the first transistor K1, and the electrostatic protection unit 302 may include, for example, a first protective layer 22, a second protective layer 23, a third protective layer 24, a fourth protective layer 25, a fifth protective layer 26, and a sixth protective layer 27, which are sequentially arranged on the side of the light shielding portion 21 away from the substrate 10, wherein the first protective layer 22 may be arranged in the same layer as the first insulating layer 12, the second protective layer 23 may be arranged in the same layer as the first active layer 13, the third protective layer 24 may be arranged in the same layer as the second insulating layer 14, the fourth protective layer 25 may be arranged in the same layer as the first gate electrode 15, the fifth protective layer 26 may be arranged in the same layer as the third insulating layer 16, and the sixth protective layer 27 may be arranged in the same layer as the first source electrode 17 and the first drain electrode 18. The light shielding portion 21 may be arranged in the same layer as the light shielding electrode 11. In the process of preparing the display substrate, for example, when depositing inorganic film layers and performing dry etching, static electricity is generated due to the action of plasma. By simultaneously preparing the electrostatic protection unit 302 in the frame area 300, the electrostatic protection unit 302 includes a plurality of tip structures, which can concentrate the static electricity in the preparation process at the tip of the electrostatic protection unit for release, thereby avoiding the accumulation of static electricity in the display substrate during the preparation process, improving the yield of the transistors of the display substrate during the preparation process, and improving the display effect.

[0101] In an exemplary embodiment, the electrostatic protection unit 302 may only include the first protection layer 22 , the third protection layer 24 and the fourth protection layer 25 , and other protection layers may be provided as required, which is not limited in the present invention.

[0102] In an exemplary embodiment, the first line segment 311 can be set in the same layer as the first gate electrode 15, the second line segment 312 can be set in the same layer as the first source electrode 17 or the first drain electrode 18, and the tip serration 333 of the transfer structure 314 can be set in the same layer as at least one of the first line segment 311 or the second line segment 312.

[0103] Fig.10 for Fig. 9 The cross-sectional view of the tip structure of the electrostatic protection unit in FIG. 2 , omitting other structures of the display substrate. Fig.10 As shown, the electrostatic protection unit 302 may include at least one tip structure, Fig.10The middle dashed line indicates the extension direction of the tip structure. In an exemplary embodiment, the extension direction of the tip structure may be perpendicular to the plane where the substrate 10 is located. The tip structure may have a vertex angle a, which is the angle between the tip structure and the substrate 10. The vertex angle a may be set to be greater than or equal to 0 degrees and less than or equal to 160 degrees. The smaller the vertex angle a, the sharper the tip structure. The vertex angles a of different tip structures may be equal or different. The number of tip structures included in the electrostatic protection unit 302 and the size of the vertex angle a of a single tip structure may be set as needed, and the present invention does not limit this.

[0104] The following is an exemplary description of the preparation process of the display substrate. The "patterning process" mentioned in the utility model includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating, and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited by the utility model. "Thin film" refers to a layer of thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The term "A and B are arranged in the same layer" in the present invention means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present invention, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0105] In an exemplary embodiment, Fig. 9 The manufacturing process of the display substrate shown may include the following steps.

[0106] (1) Forming a light shielding layer pattern. In an exemplary embodiment, forming a light shielding layer pattern may include:

[0107] A first conductive film is deposited on the substrate 10, and the first conductive film is patterned by a patterning process to form a light shielding layer pattern in the display area 100 and the frame area 300. The light shielding layer pattern in the display area 100 may include at least a light shielding electrode 11, and the light shielding layer pattern in the frame area 300 may include at least a light shielding portion 21. Fig.11shown.

[0108] In an exemplary embodiment, the light shielding electrode 11 may be used as a gate electrode of a first transistor to be formed later, and also has the function of shielding the first transistor from light. In an exemplary embodiment, the first transistor may be, for example, a driving transistor.

[0109] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. The rigid substrate may be made of materials such as glass or quartz, and the flexible substrate may be made of materials such as polyimide (PI). The flexible substrate may be a single-layer structure, or may be a laminated structure consisting of an inorganic material layer and a flexible material layer, which is not limited in the present invention. The light-shielding layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0110] (2) Forming a first insulating layer pattern. In an exemplary embodiment, forming the first insulating layer pattern may include:

[0111] A first insulating film is deposited on the substrate 10 formed with the above pattern, and the first insulating film located in the frame area 300 is patterned by a patterning process to form a first insulating layer pattern. The first insulating layer pattern may include a first insulating layer 12 located in the display area 100 and a first protective layer 22 located in the frame area 300. The first insulating layer 12 may cover the substrate 10 and have a flat surface. The surface of the first protective layer 22 may have a plurality of protruding tips, such as Fig.12 shown.

[0112] In an exemplary embodiment, a micro lens array (MLA) process may be used to form an uneven structure on the first insulating film in the frame region 300 . The cross-sectional shape of the uneven structure may be, for example, a sawtooth shape.

[0113] In an exemplary embodiment, the material of the first insulating film may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, double layer or multi-layer structure. The first insulating layer 12 may be called a buffer layer.

[0114] (3) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include:

[0115] A semiconductor film is deposited on the substrate 10 having the above pattern, and the semiconductor film is patterned by a patterning process to form a semiconductor layer pattern. The semiconductor layer pattern may include at least a first active layer 13 located in the display area 100 and a second protective layer 23 located in the frame area 300, such as Fig.13 The semiconductor film deposited in the frame region 300 can maintain the surface shape of the first protective layer 22 , so that the second protective layer 23 can be formed in the frame region 300 .

[0116] In an exemplary embodiment, an orthographic projection of the first active layer 13 on the substrate 10 may be located within a range of an orthographic projection of the light shielding electrode 11 on the substrate 10 .

[0117] In an exemplary embodiment, the semiconductor layer may be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), etc., and the present invention is not limited thereto.

[0118] (4) Forming a gate layer pattern. In an exemplary embodiment, forming a gate layer pattern may include:

[0119] On the substrate 10 formed with the above pattern, a second insulating film and a second conductive film are sequentially deposited, and the second conductive film of the display area 100 is patterned by a patterning process to form a second insulating layer 14 and a gate layer pattern disposed on the second insulating layer 14 in the display area 100. The gate layer pattern of the display area 100 includes at least a first gate electrode 15. The second insulating film and the second conductive film deposited in the frame area 300 can maintain the surface shape of the first protective layer 22, thereby forming a third protective layer 24 and a fourth protective layer 25 in the frame area 300, as shown in FIG. Fig.14 shown.

[0120] Subsequently, the first active layer 13 may be subjected to conductor processing by using the first gate electrode 15 as a shield, and the present invention does not impose any limitation on this.

[0121] In an exemplary embodiment, the second insulating layer film may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, double layer or multilayer structure. The second insulating layer 14 may be referred to as a gate insulating (GI) layer.

[0122] (5) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include:

[0123] A third insulating film is deposited on the substrate 10 formed with the above pattern, and the third insulating film in the display area 100 is patterned by a patterning process to form a third insulating layer 16 in the display area 100. The third insulating film deposited in the frame area 300 can maintain the surface shape of the fourth protective layer 25, thereby forming a fifth protective layer 26 in the frame area 300. The third insulating layer 16 may include at least two active vias, and the two active vias may respectively expose the two ends of the first active layer 13, such as Fig.15 shown.

[0124] Since the fourth protection layer 26 in the frame region 300 has a pointed structure, static electricity generated in the first gate electrode 15 in this step can be released from the tip located in the frame region 300 of the display substrate, thereby avoiding static electricity accumulation in the first gate electrode 15 .

[0125] In an exemplary embodiment, the second insulating layer film may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, double layer or multi-layer structure. The third insulating layer 16 may be referred to as an interlayer insulating (ILD) layer.

[0126] (6) Forming a source-drain electrode layer pattern. In an exemplary embodiment, forming the source-drain electrode layer may include:

[0127] A third conductive film is deposited on the substrate 10 formed with the above pattern, and the third conductive film is patterned by a patterning process to form a source-drain electrode layer pattern in the display area 100. The source-drain electrode layer pattern includes at least a first source electrode 17 and a first drain electrode 18, and the first source electrode 17 and the first drain electrode 18 are connected to the two ends of the first active layer 13 through two active vias, respectively. The third conductive film deposited in the frame area 300 can maintain the surface shape of the fifth protective layer 26, thereby forming a sixth protective layer 27 in the frame area 300, as shown in FIG. Fig. 9 shown.

[0128] In an exemplary embodiment, the source-drain electrode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0129] Subsequently, a passivation layer, a light-emitting structure layer, a packaging structure layer and other structures can be further formed on the substrate 10 on which the above-mentioned pattern is formed. The static electricity generated during these preparation processes can be released through the electrostatic protection unit 302 located in the frame area 300, which can improve the yield of transistors when preparing the display substrate. In the subsequent preparation process, the electrostatic protection unit 302 can form more protection layers, or the present invention does not limit this.

[0130] Fig.16 In yet another exemplary embodiment Figure 6 The BB-direction cross-sectional view of the display substrate is omitted and other structures of the display substrate are shown. Fig.16 As shown, the display substrate may include a substrate 10, a driving circuit layer 102 disposed on the substrate 10, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 10, and a packaging structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 10. The driving circuit layer 102 in the frame area 300 may be provided with an electrostatic discharge transistor K2, and the electrostatic discharge transistor K2 may be prepared synchronously with the first transistor K1 in the driving circuit layer 102 in the display area 100. Fig.16 The reference numerals of some film layers are omitted in the figure. Fig. 9 The description is omitted here. The driving circuit layer 102 may also include a passivation layer 30 arranged on the side of the source and drain electrode layer away from the substrate 10. In the direction away from the substrate 10, the light-emitting structure layer 103 of the display area 100 may include a color filter layer, a flat layer 34, an anode layer 35, a pixel definition layer 36, an organic light-emitting layer 37 and a cathode layer 38 arranged in sequence, and the anode layer 35 may be connected to the drain electrode of the corresponding first transistor K1 through a via hole. The color filter layer may include color filters of multiple different colors. Taking the display substrate including three sub-pixels of different colors as an example, the color filter layer may include a first color filter 31, a second color filter 32 and a third color filter 33, and color filters of different colors are respectively located in sub-pixel areas of different colors. In the direction away from the substrate 10, the light-emitting structure layer 103 of the border area 300 may include a color film layer, a seventh protective layer 40, an eighth protective layer 41, a ninth protective layer 42 and a tenth protective layer 43 arranged in sequence, wherein the color film layer of the border area 300 may include a first color film 31, a second color film 32 and a third color film 33 stacked in sequence, the seventh protective layer 40 may be arranged on the same layer as the flat layer 34, the eighth protective layer 41 may be arranged on the same layer as the anode layer 35, the ninth protective layer 42 may be arranged on the same layer as the organic light-emitting layer 37, the tenth protective layer 43 may be arranged on the same layer as the cathode layer 38, and the seventh protective layer 40, the eighth protective layer 41, the ninth protective layer 42 and the tenth protective layer 43 may include multiple tip structures.

[0131] like Fig.16As shown, the electrostatic protection unit 302 may include an electrostatic discharge transistor K2, a passivation layer 30, a first color film 31, a second color film 32 and a third color film 33 stacked in sequence, and a seventh protection layer 40, an eighth protection layer 41, a ninth protection layer 42 and a tenth protection layer 43. Fig.16 As shown, in the direction perpendicular to the substrate 10, the distance between the surface of the tenth protective layer 43 away from the substrate 10 side (i.e., the tip position) and the substrate 10 is a first distance H1, and the distance between the surface of the cathode layer 38 away from the substrate 10 side and the substrate 10 is a second distance H2. In an exemplary embodiment, the difference between the first distance H1 and the second distance H2 can be set to be greater than or equal to 2.7 microns and less than or equal to 6.6 microns. For example, the difference between the first distance H1 and the second distance H2 can be set to be greater than or equal to 3 microns and less than or equal to 6 microns. This height difference makes the tip of the tenth protective layer 43 at a higher position from the substrate 10, which can play a role similar to a lightning rod. In the preparation process of the display substrate, the static electricity of each film layer can be concentratedly released through the multiple tip structures of the electrostatic protection unit 302, thereby improving the yield of the transistor.

[0132] exist Fig.16 In the preparation process of the display substrate shown in the figure, after forming the passivation layer 30, the first color film 31, the second color film 32 and the third color film 33 can be formed in the display area 100 in sequence, and the multiple color film layers in the frame area 300 are retained, and then a flat film is coated to form a flat layer 34 in the display area 100. In the frame area 300, a plurality of tip structures can be formed on the surface of the flat film by using the MLA process to form the seventh protective layer 40. The eighth protective layer 41, the ninth protective layer 42 and the tenth protective layer 43 formed subsequently can maintain the surface morphology of the seventh protective layer 40. The preparation process can refer to the above description of Fig. 9 The description of the preparation process will not be repeated here.

[0133] The embodiment of the utility model further provides a display device, including the display substrate described in any of the above embodiments. The display device can be: an OLED display, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function, and the embodiment of the utility model is not limited thereto.

[0134] Although the implementation methods disclosed in the utility model are as above, the above contents are only implementation methods adopted to facilitate the understanding of the utility model, and are not used to limit the utility model. Any technician in the field to which the utility model belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the utility model, but the scope of patent protection of the utility model shall still be defined by the attached claims.

Claims

1. A display substrate, characterized in that: include: A substrate, comprising a display area and a frame area surrounding the display area; A plurality of sub-pixels are located in the display area; a plurality of gate lines, located in the display area and the frame area and electrically connected to the plurality of sub-pixels, the plurality of gate lines being configured to provide gate signals to the plurality of sub-pixels; A gate driving circuit is located in the frame area and connected to the plurality of gate lines; At least one electrostatic protection unit is located in the frame area and connected to the gate line, and the at least one electrostatic protection unit is configured to release static electricity on the display substrate during the preparation process. The electrostatic protection unit includes at least one tip structure, and the extension direction of the tip structure intersects with the plane where the base is located.

2. The display substrate according to claim 1, characterized in that: One of the plurality of gate lines comprises a first line segment, a second line segment and a third line segment, the first line segment and the second line segment are located in the frame area, the third line segment is located in the display area, and the at least one electrostatic protection unit is connected to at least one of the first line segment or the second line segment; The display substrate further includes a transition structure, which is located between the first line segment and the second line segment and connects the first line segment and the second line segment.

3. The display substrate according to claim 2, characterized in that: The number of the at least one electrostatic protection unit is multiple, and the multiple electrostatic protection units are respectively located on both sides of the switching structure and are respectively connected to the first line segment and the second line segment.

4. The display substrate according to claim 2, characterized in that: The plurality of gate lines include a first gate line and a second gate line, wherein the first gate line and the second gate line are adjacent to each other; The electrostatic protection unit connected to the first line segment of the first gate line and the electrostatic protection unit connected to the first line segment of the second gate line are both located between the first gate line and the second gate line; and / or, The electrostatic protection unit connected to the second line segment of the first gate line and the electrostatic protection unit connected to the second line segment of the second gate line are both located between the first gate line and the second gate line.

5. The display substrate according to claim 1, characterized in that: The top angle of the tip structure is set to be greater than or equal to 0 degree and less than or equal to 160 degrees.

6. The display substrate according to claim 5, characterized in that: The electrostatic protection unit includes a plurality of the tip structures, and at least some of the tip structures in the plurality of the tip structures have the same top angle.

7. The display substrate according to claim 1, characterized in that: The extending direction of the tip structure is perpendicular to the plane where the base is located.

8. The display substrate according to claim 3, characterized in that: The display substrate includes a driving circuit layer arranged on the base, and a light-emitting structure layer arranged on a side of the driving circuit layer away from the base. The sub-pixel includes a pixel circuit and a light-emitting element. The pixel circuit drives the light-emitting element to emit light. The pixel circuit is located in the driving circuit layer, and the light-emitting element is located in the light-emitting structure layer.

9. The display substrate according to claim 8, characterized in that: The driving circuit layer of the display area comprises a first insulating layer, a first active layer, a second insulating layer, a first gate electrode, a third insulating layer and a source-drain electrode layer which are sequentially arranged in a direction away from the substrate; The electrostatic protection unit comprises a first protection layer, a third protection layer and a fourth protection layer which are sequentially arranged in a direction away from the substrate; The first protective layer and the first insulating layer are arranged on the same layer, the third protective layer and the second insulating layer are arranged on the same layer, and the fourth protective layer and the first gate electrode are arranged on the same layer.

10. The display substrate according to claim 9, characterized in that: The electrostatic protection unit further includes a sixth protection layer, and at least one of the second protection layer and the fifth protection layer; Among them, the second protective layer and the first active layer are arranged in the same layer, the fifth protective layer and the third insulating layer are arranged in the same layer, and the sixth protective layer and the source-drain electrode layer are arranged in the same layer.

11. The display substrate according to claim 9, characterized in that: The driving circuit layer of the display area also includes a light-shielding electrode, which is located on a side of the first insulating layer close to the substrate; the frame area includes a light-shielding portion arranged in the same layer as the light-shielding electrode, and the light-shielding portion is located on a side of the electrostatic protection unit close to the substrate.

12. The display substrate according to claim 9, characterized in that: In a direction away from the substrate, the light emitting structure layer of the display area includes a flat layer and a light emitting device arranged on the flat layer, the electrostatic protection unit includes a seventh protection layer, an eighth protection layer, a ninth protection layer and a tenth protection layer arranged in sequence; the tip structure is located in the seventh protection layer, the eighth protection layer, the ninth protection layer and the tenth protection layer; Among them, the seventh protective layer and the flat layer are arranged on the same layer, the eighth protective layer and the anode of the light-emitting device are arranged on the same layer, the ninth protective layer and the organic light-emitting layer of the light-emitting device are arranged on the same layer, and the tenth protective layer and the cathode of the light-emitting device are arranged on the same layer.

13. The display substrate according to claim 12, characterized in that: The electrostatic protection unit further includes a first color film, a second color film and a third color film which are stacked in sequence; the third color film is located on a side of the seventh protection layer close to the substrate.

14. The display substrate according to claim 13, characterized in that: The electrostatic protection unit further includes an electrostatic release transistor, and the electrostatic release transistor is arranged on the driving circuit layer.

15. The display substrate according to claim 14, characterized in that: In a direction perpendicular to the substrate, the distance between the surface of the tenth protective layer away from the substrate and the substrate is a first distance, and the distance between the surface of the cathode away from the substrate and the substrate is a second distance; the difference between the first distance and the second distance is set to be greater than or equal to 2.7 microns and less than or equal to 6.6 microns.

16. The display substrate according to claim 2, characterized in that: The transition structure comprises a tip sawtooth, and the extension direction of the tip sawtooth is located in the plane where the base is located.

17. A display device, characterized in that: The invention comprises the display substrate as claimed in any one of claims 1 to 16.

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